Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
1. This action is in response to the application filed 10/17/2022.
2. Claims 1-23 have been examined and are pending in the application.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claims 1-3, 7, 13-15, 17 and 20-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Iyer U.S Patent No. 11,281,602.
As to claim 1, Iyer teaches a method comprising:
receiving a request for a chained accelerator operation; and configuring a chain of accelerators to perform the chained accelerator operation (…The chained operations are invoked when a first SDXI command705 is provided to SDXI hardware device710 and a second SDXI command707 is provided to SDXI hardware device715…, lines 10-13 column 11), including:
configuring a first accelerator to access an input data from a source memory location in system memory, process the input data, and generate first intermediate data (…When SDXI hardware device710receives SDXI command705, the SDXI hardware device proceeds to retrieve the source data from source buffer722 in accordance with the contents of the source address in the SDXI command, and directs compress engine712 to compress the data. SDXI hardware device710 continues to write the compressed data to intermediate buffer724…, lines 43-50 column 11); and
configuring a second accelerator to receive the first intermediate data, without the first intermediate data having been sent to the system memory, process the first intermediate data, and generate additional data (…when SDXI hardware device715 receives the completion indication, the SDXI hardware device proceeds to retrieve the compressed data from intermediate buffer724 in accordance with the contents of the source address in SDXI command707, and directs encrypt engine717 to encrypt the data. SDXI hardware device715 continues to write the encrypted data to destination buffer726 in accordance with the contents of the destination address in SDXI command707…, line 61 column 11 to line 2 column 12).
As to claim 2, Iyer further teaches configuring the first accelerator to store the first intermediate data to a storage (…to write the compressed data to intermediate buffer724…, lines 48-49 column 11); and
configuring the second accelerator to receive the first intermediate data from the storage (…the SDXI hardware device proceeds to retrieve the compressed data from intermediate buffer724…, lines 63-64 column 11).
As to claim 3, Iyer further teaches configuring the chain of accelerators further comprises configuring a subset of the storage to be used for the chained accelerator operation (buffers 722, 724 and 726, Fig. 7 and associated specifications).
As to claim 7, Iyer further teaches receiving the request from a process, and wherein configuring the chain of accelerators further comprises assigning a process space identifier (PASID) for the process to the chain of accelerators (…SDXI hardware driver318provides SDXI command500 to SDXI interface332. In a second step 504, SDXI hardware330 enacts the function of the compression descriptor to retrieve the source data from memory324, to compress the source data, and to return the compressed data to the memory…, lines 39-44 column 9).
As to claim 13, Iyer further teaches configuring different types of accelerators selected from a group consisting of a digital signal processors (DSP), a matrix accelerator, a tensor processing unit, an artificial intelligence (AI) accelerator, a data analytics accelerators, a cryptographic accelerator, a data compression and/or decompression accelerator, a storage accelerator, a network processors, an accelerator implemented as a Field Programmable Gate Array (FPGA), and an accelerator implemented as an Application Specific Integrated Circuit (ASIC) (…SDXI hardware330 may include accelerator blocks within a general purpose processor or processor family, such as a CPU or the like, a purpose specific processor, such as a GPU or the like, a logic-based device or state-based device, such as a FPGA, a Complex Programmable Logic Device (CPLD) or the like, a smart I/O device that provides in-line data processing in the course of I/O operations, such as a smart NIC, a Host Bus Adapter (HBA), a storage controller such as a RAID controller, a Network Attached Storage (NAS) device, a Storage Area Network (SAN) controller, or the like, or another processing device, as needed or desired. Here, it will be understood that, SDXI hardware330 may be configured to provide operations consistent with its type, but that are not specifically associated with its SDXI functionality. For example, where SDXI hardware330 represents a FPGA type of device, it will be understood that the FPGA device may be invoked to provide functionality of a more general nature, in addition to the SDXI functionality as described herein…., lines 28-6 column 5;… other accelerators may be utilized in providing combined commands similar to SDXI command500, such as decompress accelerators, encrypt/decrypt accelerators, deduplication accelerators, and the like…., lines 54-58 column 9).
As to claims 14-15, note the discussions of claims 1-2 above, respectively.
As to claim 17, note the discussion of claim 7 above.
As to claims 20-21, note the discussions of claims 1-2 above, respectively.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 4-6, 8-11, 16, 18-19 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Iyer in view of Zhao U.S Patent No. 10,728,091.
As to claim 4, Iyer does not teach analyzing characteristics of the first and second accelerators to determine that the first and second accelerators are sufficiently compatible for the chained accelerator operation.
Zhao teaches a system of data processing using a group of accelerators wherein the system analyzes characteristics of the accelerators to determine that the accelerators are sufficiently compatible for the operation (…to intelligently and dynamically provision accelerator devices (e.g., GPU device) in a way that optimizes resource usage. The term "dynamically" as used herein refers to provisioning functionalities that include (1) determining a current interconnection topology and current bandwidth usage of computing resources over a server cluster, and (2) utilizing performance scores of different topologies in conjunction with heuristic rules to determine an optimal set of accelerator devices to provision for a given HPC job. As demonstrated in further detail below, provisioning methods are configured to dynamically schedule and provision a set of accelerator devices (e.g., GPU devices) for a given job such that all or most of the accelerator devices within the set belong to a same interconnect domain, to 15thereby optimize performance and resource usage, while avoiding the scheduling and provisioning of a set of accelerator devices for the given job, which would require cross-domain interconnections, and result in potential waste of resources and degraded performance…, line 57 column 15 to line 9 column 16).
It would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to have modified Iyer reference to include the teachings of Zhao reference because by determining that the accelerators are sufficiently compatible for the operation, the system could optimize performance and resource usage, as disclosed by Zhao.
As to claim 5, Zhao further teaches analyzing the characteristics comprises analyzing bandwidth characteristics of the accelerators to determine that the accelerators are sufficiently compatible in bandwidth (…implements a dynamic "topology aware" and "bandwidth usage aware" computing resource provisioning method, which utilizes information in the topology database146 and the resource usage database148 to dynamically schedule and provision computing resources 30(e.g., G devices164) within the heterogeneous server cluster160 for executing pending jobs…, lines 5-11 column 6). Note the discussion of claim 4 above for the reason of combining references.
As to claim 6, Iyer as modified further teaches analyzing characteristics of the first and second accelerators to determine that the first and second accelerators are both capable of using a same storage (memory 720, Fig. 7 and associated specifications) to store the first intermediate data.
As to claim 8, Iyer does not teach identifying a bottleneck during performance of the chained accelerator operation;
identifying a change to the chain of accelerators to address the bottleneck; and
making the change to the chain of accelerators.
Zhao teaches a system of data processing using a group of accelerators wherein the system identifying a bottleneck during performance of the accelerator operation; identifying a change to the accelerators to address the bottleneck; and making the change to the accelerators (…During execution of the workload, the current bandwidth usage of the communication links between the provisioned GPU devices can be periodically tracked (e.g., every 5 seconds) to determine if there is possible communication overload or bottleneck, and then possibly modify the logical communication order of the GPU devices to optimize the communication…, lines 54-60 column 20).
It would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to have modified Iyer reference to include the teachings of Zhao reference because by identifying a bottleneck and making the change to the accelerators, the system could optimize performance and resource usage, as disclosed by Zhao.
As to claim 9, Zhao further teaches analyzing operational data collected during the performance of the chained accelerator operation (…During execution of the workload, the current bandwidth usage of the communication links between the provisioned GPU devices can be periodically tracked…, lines 54-57 column 20). Note the discussion of claim 8 above for the reason of combining references.
As to claim 10, Zhao further teaches identifying a set of accelerator resources to supplant or replace one of the first and second accelerators (…possibly modify the logical communication order of the GPU devices to optimize the communication…, lines 59-60 column 20). Note the discussion of claim 8 above for the reason of combining references.
As to claim 11, Iyer further teaches the first accelerator accesses the input data from the source memory location in the system memory, process the input data, and generate the first intermediate data (…When SDXI hardware device710receives SDXI command705, the SDXI hardware device proceeds to retrieve the source data from source buffer722 in accordance with the contents of the source address in the SDXI command, and directs compress engine712 to compress the data. SDXI hardware device710 continues to write the compressed data to intermediate buffer724…, lines 43-50 column 11), and the second accelerator receives the first intermediate data, process the first intermediate data, and generate the additional data (…when SDXI hardware device715 receives the completion indication, the SDXI hardware device proceeds to retrieve the compressed data from intermediate buffer724 in accordance with the contents of the source address in SDXI command707, and directs encrypt engine717 to encrypt the data. SDXI hardware device715 continues to write the encrypted data to destination buffer726 in accordance with the contents of the destination address in SDXI command707…, line 61 column 11 to line 2 column 12).
Iyer does not teach configuring a set of virtual accelerator resources of the first accelerator, and configuring a set of virtual accelerator resources of the second accelerator.
Zhao teaches a system of data processing using a group of accelerators wherein the system configures a set of virtual accelerator resources of the accelerators (…The virtualization resources708 can be instantiated to execute one or more applications or functions which are hosted by the GPU server node700 …, lines 23-25 column 22).
It would have been obvious before the effective filing date of the claimed invention to a person of ordinary skill in the art to have modified Iyer reference to include the teachings of Zhao reference because by configuring a set of virtual accelerator resources, the system could allow multiple virtual machines to share the resources, as disclosed by Zhao.
As to claim 16, note the discussion of claim 5 above.
As to claims 18-19, note the discussions of claims 8 and 11 above, respectively.
As to claims 22-23, note the discussions of claims 4 and 8 above, respectively.
Allowable Subject Matter
5. Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S Patent No. 11,550,585 discloses off-loading processing tasks from a host processor to an accelerator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andy Ho whose telephone number is (571) 272-3762. A voice mail service is also available for this number. The examiner can normally be reached on Monday – Friday, 8:30 am – 5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Kevin Young can be reached on (571) 270-3180.
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/Andy Ho/
Primary Examiner
Art Unit 2194