CTNF 17/968,744 CTNF 85403 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions The restriction requirement as set forth in the Office action mailed on 10/14/2025 has been withdrawn. Claims 1-13 and 22-30 are being examined. Claim Objections 07-29-01 AIA Claim 22 is objected to because of the following informalities: Lines 3 and 4 of claim 22 after the word “comprising” it should be a “:” and not a “;” . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1, 3, 13 and 22-30 are rejected under 35 U.S.C. 103 as being unpatentable over Majumdar et al. (US 2019/0189237 A1; hereinafter Majumdar) .. Regarding Claim 1. Majumdar (Fig.1-2) discloses a memory device, comprising: a memory array ([0027]) configured to store data; wherein the memory array comprises a plurality of storage cells (205-a; Fig.2; [0035]), wherein the plurality of storage cells (205-a) comprise a first chalcogenide material composition ([0036]); and wherein the memory array comprises a plurality of memory cells (210-a; Fig.2; [0035]), wherein the plurality of memory cells (210-a) comprise a second chalcogenide material composition ([0037]). Majumdar ([0035]-[0037]) does not particularly disclose that the second chalcogenide material composition is different from the first chalcogenide material composition of the plurality of storage cells. However, Majumdar ( [0138]) discloses that chalcogenide material used for storage cell or memory cell can be chosen from all those variation Therefore it would have been obvious in the art before the effective filling of the application to have any desired chalcogenide material composition to enable a faster switching speed on a lower energy consumption. Regarding Claim 3.The memory device of claim 1, Majumdar ([0027] and Fig.1) discloses wherein the plurality of storage cells (205-a) and the plurality of memory cells (210-a) reside on a single chip. Regarding Claim 13. The memory device of claim 1, Majumdar does not particularly disclose wherein the first chalcogenide material composition comprises an chalcogenide alloy composition comprising 10 to 15% Indium and percentages of one or more of Selenium, Arsenic, and Germanium, and wherein the second chalcogenide material composition comprises a chalcogenide alloy composition comprising 5 to 10% Indium and percentages of one or more of Selenium, Arsenic, and Germanium. However, Majumdar teaches chalcogenide material of varying stoichiometries based on design ([0138]). Therefore, It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have any desired chalcogenide material to enable a faster switching speed with reduced programming currents and on a lower energy consumption since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. See MPEP 2144.05 . Regarding Claim 22, Majumdar (Fig.9) discloses a system, comprising: a host device ( 945/950; Fig.9; [0105]); and a memory device (920; Fig.9) comprising; a memory array (920, Fig. 9; 100, Fig. 1), the memory array comprising; a plurality of storage cells (205-a; Fig.2), wherein the plurality of storage cells comprise a first chalcogenide material composition ([0036]); and a plurality of memory cells (210-a), wherein the plurality of memory cells comprise a second chalcogenide material composition ([0037]), wherein the second chalcogenide material composition of the plurality of memory cells is different from the first chalcogenide material composition of the plurality of storage cells (see [0138] that discloses that chalcogenide material used for storage cell or memory cell can be chosen from all those variation). Regarding Claim 23. Majumdar (Fig.9) discloses a device, comprising: a memory array comprising: at least one storage cell (205-a) comprising a first chalcogenide material composition ([0036]); and at least one memory cell (210-a) comprising a second chalcogenide material composition ([0037]) different from the first chalcogenide material composition; and a controller (I/O Controller 935, Fig. 9) configured to receive data to be stored in the memory array (see [0138] that discloses that chalcogenide material used for storage cell or memory cell can be chosen from all those variation). Regarding Claim 24.The device of claim 23, Majumdar ([0026], [0031], [0045], [0142]) discloses wherein the device further comprises bias circuitry configured to apply voltages to the at least one memory cell, the at least one storage cell, or a combination thereof, when an operation is performed with respect to the memory array. Regarding Claim 25.The device of claim 24, Majumdar ([0099]-[0106] [0146]) discloses wherein the controller (935, Fig.9) is further configured to control the bias circuitry. Regarding Claim 26.The device of claim 23, Majumdar ([0002], [0045]) discloses wherein the device further comprises sensing circuitry configured to sense a current associated with the at least one memory cell, the at least one storage cell, or a combination thereof. Regarding Claim 27.The device of claim 26, Majumdar ([0002], [0045]) discloses wherein the sensing circuitry is further configured to determine a state of the at least one memory cell, the at least one storage cell, or a combination thereof. Regarding Claim 28. The device of claim 23, Majumdar does not particularly disclose wherein the first chalcogenide material composition comprises 10 to 15% Indium and percentages one or more of Selenium, Arsenic, and Germanium, and the second chalcogenide material composition comprises 5 to 10% Indium and percentages one or more of Selenium, Arsenic, and Germanium. However, Majumdar teaches chalcogenide material. Therefore, It would have been obvious to one having ordinary skill in the art at the time of the invention was made to have any desired chalcogenide material to enable a faster switching speed with reduced programming currents and on a lower energy consumption since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. See MPEP 2144.05 . Regarding Claim 29.The device of claim 23, Majumdar ([0036], [0065]) discloses wherein the at least one memory cell, the at least one storage cell, or a combination thereof, are configured to switch or snap when a sufficient voltage is applied across the at least one storage cell, or a combination thereof. Regarding Claim 30.The device of claim 23, Majumdar [0027] ) discloses wherein the at least one memory cell, the at least one storage cell, or a combination thereof, are arranged in a three-dimensional vertical architecture . 07-21-aia AIA Claim (s) 2, and 4-12 are rejected under 35 U.S.C. 103 as being unpatentable over Majumdar in view of Or-Bach et al. (US 2024/0404600 A1; hereinafter Or-Bach) . Regarding Claim 2. The memory device of claim 1, Majumdar does not particularly disclose wherein the memory array comprises a silicon layer and a plurality of alternating silicon dioxide and tungsten layers. Or-Bach (Figs.1-49; specifically Fig.35-36) discloses a memory device wherein the memory array comprises a silicon layer and a plurality of alternating silicon dioxide (Fig.35C) and tungsten layers ([0263], [0273]). Therefore, it would have been obvious in the art before the effective filing of the application to have silicon and silicon dioxide alternate with tungsten to maximize the storage capacity in the memory device. Regarding Claim 4. The memory device of claim 1, Majumdar does not particularly disclose a plurality of piers positioned in proximity to the plurality of storage cells and the plurality of memory cells, wherein the plurality of piers comprise polysilicon. Or-Bach (Figs.1-49; specifically Fig.35-36) discloses a memory device comprising a plurality of piers (Fig.35D-35G) positioned in proximity to the plurality of storage cells and the plurality of memory cells, wherein the plurality of piers comprise polysilicon ([0241]). Therefore, it would have been obvious in the art before the effective filing of the application to have plurality of piers to minimize the memory scale while maximizing the storage capacity. Regarding Claim 5.The memory device of claim 1, Majumdar does not particularly disclose first placeholder material positioned adjacent to the first chalcogenide material composition of the plurality of storage cells and to a first polysilicon pier of the memory array. Or-Bach (Figs.1-49; specifically Fig.35-36) discloses a memory device comprising first placeholder material (Fig.35H) positioned adjacent to the plurality of storage cells and to a first polysilicon pier of the memory array. Therefore, it would have been obvious in the art before the effective filing of the application to have plurality of piers to minimize the memory scale while maximizing the storage capacity. Regarding Claim 6.The memory device of claim 5, Majumdar does not particularly disclose second placeholder material adjacent to the second chalcogenide material composition of the plurality of memory cells and to a second polysilicon pier of the memory array. Or-Bach (Figs.1-49; specifically Fig.35-36) discloses a memory device comprising first placeholder material (Fig.35H) positioned adjacent to the plurality of storage cells and to a first polysilicon pier of the memory array. Therefore, it would have been obvious in the art before the effective filing of the application to have plurality of piers to minimize the memory scale while maximizing the storage capacity. Regarding Claim 7. The memory device of claim 1, Majumdar does not particularly disclose comprising a top electrode in a structure of the memory array, wherein the top electrode surrounds bitlines of the memory array. Or-Bach (Figs.1-49; specifically Fig.35-36) discloses a memory device comprising a top electrode in a structure of the memory array, wherein the top electrode surrounds bitlines of the memory array. Therefore, it would have been obvious in the art before the effective filing of the application to have such memory structure to minimize the memory scale while maximizing the storage capacity and hence improve efficiency. Regarding Claim 8. The memory device of claim 1, Majumdar does not particularly disclose a bottom electrode in a structure of the memory array, wherein the bottom electrode is in contact with the first chalcogenide material composition, the second chalcogenide material composition, or a combination thereof. Or-Bach (Figs.1-49; specifically Fig.35-36) discloses a bottom electrode in a structure of the memory array, wherein the bottom electrode (Fig.35H) is in contact with the first material composition, the second chalcogenide material composition, or a combination thereof. Therefore, it would have been obvious in the art before the effective filing of the application to have such memory structure to minimize the memory scale while maximizing the storage capacity and hence improve efficiency. Regarding Claim 9. The memory device of claim 1, Majumdar does not particularly disclose a plurality of bitlines positioned in proximity to a plurality of piers of the memory array, a top electrode, the first chalcogenide material composition, the second chalcogenide composition, or a combination thereof, wherein the plurality of bitlines comprise tungsten. Or-Bach (Figs.1-49; specifically Fig.35-36; Fig.35H) discloses a plurality of bitlines positioned in proximity to a plurality of piers of the memory array, a top electrode, the first chalcogenide material composition, the second chalcogenide composition, or a combination thereof, wherein the plurality of bitlines comprise tungsten ([0311]). Therefore, it would have been obvious in the art before the effective filing of the application to have such memory structure to minimize the memory scale while maximizing the storage capacity and hence improve efficiency. Regarding Claim 10. The memory device of claim 1, Majumdar does not particularly disclose a plurality of wordlines in contact with a bottom electrode and a plurality of piers of the memory array, wherein the plurality of wordlines comprise tungsten. Or-Bach (Figs.1-49; specifically Fig.35-36; Fig.35H, [0236], [0241]) discloses a plurality of wordlines in contact with a bottom electrode and a plurality of piers of the memory array, wherein the plurality of wordlines comprise tungsten ([0311]) Regarding Claim 11. The memory device of claim 1, Majumdar does not particularly disclose a sealing material to seal the memory cells, the storage cells, or a combination thereof, within a structure of the memory array. Or-Bach (Figs.1-49; specifically Fig.35-36) discloses a sealing material to seal the memory cells ([0246]), the storage cells, or a combination thereof, within a structure of the memory array. Therefore, it would have been obvious in the art before the effective filing of the application to have such memory structure to minimize the memory scale while maximizing the storage capacity and hence improve efficiency. Regarding Claim 12. The memory device of claim 1, Majumdar does not particularly disclose wherein the plurality of memory cells and the plurality of storage cells are configured to be independently addressed based on wordline and bitline selection. Or-Bach (Figs.1-49; specifically Fig.35-36; Fig.35H) discloses a plurality of memory cells and the plurality of storage cells are configured to be independently addressed based on wordline and bitline selection ([0236]). Therefore, it would have been obvious in the art before the effective filing of the application to have such memory structure to minimize the memory scale while maximizing the storage capacity and hence improve efficiency. Conclusion 07-100 Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866- 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAJAR KOLAHDOUZAN/ Examiner, Art Unit 2898 /Leonard Chang/ Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 17/968,744 Page 2 Art Unit: 2898 Application/Control Number: 17/968,744 Page 3 Art Unit: 2898 Application/Control Number: 17/968,744 Page 4 Art Unit: 2898 Application/Control Number: 17/968,744 Page 5 Art Unit: 2898 Application/Control Number: 17/968,744 Page 6 Art Unit: 2898 Application/Control Number: 17/968,744 Page 7 Art Unit: 2898 Application/Control Number: 17/968,744 Page 8 Art Unit: 2898 Application/Control Number: 17/968,744 Page 9 Art Unit: 2898 Application/Control Number: 17/968,744 Page 10 Art Unit: 2898 Application/Control Number: 17/968,744 Page 11 Art Unit: 2898 Application/Control Number: 17/968,744 Page 12 Art Unit: 2898
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