DETAILED ACTION
This action is made FINAL in response to the amendments filed on 1/13/2026.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 – 10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As to claims 1 and 6,
Step 2A, Prong One
The claim recites in part:
determining a first reduction engine of a plurality of reduction engines corresponding to a plurality of computing cores comprised in a current die to function as a die reduction engine;
in response to receiving a plurality of pieces of data to be reduced and a plurality of synchronization indicators from the plurality of computing cores in the plurality of dies, performing, by the first reduction engine in the current die, a reduction operation on the plurality of pieces of data to be reduced to generate a reduction computing result,
Under the broadest reasonable interpretation, these limitations are process steps that cover mental processes including an observation, evaluation, judgment or opinion that could be performed in the human mind or with the aid of pencil and paper. If a claim, under its broadest reasonable interpretation, covers a mental process but for the recitation of generic computer components, then it falls within the “Mental Process” grouping of abstract ideas. Accordingly, at Step 2A, Prong One, the claim is directed to an abstract idea.
Step 2A, Prong Two
The judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements of:
sending, by each computing core in the plurality of computing cores, data to be reduced and a synchronization indicator to the plurality of first reduction engines in the plurality of dies, wherein the synchronization indicator follows the data to be reduced;
sending, by the first reduction engine in the current die, synchronization acknowledgments to the plurality of computing cores the current die;
which amounts to extra-solution activity of gathering data for use in the claimed process. As described in MPEP 2106.05(g), limitations that amount to merely adding insignificant extra-solution activity to a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application.
The claim further recites:
in response to receiving the synchronization acknowledgment from the first reduction engine in the current die, and not receiving synchronization acknowledgements from other dies, reading, by each computing core of the plurality of computing cores in the current die, the reduction computing result from the first reduction engine in the current die.
these elements are recited at a high-level of generality and amounts to no more than adding the words “apply it” to the judicial exception. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea (See MPEP 2106.05(f)). These limitations also amount to extra solution activity because it is a mere nominal or tangential addition to the claim, amounting to mere data output (see MPEP 2106.05(g)).
The claim further recites dies, reduction engines, die reduction engine, computing cores, and synchronization indicator which are recited at a high-level of generality and amounts to no more than mere instructions to apply the exception using a generic computer component (See MPEP 2106.05(f)).
In addition, the recitation of synchronization indicator and reduction computing result amounts to generally linking the use of the judicial exception to a particular environment of field of use (See MPEP 2106.05(h)). As such, the claim does not integrate the judicial exception into a practical application.
Accordingly, at Step 2A, Prong Two, the additional elements individually or in combination do no integrate the judicial exception into a practical application.
Step 2B
In accordance with Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more that the judicial exception. As discussed above, the additional elements of:
sending, by each computing core in the plurality of computing cores, data to be reduced and a synchronization indicator to the plurality of first reduction engines in the plurality of dies, wherein the synchronization indicator follows the data to be reduced;
sending, by the first reduction engine in the current die, synchronization acknowledgments to the plurality of computing cores the current die;
are recited at a high level of generality and amounts to extra-solution activity of receiving data i.e. pre-solution activity of gathering data for use in the claimed process. The courts have found limitations directed to obtaining information electronically, recited at a high level of generality, to be well-understood, routine, and conventional (see MPEP 2106.05(d)(II), “receiving or transmitting data over a network”, "electronic record keeping," and "storing and retrieving information in memory").
In accordance with Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more that the judicial exception. The limitations:
in response to receiving the synchronization acknowledgment from the first reduction engine in the current die, and not receiving synchronization acknowledgements from other dies, reading, by each computing core of the plurality of computing cores in the current die, the reduction computing result from the first reduction engine in the current die.
are recited at a high-level of generality and amounts to no more than adding the words “apply it” to the judicial exception. These limitations also amount to extra solution activity because it is a mere nominal or tangential addition to the claim, amounting to mere data output (see MPEP 2106.05(g)). The courts have similarly found limitations directed to displaying a result, recited at a high level of generality, to be well-understood, routine, and conventional. See (MPEP 2106.05(d)(II), "presenting offers and gathering statistics.", “determining an estimated outcome and setting a price”).
The dies, reduction engines, die reduction engine, computing cores, and synchronization indicator amounts to no more than mere instructions to apply the exception using a generic computer component (See MPEP 2106.05(f)).
The recitation of synchronization indicator and reduction computing result amounts to generally linking the use of the judicial exception to a particular environment of field of use (See MPEP 2106.05(h)).
Accordingly, at Step 2B the additional elements individually or in combination do not amount to significantly more than the judicial exception.
As to claims 2 and 7, the limitations “wherein the plurality of dies are located in one or more computing devices” amounts to no more than mere instructions to apply the exception using a generic computer component (See MPEP 2106.05(f)).
As to claims 3 and 8, the limitations “wherein the plurality of pieces of data to be reduced are used for batch normalization of a neural network model” amounts to generally linking the use of the judicial exception to a particular environment of field of use (See MPEP 2106.05(h)).
As to claims 4 and 9, the limitations “for each die in the plurality of dies, performing following steps: performing, by each computing core of the plurality of computing cores in the current die, the batch normalization on the reduction computing result” are process steps that cover mental processes including an observation, evaluation, judgment or opinion that could be performed in the human mind or with the aid of pencil and paper. If a claim, under its broadest reasonable interpretation, covers a mental process but for the recitation of generic computer components, then it falls within the “Mental Process” grouping of abstract ideas.
As to claims 5 and 10, the limitations “wherein a number of the first reduction engine in the current die is one or more than one” are process steps that cover mental processes including an observation, evaluation, judgment or opinion that could be performed in the human mind or with the aid of pencil and paper. If a claim, under its broadest reasonable interpretation, covers a mental process but for the recitation of generic computer components, then it falls within the “Mental Process” grouping of abstract ideas.
Response to Arguments
Applicant's arguments filed 1/13/2026 have been fully considered but they are not persuasive.
Claim Rejections - 35 USC § 101
The 101 Rejection still has not been overcome. The claims are abstract and the steps in the claims can be completed with a mental process and/or generic computer components. Additionally, the steps in the claims do not describe an improvement of technology in any way.
The applicant argues:
The core technology of the claimed invention lies in solving the specific hardware architecture problem of "reducing reduction data processing delay across dies" (see paragraph [0008] of the published specification). The claimed invention does not describe abstract mathematical concepts, methods of organizing human activity or mental processes, but rather improvements to a specific hardware architecture in a computing system with multiple
dies.
The "synchronization indicator follows the data to be reduced" recited in the claimed invention is not simply a data arrangement, but a hardware timing control mechanism that ensures that the reduction operation is completed at the physical level before synchronization is complete, thereby eliminating the need for a global refreshing command (see paragraph [0048] of the published specification: "the synchronization indicator follows the corresponding data to be reduced, ensuring that by the time synchronization is completed, the reduction operation is completed earlier than the synchronization. Thus, data consistency is thus ensured without the need for a global refreshing command"). This is a microsecond-level hardware operation that is beyond the capabilities of the human mind.
The examiner disagrees. The arguments presented rely on limitations that are neither explicitly recited in the claims nor reasonably inferred from them. At no point in the pending claims does the applicant assert, describe, or even suggest the limitation of “microsecond-level hardware operation.” Rather, the applicant appears to have introduced this language as part of the argument, but such a limitation cannot be read into the claims when it is not supported by the actual claim language.
While the applicant argues that the claimed invention addressees a specific hardware problem, which is reducing data processing delay across multiple dies, the claims themselves do not recite a specific technological improvement to computer hardware. Instead, the claims broadly recite functional results like synchronization and data reduction timing without specifying how such results are achieved through the claimed limitations.
Additionally, the recited “synchronization indicator follows the data to be reduced” is claimed at a high level of abstraction and is not limited to a specific hardware implementation. As claimed, this limitation merely describes data association which simply amounts to data manipulation. The claims do not include meaningful limitations that tie the invention to a particular technological solution or any hardware that is more than generic computer components.
Moreover, while the claims may recite a specific way for distributed reduction across multiple dies, narrowing the recited abstract idea or limiting it to a particular field of use in this way does not change our overall understanding of the claims and, thus, does not render the claims non-abstract. See Rev. Guid., 84 Fed. Reg. at 55 n.32; see also e.g., Ultramercial, Inc. v. Hulu,
The applicant mentions Example 47 of the ‘USPTO July 2024 Subject Matter Eligibility’ examples but the Applicant does not explain how the cited example is relevant to the presently claimed invention. The example is not tied to the claimed features, nor is any comparison provided demonstrating how it supports patent eligibility. It is unclear why the Applicant relies on this example.
The applicant argues:
The step of "sending a synchronization indicator following the data to trigger reduction" in the claimed invention utilizes a specific signal triggering mechanism to resolve communication delays or connectivity issues. This is not something that can be performed by the human mind.
Therefore, the claimed invention describes a specific, computer-implemented method whose computational requirements, data scale, and processing speed exceed human capabilities, and thus should not be regarded as an abstract idea directed to a "mental process."
The examiner disagrees. Patent eligibility does not turn on whether a human can practically perform the steps. The claims merely recite sending and coordinating data and synchronization information at a high level of abstraction, without specifying a particular hardware mechanism or technological improvement. The claims remain directed to an abstract idea.
The applicant argues:
With respect to Step 2A, Prong Two, the technical problem that the present invention aims to solve lies in the fact that data refreshing synchronization, and reading across dies or across devices cause long latency, which significantly degrades overall performance. Conventional solutions typically require a global refreshing command, resulting in poor efficiency (see paragraphs [0006], [0023], [0048] in the published specification).
Accordingly, the claimed invention ensures data consistency through a specific data transmission and synchronization mechanism without requiring a global refreshing command. The claimed invention adopts a distributed reduction architecture in which each die includes multiple computing cores, each computing core has a corresponding reduction engine. One reduction engine is selected within each die to serve as its responsible unit. The computing cores execute a "send to all" but "read from local" strategy, using a local confirmation mechanism to bypass the latency associated with remote reads. Through the Local Acknowledgment mechanism, the claimed invention avoids the delay of remote reading and achieves a 3 to 4 times performance improvement. This is not merely data collection; rather, it constitutes a concrete improvement to the physical operational efficiency of the distributed computing system itself.
The claimed invention establishes configuration steps for a specific hardware topology. This defines which physical circuit in the system is responsible for reduction operations, and is a specific technical means of establishing distributed computing paths, thus changing the system's operating mode. The claimed invention also improves the specific protocol for computer operation.
The synchronization indicator and reduction engine in the claimed invention are not standard functions of general-purpose computers, but rather interaction mechanisms designed for a specific parallel processing architecture. This specific interaction method integrates abstract idea into a practical application.
The examiner disagrees. The arguments presented rely on limitations that are neither explicitly recited in the claims nor reasonably inferred from them. At no point in the pending claims does the applicant assert, describe, or even suggest the limitation of “achieves a 3 to 4 times performance improvement.” Rather, the applicant appears to have introduced this language as part of the argument, but such a limitation cannot be read into the claims when it is not supported by the actual claim language.
The claims do not recite a specific improvement to computer hardware or to the functioning of the computer itself, but instead describe the abstract idea of coordinating data transmission and synchronization across computing resources. The alleged performance benefits, such as avoiding global refresh commands or achieving a “3 to 4 times” performance improvement, are results-oriented without corresponding the claim limitations that specify how such improvements are technically achieved. Merely assigning roles to computing cores, selecting a reduction engine, or performing “send to all but read from local” operations are simply conventional data processing and communication techniques implemented using generic computing components.
Further, the claimed synchronization indicator and reduction engine are recited at a high level of abstraction and do not impose meaningful limits on the claim scope. These elements merely automate known functions using standard parallel processing architectures. Therefore, the claims do not integrate the abstract idea into a practical application, but instead amount to instructions to apply the abstract idea using convention computer technology.
The applicant mentions Example 21 of the ‘USPTO July 2024 Subject Matter Eligibility’ examples but the Applicant does not explain how the cited example is relevant to the presently claimed invention. The example is not tied to the claimed features, nor is any comparison provided demonstrating how it supports patent eligibility. It is unclear why the Applicant relies on this example.
The applicant mentions Example 40 of the ‘USPTO July 2024 Subject Matter Eligibility’ examples but the Applicant does not explain how the cited example is relevant to the presently claimed invention. The example is not tied to the claimed features, nor is any comparison provided demonstrating how it supports patent eligibility. It is unclear why the Applicant relies on this example.
The applicant argues:
In addition, referring to 2106.05(a) Improvements to the Functioning of a Computer or To Any Other Technology or Technical Field, "When performing this evaluation, examiner should be careful to avoid oversimplifying the claims," meaning to only discuss the general aspects and ignore the specific requirements of the claims.
The amended claim 1 introduce "only sending, by the first reduction engine in the current die, synchronization acknowledgments to the plurality of computing cores in the current die" and "not receiving synchronization acknowledgments from other dies, reading, ", , and the amended claim 1 introduce "only sends synchronization acknowledgments to the plurality of computing cores in the current die and "not receiving synchronization acknowledgments from other dies, reading, ", which clearly define the physical difference between the claimed invention and the general computer communication protocols (general protocols typically do not limit the return distance of ACKs). This demonstrates that the claimed invention is a specific improvement to the internal operation (latency and bandwidth) of a computer system. The claimed invention falls under the category of "specific hardware signal flow control".
In general computer networks, ACKs are typically sent back from the receiver to the sender, regardless of distance. However, the claimed invention mandates that the first reduction engine in the current die only sends ACK to the computing cores of the "local die (current die)," thus explicitly excluding ACK from being sent to other dies (remote dies). This special signal path design directly reduces bus throughput and latency, constituting a concrete improvement to computer functionality.
Furthermore, "synchronization indicator following the data to be reduced" and "local ACK" in the claimed invention are special communication protocols designed to "solve latency problems within computer systems." According to Enfish, LLC V. Microsoft Corp. and MPEP 2106.05(a), claims concerning improvements to computer functionality should not be considered abstract ideas. (Step 2B: Yes)
The examiner disagrees. The arguments presented rely on limitations that are neither explicitly recited in the claims nor reasonably inferred from them. At no point in the pending claims does the applicant assert, describe, or even suggest the limitation of “general protocols typically do not limit the return distance of ACKs and local ACKs” Rather, the applicant appears to have introduced this language as part of the argument, but such a limitation cannot be read into the claims when it is not supported by the actual claim language.
The claims still fail to integrate the recited abstract idea into a practical application. The limitations “only sending synchronization acknowledgments to the plurality of computing cores in the current die” and “not receiving synchronization acknowledgements from other dies” simply describes rules for information exchange and signal routing. Such limitations represent logical restriction on data communication rather than a technological improvement to underlying computer architecture or hardware. The claims do not recite any structural modifications nor do they define a new novel hardware configuration that alters how the computer operates.
Applicant’s reliance on reduced latency and bandwidth usage reflects an intended results of the claimed information flow rules, not a claimed technical limitation for achieving such results. Performance improvements alone, without specific claim limitations directed to a concrete technological solution, are insufficient to demonstrate integration into a practical application under MPEP § 2106.05(a).
Additionally, the recited “reduction engine” and “synchronization indicator” are claimed at a high level of generality and function as abstract elements implemented using generic computer components. These elements perform conventional functions of receiving, sending, and processing data, and do not impose meaningful limits on the claim scope.
It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception. See MPEP § 2106.04(d) (discussing Finjan, Inc. v. Blue Coat Sys., Inc., 879 F.3d 1299, 1303-04, 125 USPQ2d 1282, 1285-87 (Fed. Cir. 2018))
It is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology. For example, in Trading Technologies Int’l v. IBG, 921 F.3d 1084, 1093-94, 2019 USPQ2d 138290 (Fed. Cir. 2019), the court determined that the claimed user interface simply provided a trader with more information to facilitate market trades, which improved the business process of market trading but did not improve computers or technology (MPEP 2106.05(a)(II).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON S COLE whose telephone number is (571)270-5075. The examiner can normally be reached Mon - Fri 7:30pm - 5pm EST (Alternate Friday's Off).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Omar Fernandez can be reached at 571-272-2589. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRANDON S COLE/ Primary Examiner, Art Unit 2128