DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Referring to claim 13, “the error pin” lacks antecedent basis. Between that and a “subsequent” assertion, this appears to have been intended to depend from claim 12 instead of claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 9, 14, 17, 18, 20, 22, 23-25 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2024/0103961 Al to Wang.
Referring to claim 1, Wang discloses an apparatus comprising: a first processor comprising: first circuitry to track correctable errors detected by a first communication device of a second processor; second circuitry to communicate with the second processor to initiate, based on the tracked correctable errors, a link recovery procedure for the first communication device (Abstract, “A Peripheral Component Interconnect express (PCIe) fault auto-repair method is provided. According to the method, when a PCIe link in a system runs, an operation state of the system is monitored by acquiring a Correctable Error (CE) error count and an Uncorrectable Error (UCE) error count in the PCIe link; when the CE error count reaches a corresponding error threshold value, or the UCE error count reaches a corresponding error threshold value, an error device is removed from the system to avoid continuous adverse influence of the error device on operation of the system. Moreover, an SI parameter register of the error device is modified according to pre-stored optimization parameters of all PCIe devices in a server, the SI parameter of the error device is automatically optimized, and the error device is re-accessed to the system after the PCIe fault repair.” Paragraph 59-61, “The errors of the PCIe may be classified into Correctable Errors (CEs) and Uncorrectable Errors (UCEs). After the system is started, an automatic error report mechanism is set in the server system, when a PCIe error occurs in the system, the correctable error (CE) may be automatically identified by hardware and automatically corrected or repaired, but the system cannot automatically repair the UCE. A BIOS reports the PCIe error to a BMC after acquiring the PCIe error, and records a log, that is, the system records a CE error count and a UCE error count. In the present embodiment, the CE error count and the UCE error count, which are recorded in the system, are acquired and further determination is performed based on the acquired CE error count and UCE error count. If the system does not record or cannot read error information recorded in the system, a corresponding error detection mechanism may also be set, which is not limited in the present embodiment. In order to simplify the implementation process and improve the efficiency of acquiring the error count, the process of acquiring the CE error count and the UCE error count in the PCIe link may include: a CE register and a UCE register of each PCIe device are polled; and a receiver error count recorded in a CE register is used as the CE error count, and a receiver error count recorded in a UCE register is used as the UCE error count. According to the above implementation, an error register of the PCIe device and a Root port (e.g., a CPU PCIe port) end are monitored during the operation process of the server system, the operation state of the PCIe device is monitored in real time by polling the CE register and the UCE register of the PCIe device, so as to acquire the receiver error count of CE and the receiver error count of UCE, and determine whether a (CE or UCE) fault occurs in the PCIe device based on the acquired receiver error count of CE and receiver error count of UCE. The implementation is simplified by directly reading the register. Meanwhile, the numerical value recorded in the register is written after error is detected in the system, so that the data is accurate, and the accuracy of acquiring the data may be ensured. In the present embodiment, the above implementation for acquiring the error count is only taken as an example for introduction, and data acquisition modes of other approaches (for example, reading count values of Bad TLP count and Bad DLLP count registers) may all refer to the description in the present embodiment, and thus details are not described herein again.”).
Referring to claim 3, Wang discloses the second circuitry is to communicate with the second processor to initiate the link recovery procedure based on a number of tracked correctable errors (Abstract, “A Peripheral Component Interconnect express (PCIe) fault auto-repair method is provided. According to the method, when a PCIe link in a system runs, an operation state of the system is monitored by acquiring a Correctable Error (CE) error count and an Uncorrectable Error (UCE) error count in the PCIe link; when the CE error count reaches a corresponding error threshold value, or the UCE error count reaches a corresponding error threshold value, an error device is removed from the system to avoid continuous adverse influence of the error device on operation of the system. Moreover, an SI parameter register of the error device is modified according to pre-stored optimization parameters of all PCIe devices in a server, the SI parameter of the error device is automatically optimized, and the error device is re-accessed to the system after the PCIe fault repair.”).
Referring to claim 5, Wang discloses wherein the first communication device comprises a Peripheral Component Interconnect Express (PCIe) root port (Paragraph 61, “According to the above implementation, an error register of the PCIe device and a Root port (e.g., a CPU PCIe port) end are monitored during the operation process of the server system, the operation state of the PCIe device is monitored in real time by polling the CE register and the UCE register of the PCIe device, so as to acquire the receiver error count of CE and the receiver error count of UCE, and determine whether a (CE or UCE) fault occurs in the PCIe device based on the acquired receiver error count of CE and receiver error count of UCE. The implementation is simplified by directly reading the register. Meanwhile, the numerical value recorded in the register is written after error is detected in the system, so that the data is accurate, and the accuracy of acquiring the data may be ensured. In the present embodiment, the above implementation for acquiring the error count is only taken as an example for introduction, and data acquisition modes of other approaches (for example, reading count values of Bad TLP count and Bad DLLP count registers) may all refer to the description in the present embodiment, and thus details are not described herein again.”).
Referring to claim 9, Wang discloses the first processor is a baseboard management controller (BMC) (Paragraph 59, “The errors of the PCIe may be classified into Correctable Errors (CEs) and Uncorrectable Errors (UCEs). After the system is started, an automatic error report mechanism is set in the server system, when a PCIe error occurs in the system, the correctable error (CE) may be automatically identified by hardware and automatically corrected or repaired, but the system cannot automatically repair the UCE. A BIOS reports the PCIe error to a BMC after acquiring the PCIe error, and records a log, that is, the system records a CE error count and a UCE error count. In the present embodiment, the CE error count and the UCE error count, which are recorded in the system, are acquired and further determination is performed based on the acquired CE error count and UCE error count. If the system does not record or cannot read error information recorded in the system, a corresponding error detection mechanism may also be set, which is not limited in the present embodiment.”).
Referring to claims 14, 17, 18, 20, 22, 23 see rejection of claims 1, 5 above.
Referring to claim 24, Wang discloses wherein the processor comprises second circuitry to calculate the metric (Paragraph 60, “In order to simplify the implementation process and improve the efficiency of acquiring the error count, the process of acquiring the CE error count and the UCE error count in the PCIe link may include: a CE register and a UCE register of each PCIe device are polled; and a receiver error count recorded in a CE register is used as the CE error count, and a receiver error count recorded in a UCE register is used as the UCE error count.”).
Referring to claim 25, Wang discloses further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor (Paragraph 115, “The PCIe fault auto-repair device 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input/output interfaces 358, and/or, one or more operating systems 341.” Paragraph 3, “A PCIe (which is a high-speed serial computer expansion bus standard) device is an indispensable component in a server, and the performance, calculation, functions and the like of the server are all related to the PCIe device. The PCIe device further relates to the calculation (such as Graphics Processing Unit (GPU) and Field Programmable Gate Array (FPGA)), storage (such as Serial Attached SCSI (SAS) Host Bus Adapter (HBA), Nonvolatile Memory Express (NVME) Solid State Drive (SSD)), and network (Network Interface Card (NIC)) of the server, and plays an important role.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 4, 15, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1, 14, 18 above, and further in view of US 2004/0156446 to Santhoff et al.
Referring to claim 2, Wang discloses the second circuitry is to communicate with the second processor to initiate the link recovery procedure based on a number of tracked correctable errors (Abstract, “A Peripheral Component Interconnect express (PCIe) fault auto-repair method is provided. According to the method, when a PCIe link in a system runs, an operation state of the system is monitored by acquiring a Correctable Error (CE) error count and an Uncorrectable Error (UCE) error count in the PCIe link; when the CE error count reaches a corresponding error threshold value, or the UCE error count reaches a corresponding error threshold value, an error device is removed from the system to avoid continuous adverse influence of the error device on operation of the system. Moreover, an SI parameter register of the error device is modified according to pre-stored optimization parameters of all PCIe devices in a server, the SI parameter of the error device is automatically optimized, and the error device is re-accessed to the system after the PCIe fault repair.”).
Although Wang does not specifically disclose wherein the second circuitry is to communicate with the second processor to initiate the link recovery procedure based on a rate of tracked correctable errors, this is very well known in the art. In a related field of computing, an example of this is shown by Santhoff, from paragraph 105-107, “Referring to FIG. 11, in another embodiment of the present invention, a bit-error-rate (BER) is measured and the UWB pulse recurrence frequency (PRF), or pulse transmission rate is adjusted in response to the BER. In step 310, a first UWB device transmits a data set through a wire or cable medium. The data set may comprise any number of data bits. In step 320, a second UWB device receives the data set. The second device calculates the BER in step 330, by comparing the data bits that were received with the expected data bits. The calculated BER is compared to a threshold in step 340. If the BER exceeds the threshold, a threshold exceeded flag is set in step 350, and a threshold-exceeded message is sent in step 360. The first UWB device receives the threshold-exceeded message and reduces its PRF in step 370. If the BER threshold is not exceeded, the second device checks to see if the threshold-exceeded flag is set in step 380. If the threshold-exceeded flag is set, in step 390 the second device sends a stop message to the first device and the first device terminates the process in step 400. If the threshold-exceeded flag is not set, in step 410 the second device sends a continue message. The first device receives the continue message and increases its PRF in step 420.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to track using a rate because, as shown by Santhoff, it allows a count to be tracked as a ratio, which provides the denominator context, which may be used for comparison purposes, eg, thresholds.
Referring to claim 4, Wang discloses the second circuitry is to communicate with the second processor to initiate the link recovery procedure based on a number of tracked correctable errors (Abstract, “A Peripheral Component Interconnect express (PCIe) fault auto-repair method is provided. According to the method, when a PCIe link in a system runs, an operation state of the system is monitored by acquiring a Correctable Error (CE) error count and an Uncorrectable Error (UCE) error count in the PCIe link; when the CE error count reaches a corresponding error threshold value, or the UCE error count reaches a corresponding error threshold value, an error device is removed from the system to avoid continuous adverse influence of the error device on operation of the system. Moreover, an SI parameter register of the error device is modified according to pre-stored optimization parameters of all PCIe devices in a server, the SI parameter of the error device is automatically optimized, and the error device is re-accessed to the system after the PCIe fault repair.”).
Although Wang does not specifically disclose wherein the second circuitry is to initiate calculation of a rate of tracked correctable errors for the first communication device at a regular interval, this is known in the art. In a related field of computing, an example of this is shown by Santhoff, from paragraph 105-107, “Referring to FIG. 11, in another embodiment of the present invention, a bit-error-rate (BER) is measured and the UWB pulse recurrence frequency (PRF), or pulse transmission rate is adjusted in response to the BER. In step 310, a first UWB device transmits a data set through a wire or cable medium. The data set may comprise any number of data bits. In step 320, a second UWB device receives the data set. The second device calculates the BER in step 330, by comparing the data bits that were received with the expected data bits. The calculated BER is compared to a threshold in step 340. If the BER exceeds the threshold, a threshold exceeded flag is set in step 350, and a threshold-exceeded message is sent in step 360. The first UWB device receives the threshold-exceeded message and reduces its PRF in step 370. If the BER threshold is not exceeded, the second device checks to see if the threshold-exceeded flag is set in step 380. If the threshold-exceeded flag is set, in step 390 the second device sends a stop message to the first device and the first device terminates the process in step 400. If the threshold-exceeded flag is not set, in step 410 the second device sends a continue message. The first device receives the continue message and increases its PRF in step 420.” Further, paragraph 111, “Since the characteristics of wire or cable media may change with the environmental and load conditions of the media, it is anticipated that the optimization process may be periodically repeated during communication. The periodicity of the optimization process may be additionally dependent on the BER. In one embodiment, a BER calculation is done periodically and if the BER exceeds a pre-determined threshold, one or more of the above-described optimization methods may be employed.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to track using a rate, regularly calculated, because, as shown by Santhoff, it allows a count to be tracked as a ratio, which provides the denominator context, which may be used for comparison purposes, eg, thresholds.
Referring to claims 15, 19, see rejection of claim 2 above.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 above, and further in view of US 2021/0050941 to Das Sharma et al.
Referring to claim 6, Wang discloses wherein the first communication device comprises a Peripheral Component Interconnect Express (PCIe) root port (Paragraph 61, “According to the above implementation, an error register of the PCIe device and a Root port (e.g., a CPU PCIe port) end are monitored during the operation process of the server system, the operation state of the PCIe device is monitored in real time by polling the CE register and the UCE register of the PCIe device, so as to acquire the receiver error count of CE and the receiver error count of UCE, and determine whether a (CE or UCE) fault occurs in the PCIe device based on the acquired receiver error count of CE and receiver error count of UCE. The implementation is simplified by directly reading the register. Meanwhile, the numerical value recorded in the register is written after error is detected in the system, so that the data is accurate, and the accuracy of acquiring the data may be ensured. In the present embodiment, the above implementation for acquiring the error count is only taken as an example for introduction, and data acquisition modes of other approaches (for example, reading count values of Bad TLP count and Bad DLLP count registers) may all refer to the description in the present embodiment, and thus details are not described herein again.”).
Although Wang does not specifically disclose that such a root port could also be CXL, CXL is known in the art. In a related field of computing, an example of this is shown by Das Sharma, from paragraph 40, “As serial interconnects continue to increase (double) in data rates, such as can be seen for each PCIe generation, maintaining a bit error rate (BER) of 10.sup.−12 or better with the hundreds of lanes per system on chip (SoC) becomes difficult due to various elements contributing to cross-talk, inter-symbol interference (ISI), and channel loss arising from the socket, the vias, the board, the connector, and the add-in card (AIC). With the deployment of PAM-4 encoding for the next generation data rates (e.g., PCIe (Gen 6 at 64 GT/s along with the next generation of Compute Express Link (CXL) and Ultra Path Interconnect (UPI) data rates) the target BER is much higher at 10.sup.−6. The nature of errors expected at these higher data rates are expected to be correlated between consecutive bits on the same lane (burst errors) due to the decision feedback equalizer (DFE). The nature of these errors is also expected to have correlation between errors across lanes since the lanes share the same source of error such as power supply noise, clock jitter on the TX side, etc.” Further, paragraph 56-58, “ PCIe Gen 6 (PCI Express 6.sup.th Generation) at 64.0 GT/s, CXL 3.0 (Compute Express Link 3.sup.rd Generation) at 64.0 GT/s, and CPU-CPU symmetric coherency links such as UPI (Ultra Path Interconnect) at frequencies above 32.0 GT/s (e.g., 48.0 GT/s or 56.0 GT/s or 64.0 GT/s) are examples of interconnects that will need FEC to work in conjunction with CRC. In SoCs, it is highly desirable for the same PHY to be multi-protocol capable and used as PCIe/CXL/UPI depending on the device connected as the Link partner. In embodiments of this disclosure, multiple protocols (e.g., PCIe, CXL, UPI) may share a common PHY. Each protocol, however, may have different latency tolerance and bandwidth demands. For example, PCIe may be more tolerant to a latency increase than CXL. CPU-CPU symmetric cache coherent links such as UPI are most sensitive to latency increases. Links such as PCIe and CXL can be partitioned into smaller independent sub-links. For example, a x16 PCIe/CXL link may be partitioned to up to 8 independent links of x2 each. A symmetric cache coherent link may not support that level of partitioning. Due to the differences in latency characteristics, partitioning support, as well as due to fundamental protocol differences, these links may use different flow control unit (Flit) sizes and Flit arrangements, even though they may share the same physical layer.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a root port be CXL because, as shown by Das Sharma, these are recognized as substitutable standards.
Claim(s) 8, 11, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1, 18 above, and further in view of US 2021/0349777 to Liu et al.
Referring to claim 8, Wang discloses devices may be I/O devices (Paragraph 3, “A PCIe (which is a high-speed serial computer expansion bus standard) device is an indispensable component in a server, and the performance, calculation, functions and the like of the server are all related to the PCIe device. The PCIe device further relates to the calculation (such as Graphics Processing Unit (GPU) and Field Programmable Gate Array (FPGA)), storage (such as Serial Attached SCSI (SAS) Host Bus Adapter (HBA), Nonvolatile Memory Express (NVME) Solid State Drive (SSD)), and network (Network Interface Card (NIC)) of the server, and plays an important role.”).
Although Wang does not explicitly disclose wherein the first communication device comprises an input/output device coupled downstream of a root port, this is known in the art. In a related field of computing, an example of this is shown by Liu, from the abstract, “A fault processing method includes: a fault processing apparatus receives first hardware fault information generated by a first PCIe device on a first PCIe link. The first hardware fault information includes a device identifier of the first PCIe device and is used to indicate that a hardware fault occurs on the first PCIe device. Further, the fault processing apparatus performs, based on the first hardware fault information, fault recovery on the first PCIe link on which the first PCIe device is located, and interrupts a software service related to the first PCIe device.” Further, see figures 2 and 3, where such devices are connected downstream of a root port. Further, paragraph 65-66, “According to the foregoing embodiments, the following describes a fault processing method in the present invention. FIG. 4 is a schematic flowchart of a fault processing method according to an embodiment of the present invention. The fault processing method shown in FIG. 4 is applied to the computing device shown in FIG. 2 or FIG. 3, and the method includes the following implementation steps. Step S402: A fault processing apparatus receives first hardware fault information generated by a first PCIe device on a first PCIe link, where the first hardware fault information is used to indicate that a hardware fault occurs on the first PCIe device, and the first hardware fault information includes a device identifier of the first PCIe device.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an I/O device connected downstream of a root port because, as shown by Liu, this enables PCIe communication, from paragraph 60-62, “The devices at the hardware layer 20 may be connected through a PCIe bus to constitute the PCIe bus system. For example, in the figure, the CPU 201, the memory 202, the root complex 203, the PCIe switch 204, the GPU 2051, and the GPU 2052 are connected through the PCIe bus to constitute the PCIe bus system. A communication link between any two devices at the hardware layer 20 is also referred to as a PCIe link. The PCIe device group 205 includes at least one PCIe device. The PCIe device is used as a PCIe endpoint (EP) defined in a PCIe protocol, and may include but is not limited to devices such as a field programmable gate array (FPGA), a graphics processing unit (GPU), and a chip (for example, an 1822 chip). The figure shows the GPU 2051 and the GPU 2052 as an example. Any PCIe device in the PCIe device group may communicate with the root complex 203 through the PCIe switch 204. For example, the GPU 2051 may communicate with the root complex 203 through the PCIe switch 204 in the figure. Optionally, the PCIe device in the PCIe device group may further directly communicate with the root complex 203. For example, the GPU 2052 may directly communicate with the root complex 203 in the figure. Optionally, when there are a plurality of PCIe devices communicating with the PCIe switch, any two PCIe devices in the plurality of PCIe devices may communicate with each other through the PCIe switch 204, which is not shown in the figure.”
Referring to claim 11, although Wang does not specifically disclose wherein the link recovery procedure comprises a PCIe Downstream Port Containment (DPC) process, this is known in the art. In a related field of computing, an example of this is shown by Liu, from paragraph 71, “For example, referring to the schematic structural diagram of the computing device shown in FIG. 2, the hardware fault interrupt signal is a DPC interrupt signal, the first PCIe device is the GPU 2051, and the first PCIe link is a communication link between the PCIe switch 204 and the GPU 2051. When the computing device supports a DPC function, and when the fault processing apparatus detects, through the downstream port 2042 of the PCIe switch 204, that the first PCIe link is faulty, when the downstream port 2042 receives a fault packet sent by the GPU 2051 or does not receive, within a preset period, a heartbeat packet sent by the GPU 2051, the fault processing apparatus may generate a DPC hardware fault interrupt signal. The DPC interrupt signal carries the first hardware fault information, and the first hardware fault information is used to indicate the device identifier of the first PCIe device on which the hardware fault occurs, that is, the GPU 2051. Further, the fault processing apparatus may send the DPC interrupt signal to a fault recovery module (which may be the foregoing DPC module) of the fault processing apparatus, so that the DPC module performs fault recovery on the first PCIe link based on the first hardware fault information.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use DPC because, as shown by Liu, this enables a fault to be signaled so that fault information can be relayed to be handled.
Referring to claim 21, see rejection of claim 8 above.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 above, and further in view of US 2014/0189427 to Jayaprakash Bharadwaj et al.
Referring to claim 10, although Wang does not specifically disclose wherein the link recovery procedure includes stopping traffic downstream of the first communication device and retraining a link of the first communication device, this is known in the art. In a related field of computing, an example of this is shown by Jayaprakash Bharadwaj, from paragraph 77, “In LER mode, outstanding transactions and inbound and outbound packets are dropped and drained from the link. When hardware (or software) logic drops the pending transactions, a port quiesced bit 855 can be set. Another controller, such as an at least partially software-based error handler, can attempt to resolve and analyze the error condition. The error handler (or other tool) can further clear error registers (e.g., upon resolution of the error condition). Additionally, upon clearing the error registers, the error handler can identify that no transactions are pending on the link (or port) by virtue of the value of the port quiesced bit 855, and clear the LER status bit to cause the link to exit LER mode. In one example, an exit from LER includes retraining of the link and bringing back up to an active transmitting state.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to stop downstream traffic and retrain a link because, as shown by Jayaprakash Bharadwaj, from paragraph 68, “In some implementations, a live error recovery (LER) feature can be supported on ports in an interconnect architecture, such as PCIe-compliant ports. LER can be utilized to trap errors at a root port where the error is detected and prevent propagation of the error beyond the port. Detection of an error can trigger live error recovery by causing a link to be forced into a link down state causing all outbound requests to be aborted and all inbound packets following the packet that triggered the LER condition to also be dropped. This can cause the error to be contained at a particular port where the error was detected. The error can be reported to global error detection and handling modules, including identification of the port and link where the error was detected. Software-based error assessment tools, such as error handlers, can then process and clear the reported error, in some cases, without a system-wide reset. Upon confirming that the inbound and outbound queues of the port of the downed link have been drained, recovery of the link can be initiated so as to bring the link back up to a transmitting state (e.g., following containment and clearing of the error), again, without a system-wide reset.”
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang as applied to claim 1 above, and further in view of US 10599504 to BeSerra et al.
Referring to claim 12, Wang discloses wherein the first processor is to read information identifying the first communication device responsive to polling by the second processor (Paragraph 60, “In order to simplify the implementation process and improve the efficiency of acquiring the error count, the process of acquiring the CE error count and the UCE error count in the PCIe link may include: a CE register and a UCE register of each PCIe device are polled; and a receiver error count recorded in a CE register is used as the CE error count, and a receiver error count recorded in a UCE register is used as the UCE error count.”).
Although Wang does not specifically disclose this is responsive to asserting an error pin, this is known in the art. In a related field of computing, an example of this is shown by BeSerra, from line 12 of column 9, “The BIOS 404 can include various services that can be called using hardware and software interrupts that reference the interrupt table. For example, the SMI handler 406 can be called by asserting an SMI pin of the processor 440, such as by the error detection logic 444 when an error is detected. The SMI handler code can be used to perform methods (such as methods 200 and/or 300) to dynamically adjust the refresh rate based on the memory error rate. In particular, a memory error can be detected by the error detection logic 444 which can assert the SMI pin, causing the SMI handler 406 to be invoked. The SMI handler can determine that the error detection logic 444 asserted the interrupt and execute a refresh control routine. The refresh control routine can calculate an error rate, determine if the calculated error rate exceeds a threshold rate, and dynamically adjust the refresh rate and/or patrol scrub rate accordingly. Specifically, the refresh rate and/or patrol scrub rate can be adjusted by writing the control registers of the memory controller 442. These registers can be written while the processor 440 is operating without performing a reboot of the processor 440.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use such a pin because, as shown by BeSerra, it allows an service to be called via an interrupt.
Allowable Subject Matter
Claims 7, 13, 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Referring to claim 7, the prior art does not teach or fairly suggest wherein the correctable errors detected by the first communication device comprise correctable errors occurring at the first communication device and correctable errors occurring at one or more communication devices downstream of the first communication device, in the scope and context of claim 1.
Referring to claim 13, the prior art does not teach or fairly suggest wherein the first processor is to read information identifying a second communication device responsive to a subsequent assertion of the error pin by the second processor, in the scope and context of claims 1 and 12, in accord with resolution of the 112 rejection above.
Referring to claim 16, see claim 7 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN 106201753 A, see abstract.
US 20080256400 A1, see abstract.
CN 111414268 A, see abstract.
CN 112256539 A, see abstract.
GB 2456618 A, see abstract.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL L CHU whose telephone number is (571)272-3656. The examiner can normally be reached weekdays 8 am to 5 pm.
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/GABRIEL CHU/ Primary Examiner, Art Unit 2114