DETAILED ACTION
Request for Continued Examination
The request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 1/30/26 is accepted.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (US 2019/0363048).
As to claim 1, Zhao teaches a semiconductor device (see annotated fig. 5 below), comprising:
a dielectric layer (503);
a plurality of vias (509) formed in the dielectric layer (503), the plurality of vias comprising a first via (see fig. below);
an adhesion layer (511 and/or 515); and
a plurality of metal lines (521, although only one is shown, it is obvious that there would be multiple lines 521 and vias 509 so as to make external connections to other devices or diffusion regions on the package/substrate, since it has been held that “mere duplication of parts has no patentable significance unless a new and unexpected result is produced” (See MPEP 2144.04(VI)(B)),
wherein a first metal line of the plurality of metal lines comprises a first recess formed at a bottom surface of the first metal line such that a first section of the first metal line directly contacts the first via and a second section of the first metal line defined by the first recess does not directly contact the first via or the dielectric layer in which the first via is formed, and
wherein a second metal line of the plurality of metal lines comprises at least one second recess positioned between a bottom surface of the second metal line and the dielectric layer, wherein the at least one second recess is defined by the bottom surface of the second metal line, a bottom surface of the adhesion layer, and a top surface of the dielectric layer.
See annotated drawing below. Figure 5 is annotated twice to show how the via-and-line configuration meets the limitations of both the first and second metal lines.
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As to claim 3, Zhao further teaches a first portion of the adhesion layer (shaded portion/second recess) is positioned between the dielectric layer (503) and the bottom surface of the second metal line such that the second metal line does not directly contact the dielectric layer (see annotated figure above).
As to claim 5, Zhao further teaches an oxide pattern positioned between the first portion of the adhesion layer and the dielectric layer (see figure below).
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As to claim 6, Zhao further teaches the at least one second recess is defined by a side surface of the oxide pattern (see figure above).
As to claim 7, Zhao teaches a semiconductor device (see annotated fig. 5 below), comprising: a dielectric layer (503);
a plurality of vias (509) formed in the dielectric layer (503), the plurality of vias comprising a first via (see fig. below);
a plurality of metal lines (521, although only one is shown, it is obvious that there would be multiple lines 521 and vias 509 so as to make external connections to other devices or diffusion regions on the package/substrate, since it has been held that “mere duplication of parts has no patentable significance unless a new and unexpected result is produced” (See MPEP 2144.04(VI)(B)); and
at least one oxide pattern (see annotated figure below) positioned between a bottom surface of a first metal line of the plurality of metal lines and a top surface of the dielectric layer (see below); and
wherein the first metal line comprises at least one first recess positioned between the bottom surface of the first metal line and the dielectric layer;
wherein a second metal line of the plurality of metal lines comprises a second recess formed at the a bottom surface of the second metal line such that a first section of the second metal line directly contacts the first via and a second section of the second metal line defined by the second recess does not directly contact the first via or the dielectric layer in which the first via is formed (see figure below) and
wherein the at least one first recess is defined by the bottom surface of the first metal line, a side surface of the at least one oxide pattern, and the top surface of the dielectric layer (see figure below).
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As to claim 9, Zhao further teaches the plurality of metal lines comprise a ruthenium-based material ([0039]).
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
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Hand-Delivered responses should be brought to:
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
3/6/26