DETAILED ACTION
This action is in response to the submission filed on 3/10/2026. Claims 1-2 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments-Drawings/35 USC § 112
Applicant’s arguments with respect to the amendments have been fully considered and are persuasive. The objections/rejections have been withdrawn.
Response to Arguments-35 USC § 101
Applicant's arguments filed 3/10/2026 have been fully considered but they are not persuasive.
Applicant argues on pages 10-12 that the claims are not directed towards mathematical concepts in the abstract but how the hardware components process signals and that a technical improvement is realized by performing the method.
The claims recite generic circuitry for performing mathematical concepts. While the claim recites various circuits, they do not appear to be specialized or specific computing components. The disclosure also does not appear to describe any non-generic circuitry. It is unclear how performing a simulation on generic circuitry provides a technical improvement. Claim 2 in particular is purely directed towards mathematical operations using merely generic implementation on an FPGA. The disclosure confirms this in paragraph [0073] of the printed publication which states “the continuous model can be processed in general-purpose digital processing circuit”. The rejection has been updated to reflect the amended claim language.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. To determine if a claim is directed to patent ineligible subject matter, the Court has guided the Office to apply the Alice/Mayo test, which requires:
1. Determining if the claim falls within a statutory category;
2A. Determining if the claim is directed to a patent ineligible judicial exception consisting of a law of
nature, a natural phenomenon, or abstract idea; and
2B. If the claim is directed to a judicial exception, determining if the claim recites limitations or elements
that amount to significantly more than the judicial exception.(See MPEP 2106).
Step 1: With respect to claims 1-2, applying step 1, the preamble of independent claims 1 and 2 claim a circuit and a method. As such these claims fall within the statutory categories of machine and process.
Step 2A, prong one: In order to apply step 2A, a recitation of claim 1 is copied below. The limitations of the claim that describe an abstract idea are bolded.
A circuit for simulating real-time reconfigurable general-purpose memristor, which is built based on an FPGA, comprising:
system state variable generation circuitry, which comprises a multiplier, an accumulator and an adder, wherein the multiplier is used to multiply an input signal x[n] and an FPGA system clock cycle Ts together to obtain a result Ts-x[n], and result Ts-x[n] is outputted to the accumulator for accumulation to obtain an accumulated value (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi)), which is denoted by:
PNG
media_image1.png
42
74
media_image1.png
Greyscale
the accumulated value is outputted to the adder to add a system state variable's initial value h[0] (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi)),
then a system state variable h[n] is obtained:
PNG
media_image2.png
42
156
media_image2.png
Greyscale
where the input signal x[n] is a voltage signal or current signal, the system state variable h[n] is a charge or magnetic flux variable (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi));
calculation circuitry, which comprises m reconfigurable calculating units operating in m grades cascaded pipeline mode, and is used to implement m polynomial multiply-accumulate operations, wherein each reconfigurable calculating unit comprises two multipliers, one adder and one D flip-flop (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi));
to i+1 reconfigurable calculating unit, i=0,1,2,...,m-1, its inputs are polynomial coefficient k[i+1], the adder's input s[i] and the first multiplier's inputs H[i] and d[i], its outputs are the adder's output s[i+1], the second multiplier's output H[i+1] and the delayed signal d[i+1] (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi)), the mathematical relation of the inputs and the outputs is:
PNG
media_image3.png
78
227
media_image3.png
Greyscale
where the first multiplier is used to multiply inputs H[i] and d[i] together to obtain the output H[i+1], the second multiplier is used to multiply the first multiplier's output H[i+1] and polynomial coefficient k[i+1] together to obtain an output k[i+1]-H[i+1], the adder is used to add the input s[i] and the output k[i+1]-H[i+1] together to obtain the output s[i+1], the D flip-flop is used to delay the input d[i] to obtain the delay signal d[i+1] (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi));
to the 1st reconfigurable calculating unit, its input d[0] is the system state variable h[n] outputted by the system state variable generation circuitry, its input H[0] is 1, its input s[0] is the polynomial coefficient k(0); wherein the number m of the polynomials is determined as follows (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi)):
determining the maximum amplitude amax and the minimum frequency comm respectively according to the amplitude and the frequency of the zero-DC component AC signal in the input signal x[n], then determining the range of the system state variable h[n] as follows:
PNG
media_image4.png
43
87
media_image4.png
Greyscale
in the range of the system state variable h[n], using McLaughlin formula to perform a m-order polynomial fitting of memristance or memductance f(h[n]) about the system state variable h[n] to obtain a fitting function g(h[n]), where the maximum fitting error εM is:
PNG
media_image5.png
91
167
media_image5.png
Greyscale
the value of the polynomial order m should satisfy εM ≤ε0, where ε0 is the acceptable maximum fitting error;
wherein the polynomial coefficient k[i] of the ith order, i=0,1,2,...,m is obtained by expanding the memristance or memductance f(h[n]) at time n into a polynomial according to McLaughlin formula (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi)):
PNG
media_image6.png
40
178
media_image6.png
Greyscale
the output s[m] of the mth reconfigurable calculating unit is taken as the memristance or memductance f(h[n]) (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi));
a FIFO, which is used to delay the input signal x[n] m+39 clock periods to obtain a delayed input signal (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi));
output circuitry, which comprises a multiplier, where the multiplier is used to multiply the delayed input signal and the memristance or memductance f(h[n]) outputted by the mth reconfigurable calculating unit to obtain an output signal y[n], the output signal y[n] is a current signal or a voltage signal (Mathematical concepts - Mathematical Calculation – MPEP 2106.04{a}{2}{1}{C} (i-vi)).
The limitations as analyzed include concepts directed to the "Mathematical Concepts"
grouping of abstract ideas (including mathematical relationships, mathematical formulas or
equations, mathematical calculations) (see MPEP § 2106.04(a)(2), subsection I). A claim that
recites a mathematical calculation, when the claim is given its broadest reasonable
interpretation in light of the specification, will be considered as falling within the "mathematical
concepts" grouping. A mathematical calculation is a mathematical operation (such as
multiplication) or an act of calculating using mathematical methods to determine a variable or
number, e.g., performing an arithmetic operation such as exponentiation (see MPEP
2106.04(a)(2)(1)(C). Thus, limitations noted above also fall into the "Mathematical Concepts"
groupings of abstract ideas.
Step 2A, prong two: Under step 2A prong two, this judicial exception is not integrated
into a practical application because the additional claim limitations outside the abstract idea
only present generic computing components. In particular, the claim recites the additional limitations: “A circuit for simulating real-time reconfigurable general-purpose memristor, which is built based on an FPGA” (generic computing components merely carrying out the abstract idea - see MPEP § 2106.0S(f) and (b)), “system state variable generation circuitry, which comprises a multiplier, an accumulator and an adder, wherein the multiplier is used to multiply” (generic computing components merely carrying out the abstract idea - see MPEP § 2106.0S(f) and (b)), “a calculation module, which comprises m reconfigurable calculating units” (generic computing components merely carrying out the abstract idea - see MPEP § 2106.0S(f) and (b)), “a FIFO, which is used to delay” (generic computing components merely carrying out the abstract idea - see MPEP § 2106.0S(f) and (b)), “output circuitry, which comprises a multiplier, where the multiplier is used to multiply” (generic computing components merely carrying out the abstract idea - see MPEP § 2106.0S(f) and (b)).
Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
Step 2B: Moving on to step 2B of the analysis, the Examiner must consider whether each claim limitation individually or as an ordered combination amounts to significantly more
than the abstract idea. This analysis includes determining whether an inventive concept
is furnished by an element or a combination of elements that are beyond the judicial
exception. For limitations that were categorized as "apply it" or generally linking the use
of the abstract idea to a particular technological environment or field of use, the analysis
is the same. The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional limitations is considered directed towards generic computer components carrying out the abstract idea. See MPEP 2106.04(d) referencing MPEP 2106.05(h).
For the foregoing reasons, claim 1 is directed to an abstract idea without significantly more, and is rejected as not patent eligible under 35 U.S.C. 101.
Independent claim 2 is directed to substantially the same subject matter as independent claim 1 and is rejected under similar rationale and further failure to add significantly more.
Allowable Subject Matter
Claims 1-2 contain allowable subject matter.
The claims will be allowed if the rejections under 35 USC 101 are overcome.
The closest prior art of record, US 9019030 B1 (“Abuelma'atti”) teaches a method for a memristor model of embodiments of a memristor circuit of a memristor-based emulator for use in digital modulation. However, this reference and the remaining prior art of record, alone or in combination, fails to disclose or suggest
(claim 1)
“obtain a fitting function g(h[n]), where the maximum fitting error εM is:
PNG
media_image5.png
91
167
media_image5.png
Greyscale
the value of the polynomial order m should satisfy εM ≤ε0, where ε0 is the acceptable maximum fitting error;
wherein the polynomial coefficient k[i] of the ith order, i=0,1,2,...,m is obtained by expanding the memristance or memductance f(h[n]) at time n into a polynomial according to McLaughlin formula:
PNG
media_image6.png
40
178
media_image6.png
Greyscale
the output s[m] of the mth reconfigurable calculating unit is taken as the memristance or memductance f(h[n]);
a FIFO, which is used to delay the input signal x[n] m+39 clock periods to obtain a delayed input signal;
output circuitry, which comprises a multiplier, where the multiplier is used to multiply the delayed input signal and the memristance or memductance f(h[n]) outputted by the mth reconfigurable calculating unit to obtain an output signal y[n], the output signal y[n] is a current signal or a voltage signal”,
and
(claim 2)
“5.3) meanwhile, sending the single precision floating-point dataf x[n] to a first FIFO for delay to obtain a delayed dataf dly x[n], which makes the delayed data f dlyx[n] at the read port of the first FIFO aligned with the memristance or memductance f(h[n]) along the time, then calculating the output signal y[n]:
PNG
media_image7.png
21
199
media_image7.png
Greyscale
where the input signal x[n] is a voltage signal or current signal, the output signal y[n] is a current signal or voltage signal;
(6). storing the delayed dataf dly x[n] and the output signal y[n] into a second FIFO, when the second FIFO is written full, reading out the delayed data f dlyx[n] and the output signal y[n] from the second FIFO and send them to a computer;
(7). in the computer, multiplying the vertical sensitivity of input signal displaying and the half of the number of the vertical divisions in waveform display area to obtain a display range R1, multiplying the vertical sensitivity of memristor output displaying and the half of the number of the vertical divisions in waveform display area to obtain a display range R2;
then processing the delayed dataf dly x[n] as follows:
PNG
media_image8.png
77
209
media_image8.png
Greyscale
where max(ldx(n)) represents choosing the data which absolute value is maximum from the sequence of data dx(n), data dxHL(n)E[-1,1];
processing the output data y[n] as follows:
PNG
media_image9.png
102
197
media_image9.png
Greyscale
where max (Idy(n)j) represents choosing the data which absolute value is maximum from the sequence of data dy(n), data dyHL(n)E[-1,1];
(8). taking the center of the waveform display area of the X-Y view of a digital oscilloscope as a coordinate origin (0, 0), respectively taking the data dxHL(n) as a x-coordinate and the data dyHL(n) asa y-coordinate, then sending the pixel (dxHL(n), dyHL(n)) as the pixel to be highlighted into the digital oscilloscope's LCD to perform a display of Lissajous figure showing a pinched hysteresis loop;
meanwhile, sending the data dx(n) and the data dy(n) into the digital oscilloscope for caching and then performing a waveform display of time-domain;
(9). resetting the second FIFO, then judging according to the following rules: if both of the polynomial coefficient k(i) and the range of the system state variable h[n] have not been changed, then going to step (6), if the polynomial coefficient k(i) has been changed and the range of the system state variable h[n] has not been changed, then going to step (5), otherwise, going to step (1)”,
in combination with the remaining elements and features of the claimed invention. It is for these reasons that the applicant’s invention defines over the prior art of record.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NITHYA J. MOLL whose telephone number is (571)270-1003. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen can be reached at 571-272-3676. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NITHYA J. MOLL/Primary Examiner, Art Unit 2189