DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/19/2022 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 11-13 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang [US 2020/0083623].
Regarding claim 1, Huang discloses a memory module comprising: a printed circuit board (PCB) (fig. 1; 12) having a first face (fig. 2; 13), a second face (fig. 2; 15), and a first edge (fig. 2; 23) to be received by a connector (fig. 4; 30); a plurality of memory chips (fig. 2; 14) on at least one of the first and second faces (13, 15) of the PCB (12); and two rows of conductive contacts (fig. 1; 16, 18) on each of the first and second faces (13, 15) of the PCB (12), the two rows (16, 18) including a first row of conductive contacts (16) proximate to the first edge (23) of the PCB to be received by the connector (30), and a second row of conductive contacts (18) between the first row (16) and a second edge (fig. 2; top edge of 12) of the PCB opposite to the first edge (23).
Regarding claim 2, Huang discloses wherein: the second row of conductive contacts (18) is between the first row (16) and the plurality of memory chips (14).
Regarding claim 3, Huang discloses wherein: the first row of conductive contacts (16) is to couple with a plurality of inner pins (fig. 4; 34) of the connector (30); and the second row of conductive contacts (18) is to couple with a plurality of outer pins (fig. 4; 36) of the connector (30).
Regarding claim 11, Huang discloses a dual-inline memory module (DIMM) comprising: a printed circuit board (PCB) (12) having a first face (13), a second face (15), and an edge (23) to be received by a DIMM connector (30); a plurality of DRAM chips (14) on each of the first and second faces (13, 15) of the PCB; a bottom row of conductive contacts (16) on each of the first and second faces (13, 15) of the PCB (12) at the edge (23) of the PCB to be received by the DIMM connector (30); and a top row of conductive contacts (18) on each of the first and second faces (13, 15) of the PCB, wherein the top row (18) is aligned over and parallel to the bottom row of conductive contacts (13).
Regarding claim 12, Huang discloses wherein: the top row of conductive contacts (18) is between the bottom row (16) and the plurality of DRAM chips (14).
Regarding claim 13, Huang discloses wherein: the bottom row of conductive contacts (16) is to couple with a plurality of inner pins (34) of the DIMM connector (30); and the top row of conductive contacts (18) is to couple with a plurality of outer pins (36) of the DIMM connector (30).
Regarding claim 16, Huang discloses a system comprising: a processor (fig. 32; 980a), and a memory module coupled (fig. 32; 910) with the processor (980a), the memory module (910) including (910 and 930 may be formed in accordance with other embodiments i.e. figs. 1 and 2; see Par [0070] Ln 12-14): a printed circuit board (PCB) (12) having a first face (13), a second face (15), and a first edge (23) to be received by a connector (30); a plurality of memory chips (14) on at least one of the first and second faces (13, 15) of the PCB; and two rows of conductive contacts (16, 18) on each of the first and second faces (13, 15) of the PCB, the two rows (16, 18) including a first row of conductive contacts (16) proximate to the first edge (23) of the PCB to be received by the connector (30), and a second row of conductive contacts (18) between the first row (16) and a second edge (top edge of 12) of the PCB opposite to the first edge (23).
Regarding claim 17, Huang discloses wherein: the second row of conductive contacts (18) is between the first row (16) and the plurality of memory chips (14).
Regarding claim 18, Huang discloses wherein: the first row of conductive contacts (16) is to couple with a plurality of inner pins (34) of the connector (30); and the second row of conductive contacts (18) is to couple with a plurality of outer pins (36) of the connector (30).
Regarding claim 19, Huang discloses a motherboard (fig. 32; 950) including the connector (fig. 32; 930).
Regarding claim 20, Huang discloses one or more of: a display (fig. 32; 984), a battery, and a power supply.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4, 5, 7, 8, 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Huang [US 2020/0083623] in view of Amidi et al. [US 2008/0123305].
Regarding claims 4, 5, 7, 8, 14 and 15, Huang discloses all of the claim limitations except wherein: the two rows of conductive contacts on each of the first and second faces of the PCB are to couple with two memory channels [claim 4]; wherein: the first and second rows of conductive contacts on the first face of the PCB are to couple with a first memory channel; and the first and second rows of conductive contacts on the second face of the PCB are to couple with a second memory channel [claim 5]; a first registering clock driver (RCD) on the PCB to receive command and address signals for a first of the two memory channels; and a second RCD on the PCB to receive command and address signals for a second of the two memory channels [claim 7]; the first RCD is on a first face of the PCB; and the second RCD is on a second face of the PCB [claim 8]; wherein: the bottom rows and the top rows of conductive contacts on each of the first and second faces of the PCB are to couple with two memory channels [claim 14]; wherein: the bottom rows and the top rows of conductive contacts on the first face of the PCB are to couple with a first memory channel; and the bottom rows and the top rows of conductive contacts on the second face of the PCB are to couple with a second memory channel [claim 15].
Regarding claims 4, 5, 7, 8, 14 and 15, Amidi teaches the row of conductive contacts (figs. 9a-b; 194) on each of the first and second faces (figs. 9a-b; 155a, 155b) of the PCB (191) are to couple with two memory channels (figs. 9a-b; 190a-b); wherein: half of the row of conductive contacts (194) on the first and second faces (155a-b) of the PCB (191) are to couple with a first memory channel (190a); and half of the row of conductive contacts (194) on the first and second faces (155a-b) of the PCB (191) are to couple with a second memory channel (190b); a first registering clock driver (RCD) (figs. 9a-b; 152a) on the PCB to receive command and address signals for a first (190a) of the two memory channels (190a-b); and a second RCD (152b) on the PCB to receive command and address signals for a second (190b) of the two memory channels (190a-b); the first RCD (152a) is on a first face (155a) of the PCB (191); and the second RCD (152b) is on a second face (155b) of the PCB (191).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate the bottom and top/two rows of conductive contacts on each of the first and second faces of the PCB being coupled with two memory channels, the first/bottom and second/top rows of conductive contacts on the first face of the PCB are to couple with a first memory channel; and the first/bottom and second/top rows of conductive contacts on the second face of the PCB are to couple with a second memory channel, a first registering clock driver (RCD) on the PCB to receive command and address signals for a first of the two memory channels; and a second RCD on the PCB to receive command and address signals for a second of the two memory channels and the first RCD being on a first face of the PCB; and the second RCD being on a second face of the PCB as suggested by Amidi for the benefit of providing improved information flow between a processor and the memory module to achieve increased overall system performance.
Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Huang [US 2020/0083623] and Amidi et al. [US 2008/0123305] as applied to claim 4 above, and further in view of Lee et al. [US 2019/0237152].
Huang and Amidi disclose all of the limitations except a single registering clock driver (RCD) on the PCB, the single RCD to receive command and address signals for both of the two memory channels.
However, Lee teaches a single registering clock driver (RCD) (fig. 5; 530) on the PCB (fig. 5; 502), the single RCD (530) to receive command and address signals for both of the two memory channels (fig. 5; CHA, CHB).
Therefore, it would have been further obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate a single registering clock driver (RCD) on the PCB, the single RCD to receive command and address signals for both of the two memory channels as suggested by Lee for the benefit of improving the digital logic of a memory module processor for a simpler design with optimized functionality.
Claim(s) 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Huang [US 2020/0083623].
Regarding claims 9 and 10, Huang (figs. 1-2 embodiment) discloses all of the claim limitations except a third row of conductive contacts between the first row and the second row of conductive contacts [claim 9]; the first row of conductive contacts is to couple with a plurality of inner pins of the connector; the second row of conductive contacts is to couple with a plurality of outer pins of the connector; and the third row of conductive contacts is to couple with a plurality of pins between the plurality of inner pins and the plurality of outer pins [claim 10].
Regarding claims 9 and 10, figs. 23-26 embodiments teach a third row of conductive contacts (figs. 23, 25; 517 or 617) between the first row (516/616) and the second row of conductive contacts (518/618); the first row (516/616) of conductive contacts is to couple with a plurality of inner pins (figs. 24, 26; 534/634) of the connector (figs. 24, 26; 530/630); the second row of conductive contacts (518/618) is to couple with a plurality of outer pins (536/636) of the connector (530-630); and the third row of conductive contacts (517/617) is to couple with a plurality of pins (535/635) between the plurality of inner pins (534/634) and the plurality of outer pins (536/636).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to incorporate a third row of conductive contacts between the first row and the second row of conductive contacts and the first row of conductive contacts to couple with a plurality of inner pins of the connector; the second row of conductive contacts to couple with a plurality of outer pins of the connector; and the third row of conductive contacts to couple with a plurality of pins between the plurality of inner pins and the plurality of outer pins as suggested by Huang figs. 23-26 embodiments because it would have been an obvious matter of design choice to have three rows of conductive contacts instead of two since applicant has not disclosed that having three rows over two is a critical factor of the functionality of the invention and it appears that the invention would perform equally well with two rows; it also would have been obvious for the benefit of improving the application of use of a memory module for robust computing purposes.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARCUS E HARCUM whose telephone number is (571)272-9986. The examiner can normally be reached Mon-Fri. 8am-5pm.
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/MARCUS E HARCUM/ Examiner, Art Unit 2831