Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21, 23-26, 28-31, 33-37 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 21, 26, and 31 recites the limitation "control the common operating frequency limit based on the identified number of active processor cores" in 14th line of the claim 21, 15th line of the claim 26, and 15th line of the claim 31. There is insufficient antecedent basis for this limitation in the claim. Furthermore, the claim does not disclose how number of active processor cores is identified. Therefore, the claims 21, 26, and 31 are indefinite for failing to particularly point out and distinctly claim the subject matter.
Regarding claims 23-25, 28-30, and 33-37, the claims 23-25, 28-30, and 33-37 inherit the deficiency of the independent claims 21, 26, and 31, as discussed above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21, 23-26, 28-31, and 33-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rotem et al. (United States Patent Application Publication US 2006/0149975), hereinafter Rotem, in view of Ananthakrishnan et al. (United States Patent Application Publication US 2019/0041962), hereinafter Ananthakrishnan, and further in view of Nguyen et al. (United States Patent Application Publication US 2020/0073456), hereinafter Nguyen.
Regarding claim 21, Rotem teaches one or more non-transitory computer-readable media comprising instructions that, when executed, are to cause a power control unit (PCU) of an electronic device to: for a set of processor cores with a common operating frequency limit, identify, for a first core of the set, a first weight; identify, for a second core of the set, a second weight; identify, for a third core of the set, a third weight, wherein the first, second, and third core operating voltages may be different from one another ([0023] “The memory subsystems may also include a read only memory (ROM) 32 such as a compact disk ROM (CD-ROM), magnetic disk, flash memory, etc.” [0024] “The activity can be determined by monitoring a state signal 40 (40a-40n) of each of the plurality of processor cores 12' and identifying whether each state signal 40 indicates that the corresponding core is active.” [0026] “The state signals 40 can also include information regarding performance levels. For example, the state signals 40 may indicate the performance level of each active core. Such a signal could be provided by ACPI performance state (Px state) signals.” State signals for plurality of cores are identified. Furthermore, the state signals include information regarding performance levels, such as ACPI performance state. Rotem also suggests that the processor cores are at different P states of the ACPI performance state.);
identify, based on the first weight, the second weight, and the third weight, an activity level for the set of processor cores ([0024] “The activity can be determined by monitoring a state signal 40 (40a-40n) of each of the plurality of processor cores 12' and identifying whether each state signal 40 indicates that the corresponding core is active.” Based on the state signals including performance levels of cores, active cores among the plurality of cores are identified, which indicates an activity level of the plurality of cores.); and
control the common operating frequency limit based on the identified number of active processor cores ([0015] “activity module 14 determines the number 18 of active cores in the plurality of processor cores 12 and selects a maximum operating point 17 for the active cores based on the number 18 of active cores.” Based on the number of active cores, a maximum operating point for the active cores are selected. Furthermore, as shown in TABLE I and [0016], the maximum operating point, which includes maximum operating frequency for the active cores, is identified for all the active cores, which is interpreted as the common operating frequency limit.).
However, Rotem does not explicitly teach a weight based on operating voltage; wherein the first, second, and third core operating voltages may be different from one another.
Ananthakrishnan teaches a weight based on operating voltage. ([0023] “It is to be noted that some examples and embodiments discussed in this disclosure refers specifically to P-state, where a P-state may be in accordance with the ACPI (Advanced Configuration and Power Interface) standard. However, the scope of this disclosure is not limited by merely P-state determination in accordance with the ACPI standard. For example, the principles of this disclosure may generally be applied to determining operating voltage and/or operating frequency, which may, or may not, be in accordance with P-states.” [0090] “The power state, such as the P-state of the core in an example, is an ACPI state, which may specify a frequency, voltage, and/or other operating parameters for the core.” The ACPI state, which is power state, such as the P-states of the core, specifies an operating voltage.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Rotem by incorporating the teaching of Ananthakrishnan of a weight based on operating voltage. They are all directed toward power management in a multi core processor. As recognized by Ananthakrishnan, the ACPI specifies power states, such as P-states, which determines operating voltage ([0023]). Thus, it would be obvious to combine the two well-known teaching of Rotem and the teaching of Ananthakrishnan.
However, Rotem in view of Ananthakrishnan does not teach wherein the first, second, and third weighs are further based, respectively, on a first core temperature, a second cored temperature, and a third core temperature.
Nguyen teaches wherein the first, second, and third weighs are further based, respectively, on a first core temperature, a second cored temperature, and a third core temperature ([0026] “Processor 202 measures a die temperature of one or more cores 204a-204d by sensor 210. Processor 202 determines the die temperature as measured by sensor 210 at module 212. Using the die temperature, processor 202 determines a temperature difference and measures the temperature difference against an activation point at modules 214-216. In response to the temperature difference being at most equal to the activation point, processor 202 adjusts the power limit by decreasing the power limit at module 218. At modules 220-222, based on a more recent die temperature, processor 202 determines a new temperature difference. In response to the new temperature difference being equal to or greater than the activation point, processor 202 increases the power limit as at module 222.” Temperature are measured at one or more cores, which suggests that temperature of three cores are measured. Then, based on the measured temperature of the cores, the power limit. The power of core is based on frequency of cores.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Rotem in view of Ananthakrishnan by incorporating the teaching of Nguyen of wherein the first, second, and third weighs are further based, respectively, on a first core temperature, a second cored temperature, and a third core temperature. They are all directed toward controlling operating parameters of cores. As recognized by Nguyen, higher temperature of cores affects the performance of the cores ([0014]). Also, it is well-known in the art before the effective filing date of the claimed invention, the high temperature can cause permanent damage to the cores. By keeping the temperature of the cores below its thermal design point, the damage can be prevented. Therefore, it would be advantageous to incorporate the teaching of Nguyen of wherein the first, second, and third weighs are further based, respectively, on a first core temperature, a second cored temperature, and a third core temperature in order to improve performance and prevent damage.
Regarding claim 23, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the one or more non-transitory computer-readable media of claim 21, as discussed above.
Ananthakrishnan further teaches wherein the first, second, and third weights are further based, respectively, on a first core operating frequency, a second core operating frequency, and a third core operating frequency ([0023] “It is to be noted that some examples and embodiments discussed in this disclosure refers specifically to P-state, where a P-state may be in accordance with the ACPI (Advanced Configuration and Power Interface) standard. However, the scope of this disclosure is not limited by merely P-state determination in accordance with the ACPI standard. For example, the principles of this disclosure may generally be applied to determining operating voltage and/or operating frequency, which may, or may not, be in accordance with P-states.”).
Regarding claim 24, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the one or more non-transitory computer-readable media of claim 21, as discussed above.
Rotem, as modified above, further teaches wherein the first, second, and third weights are un-related to activity states of the processor cores ([0025] “processor power states are designated as CO, Cl, C2, C3,...Cn. The shallowest, CO, power state is an active power state where the CPU executes instructions. The Cl through Cn power states are processor sleeping states where the processor consumes less power and dissipates less heat than leaving the processor in the CO state. While in a sleeping state, the processor core does not execute any instructions.”).
Regarding claim 25, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the one or more non-transitory computer-readable media of claim 21, as discussed above.
Rotem, as modified above, further teaches wherein the common operating frequency limit is based on correlation of the identified number of active cores with a plurality of pre-identified frequency limits and a plurality of pre-identified numbers of active processor cores, wherein respective frequency limits of the plurality of pre-identified frequency limits are related to a respective number of active processor cores of the plurality of pre-identified numbers of active processor cores ([0027] “The activity module 14' can then search the configuration table 36 for an entry containing the number of active cores. A similar search could be conducted with respect to performance levels. Upon finding the entry, the activity module 14' may retrieve a maximum operating point, via the configuration table input 38, from the entry, where the maximum operating point enables a parameter such as frequency or core voltage to be limited.” “TABLE I” “# Active” “Max Freq.” A configuration table includes information or setting to select the maximum operating frequency, which is pre-identified, according to the number of active cores. Thus, the entry of the configuration table is pre-identified.).
Regarding claim(s) 26, 28-30, the claim(s) 26, 28-30 are the apparatus claims of the method claim(s) 21, 23-25. The claim(s) 26, 28-30 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the claim(s) 26, 28-30.
Rotem teaches an electronic device comprising: a multi-core processor that includes a plurality of processor cores; and a power control unit (PCU) coupled with the multi-core processor ([0021] “the processor 22 has an activity module 14', a plurality of processor cores 12' (12a'-12n') and a voltage and frequency controller 24.”),
wherein the PCU is configured to: for a set of processor cores with a common operating frequency limit, identify, for a first core of the set, a first weight based on a first core operating voltage; identify, for a second core of the set, a second weight based on a second core operating voltage; identify, for a third core of the set, a third weight based on a third core operating voltage, wherein the first, second, and third core operating voltages may be different from one another([0023] “The memory subsystems may also include a read only memory (ROM) 32 such as a compact disk ROM (CD-ROM), magnetic disk, flash memory, etc.” [0024] “The activity can be determined by monitoring a state signal 40 (40a-40n) of each of the plurality of processor cores 12' and identifying whether each state signal 40 indicates that the corresponding core is active.” [0026] “The state signals 40 can also include information regarding performance levels. For example, the state signals 40 may indicate the performance level of each active core. Such a signal could be provided by ACPI performance state (Px state) signals.” State signals for plurality of cores are identified. Furthermore, the state signals include information regarding performance levels, such as ACPI performance state. Rotem also suggests that the processor cores are at different P states of the ACPI performance state.);
identify, based on the first weight, the second weight, and the third weight, an activity level for the set of processor cores ([0024] “The activity can be determined by monitoring a state signal 40 (40a-40n) of each of the plurality of processor cores 12' and identifying whether each state signal 40 indicates that the corresponding core is active.” Based on the state signals including performance levels of cores, active cores among the plurality of cores are identified, which indicates an activity level of the plurality of cores.); and
control the common operating frequency limit based on the identified number of active processor cores ([0015] “activity module 14 determines the number 18 of active cores in the plurality of processor cores 12 and selects a maximum operating point 17 for the active cores based on the number 18 of active cores.” Based on the number of active cores, a maximum operating point for the active cores are selected. Furthermore, as shown in TABLE I and [0016], the maximum operating point, which includes maximum operating frequency for the active cores, is identified for all the active cores, which is interpreted as the common operating frequency limit.).
Ananthakrishnan teaches a weight based on operating voltage. ([0023] “It is to be noted that some examples and embodiments discussed in this disclosure refers specifically to P-state, where a P-state may be in accordance with the ACPI (Advanced Configuration and Power Interface) standard. However, the scope of this disclosure is not limited by merely P-state determination in accordance with the ACPI standard. For example, the principles of this disclosure may generally be applied to determining operating voltage and/or operating frequency, which may, or may not, be in accordance with P-states.” [0090] “The power state, such as the P-state of the core in an example, is an ACPI state, which may specify a frequency, voltage, and/or other operating parameters for the core.” The ACPI state, which is power state, such as the P-states of the core, specifies an operating voltage.).
Nguyen teaches wherein the first, second, and third weighs are further based, respectively, on a first core temperature, a second core temperature, and a third core temperature ([0026] “Processor 202 measures a die temperature of one or more cores 204a-204d by sensor 210. Processor 202 determines the die temperature as measured by sensor 210 at module 212. Using the die temperature, processor 202 determines a temperature difference and measures the temperature difference against an activation point at modules 214-216. In response to the temperature difference being at most equal to the activation point, processor 202 adjusts the power limit by decreasing the power limit at module 218. At modules 220-222, based on a more recent die temperature, processor 202 determines a new temperature difference. In response to the new temperature difference being equal to or greater than the activation point, processor 202 increases the power limit as at module 222.” Temperature are measured at one or more cores, which suggests that temperature of three cores are measured. Then, based on the measured temperature of the cores, the power limit. The power of core is based on frequency of cores.).
Regarding claim 33, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the PCU of claim 31, as discussed above.
Ananthakrishnan further teaches wherein the first, second, and third weights are further based, respectively, on a first core operating frequency, a second core operating frequency, and a third core operating frequency ([0023] “It is to be noted that some examples and embodiments discussed in this disclosure refers specifically to P-state, where a P-state may be in accordance with the ACPI (Advanced Configuration and Power Interface) standard. However, the scope of this disclosure is not limited by merely P-state determination in accordance with the ACPI standard. For example, the principles of this disclosure may generally be applied to determining operating voltage and/or operating frequency, which may, or may not, be in accordance with P-states.”).
Regarding claim 34, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the PCU of claim 31, as discussed above.
Rotem, as modified above, further teaches wherein the first, second, and third weights are un-related to activity states of the processor cores ([0025] “processor power states are designated as CO, Cl, C2, C3,...Cn. The shallowest, CO, power state is an active power state where the CPU executes instructions. The Cl through Cn power states are processor sleeping states where the processor consumes less power and dissipates less heat than leaving the processor in the CO state. While in a sleeping state, the processor core does not execute any instructions.”).
Regarding claim 35, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the PCU of claim 31, as discussed above.
Rotem, as modified above, further teaches wherein the common operating frequency limit is based on correlation of the identified number of active cores with a plurality of pre-identified frequency limits and a plurality of pre-identified numbers of active processor cores, wherein respective frequency limits of the plurality of pre-identified frequency limits are related to a respective number of active processor cores of the plurality of pre-identified numbers of active processor cores ([0027] “The activity module 14' can then search the configuration table 36 for an entry containing the number of active cores. A similar search could be conducted with respect to performance levels. Upon finding the entry, the activity module 14' may retrieve a maximum operating point, via the configuration table input 38, from the entry, where the maximum operating point enables a parameter such as frequency or core voltage to be limited.” “TABLE I” “# Active” “Max Freq.” A configuration table includes information or setting to select the maximum operating frequency, which is pre-identified, according to the number of active cores. Thus, the entry of the configuration table is pre-identified.).
Regarding claim 36, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the PCU of claim 35, as discussed above.
Rotem, as modified above, further teaches wherein the identified frequency limit is based on identification that the identified number of active cores is between two of the plurality of pre-identified numbers of active processor cores ([0027] “The activity module 14' can then search the configuration table 36 for an entry containing the number of active cores. A similar search could be conducted with respect to performance levels. Upon finding the entry, the activity module 14' may retrieve a maximum operating point, via the configuration table input 38, from the entry, where the maximum operating point enables a parameter such as frequency or core voltage to be limited.” “TABLE I” “# Active” “Max Freq.” The determined number of active cores is a certain number between two of the plurality of pre-identified number of active cores.).
Regarding claim 37, Rotem in view of Ananthakrishnan and further in view of Nguyen teaches all the limitations of the PCU of claim 36, as discussed above.
Rotem, as modified above, further teaches wherein the identified frequency limit is between two of the plurality of pre-identified frequency limits ([0027] “The activity module 14' can then search the configuration table 36 for an entry containing the number of active cores. A similar search could be conducted with respect to performance levels. Upon finding the entry, the activity module 14' may retrieve a maximum operating point, via the configuration table input 38, from the entry, where the maximum operating point enables a parameter such as frequency or core voltage to be limited.” “TABLE I” “# Active” “Max Freq.” When the determined number of active cores is a certain number between two of the plurality of pre-identified number of active cores, the corresponding maximum operating frequency is also between two maximum operating frequencies.).
Response to Arguments
Applicant’s arguments, see Remarks, filed 8/24/2026, with respect to the rejection(s) of claim(s) 21, 23-26, 28-31, and 33-37 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Nguyen. Nguyen teaches to increase or decrease of the power limit based on the temperature measured at one or more cores.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
PARK et al. (United States Patent Application Publication US 2015/0134995) teaches a system-on-chip including a symmetric multi-processor including a plurality of cores to determine maximum operating clock frequency for cores based on temperature and operating states of the cores.
Goffman-Vinopal et al. (United States Patent Application Publication US 2021/0157381) teaches determining a minimum and maximum allowable operating clock frequency for an IC having a plurality of processor cores based on a total number of active processor cores.
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/HYUN SOO KIM/Examiner, Art Unit 2176
