Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-8, 10-14, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (United States Patent US 10401938), hereinafter Lee, in view of Piga et al. (United States Patent Application Publication US 2018/0364782), hereinafter Piga.
Regarding claim 1, Lee teaches One or more non-transitory computer-readable media comprising instructions ([Col. 15 Lines 62-63] “The program instructions may be stored on a non-transitory computer readable storage medium.”) that, when executed, are to cause a power control unit (PCU) of an electronic device to: identify, based on a metric related to an activity level of a processor core of a multi- core processor of the electronic device, a first weight related to a first processor core of the multi-core processor; identify, based on the metric, a second weight related to a second processor core of the multi-core processor; identify, based on the metric, a third weight related to a third processor core of the multi-core processor, wherein the first weight, second weight, and third weight are different from one another ([Col. 10 Lines 21-32] “Field 312 stores a maximum weight. In various embodiments, a programmable maximum weight is maintained for each supported P-state. The maximum weight represents the maximum power supply load supported for the particular P-state. The term weight is used to identify a numerical value indicating a power supply load provided by the multiple cores of the multiple processor complexes on the single power plane. In various embodiments, larger weights indicate larger power supply loads and a larger possibility for voltage droop to occur while lower weights indicate smaller power supply loads and a smaller possibility for voltage droop to occur.” [Col. 13 Lines 20-25] “an intermediate value for a particular core is a bit vector indicating one or more of an active/sleep state and an operating mode of one or more operating modes the core is capable of using. In one embodiment, each bit position in the vector indicates a particular operating mode.” P-state is power state of a core, which is also associated with operating voltage, operating frequency, and weights. Current power modes and activity of each core and requests to change the operating modes from each core are monitored. Furthermore, as shown in FIG. 3, FIG. 4, and FIG. 6, the operating mode request and the current mode of each core is calculated or weighted to determine the total weight, which is to determine the change of the requested operating modes.).
However, Lee does not teach to identify, based on the first weight, the second weight, and the third weight, a number of active processor cores of the multi-core processor; and alter a frequency limit of the multi-core processor based on the identified number of active processor cores of the multi-core processor.
Piga teaches identify, based on the first weight, the second weight, and the third weight, a number of active processor cores of the multi-core processor ([0053] “The processing core activity determination logic 202 obtains (e.g., receives) processing core activity data 212 from, for example, one or more processing cores, such as the processing cores processing cores 122, 124, 126, 128 of FIG. 1…The processing core activity determination logic 202 determines, based on the processing core activity data 212, a processing core activity level for a processing core. The processing core activity level indicates, for example, a processor activity percentage over a period of time.” Based on the activity level, the number of active cores is determined.); and
alter a frequency limit of the multi-core processor based on the identified number of active processor cores of the multi-core processor ([0054] “The processing core workload sensitivity determination logic 204 then determines an activity deviation between the number of active processing cores and the expected number of active processing cores” [0055] “The processing core frequency determination logic 206 then adjusts the frequency of the one or more processing cores based on the processing core activity deviation data 208.” The frequency of cores is adjusted based on the activity deviation, which is determined based on the number of active cores. Thus, the frequency is adjusted based on the number of active cores.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee by incorporating the teaching of Piga to identify, based on the first weight, the second weight, and the third weight, a number of active processor cores of the multi-core processor; and alter a frequency limit of the multi-core processor based on the identified number of active processor cores of the multi-core processor. They are all directed toward adjusting operating modes of processor cores. As recognized by Piga, as SoCs are becoming increasingly complex, it is becoming important to understand SoC and workload interactions and manage power in a scalable way while optimizing for a Quality-of-Service ([0003]). By identifying number of active cores based on actual idle time of each core, accurate control of each core to adjust an operating mode, such as an operating frequency, can be achieved, which also improve the QoS and reduce a degrade of the performance and the system. Therefore, it would be advantageous to incorporate the teaching of Piga in order to improve the QoS and reduce a degrade of the performance and the system.
Regarding claim 2, Lee in view of Piga teaches all the limitations of the one or more non-transitory computer-readable media of claim 1, as discussed above.
Lee, as modified above, further teaches wherein the metric is related to a voltage of the processor core ([Col. 6 Lines 24-26] “the P-state is used to determine the operational voltage and operational frequency used by a component,”).
Regarding claim 4, Lee in view of Piga teaches all the limitations of the one or more non-transitory computer-readable media of claim 1, as discussed above.
Lee, as modified above, further teaches wherein the metric is related to a frequency of the processor core ([Col. 6 Lines 24-26] “the P-state is used to determine the operational voltage and operational frequency used by a component,”).
Regarding claim 5, Lee in view of Piga teaches all the limitations of the one or more non-transitory computer-readable media of claim 1, as discussed above.
Lee, as modified above, further teaches wherein the metric is un-related to an activity state of the processor core ([Col. 6 Lines 6-10] “a V complex for each of the processor complexes 260-270 and a V system for one or more other components in the computing system 200. There may be multiple supply voltages for the rest of the computing system.” Voltage or power consumption of components other than cores are considered.).
Regarding claim(s) 7, 8, and 10-12, the claim(s) 7, 8, and 10-12 are the method claims of the claim(s) 1, 2, 4-6. The claim(s) 7, 8, and 10-12 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Lee in view of Piga teaches all the limitations of the claim(s) 7, 8, 10-12.
Regarding claim(s) 13, 14, 16, and 17, the claim(s) 13, 14, 16, and 17 are the apparatus claims of the claim(s) 1, 2, 4, and, 5. Lee further teaches a power control unit (PCU) configured for use with an electronic device, wherein the PCU comprises: circuitry to communicatively coupled with a multi-core processor; and logic ([Col. 6 Lines 60-61] “the term "processor complex" is used to denote a configuration of one or more processor cores” [Col. 8 Lines 41-44] “the power state controller 278 includes queues for storing requests and control logic for determining operating modes for the processors 262A-262D and 272A-272D.”). The claim(s) 13, 14, 16, and 17 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Lee in view of Piga teaches all the limitations of the claim(s) 13, 14, 16, and 17.
Claim(s) 3, 9, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Piga as applied to claims 1, 7, and 13 above, and further in view of Crane et al. (United States Patent Application Publication US 2022/0075443), hereinafter Crane.
Regarding claim 3, Lee in view of Piga teaches all the limitations of the one or more non-transitory computer-readable media of claim 1, as discussed above.
However, Lee in view of Piga does not teach wherein the metric is related to a temperature of the processor core.
Crane teaches wherein the metric is related to a temperature of the processor core (Fig. 1 “Multi-core Processor 101” “Power Estimation Module 115” [0037] “per-core temperatures may also be received as metrics that may be used to compare to the total power consumed to obtain an estimated per-core power consumption value.”).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee in view of Piga by incorporating the teaching of Crane of wherein the metric is related to a temperature of the processor core. They are all directed toward controlling operating mode of cores. As recognized by Crane, heat can cause physical damage to the multi-core processor ([0038]). Thus, by monitoring temperature of the cores and controlling the cores to stay below high heat, the lifespan of the cores can be improved. Therefore, it would be advantageous to incorporate the teaching of Crane of wherein the metric is related to a temperature of the processor core in order to improve the lifespan of the cores.
Regarding claim(s) 9, the claim(s) 9 is the method claim of the claim(s) 3. The claim(s) 9 does not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Lee in view of Piga and further in view of Crane teaches all the limitations of the claim(s) 9.
Regarding claim(s) 15, the claim(s) 15 is the apparatus claim of the claim(s) 3. Lee further teaches a power control unit (PCU) configured for use with an electronic device, wherein the PCU comprises: circuitry to communicatively coupled with a multi-core processor; and logic ([Col. 6 Lines 60-61] “the term "processor complex" is used to denote a configuration of one or more processor cores” [Col. 8 Lines 41-44] “the power state controller 278 includes queues for storing requests and control logic for determining operating modes for the processors 262A-262D and 272A-272D.”). The claim(s) 15 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Lee in view of Piga and further in view of Crane teaches all the limitations of the claim(s) 15.
Claim(s) 6, 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Piga as applied to claims 1 and 13 above, and further in view of Shrall et al. (United States Patent US 9075556), hereinafter Shrall.
Regarding claim 6, Lee in view of Piga teaches all the limitations of the one or more non-transitory computer-readable media of claim 1, as discussed above.
However, Lee in view of Piga does not explicitly teach wherein the identified frequency limit is based on correlation of the identified number of active cores with a plurality of pre-identified frequency limits and a plurality of pre-identified numbers of active processor cores, wherein respective frequency limits of the plurality of pre-identified frequency limits are related to a respective number of active processor cores of the plurality of pre- identified numbers of active processor cores.
Shrall teaches wherein the identified frequency limit is based on correlation of the identified number of active cores with a plurality of pre-identified frequency limits and a plurality of pre-identified numbers of active processor cores, wherein respective frequency limits of the plurality of pre-identified frequency limits are related to a respective number of active processor cores of the plurality of pre-identified numbers of active processor cores (TABLE 1, FIG. 3 “320 Store Lower of Configurable Frequency Limit Values And Maximum Peak Frequency Values in Configuration Storage” “360 Limit Domain Operating Frequency To Resolved Value” “370 Enable Domain Operating Frequency At Requested Performance Level” TABLE 1 “Description” As shown in TABLE, which shows the frequency limits based on the number of active cores, the frequency limits for cores depending on a number of active cores are stored in the configuration storage. Thus, the frequency limit is determined according to the frequency limits based on the number of active cores stored in the configuration storage.).
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee in view of Piga by incorporating the teaching of Shrall of wherein the identified frequency limit is based on correlation of the identified number of active cores with a plurality of pre-identified frequency limits and a plurality of pre-identified numbers of active processor cores, wherein respective frequency limits of the plurality of pre-identified frequency limits are related to a respective number of active processor cores of the plurality of pre-identified numbers of active processor cores. They are all directed toward controlling operating frequency of cores. As recognized by Shrall, by storing frequency limits dependent on a given number of active cores, frequency limit values can be provided without excursion, which improves efficiency and speed ([Col. 4 Lines 29-40], [Col. 6 Lines 58-59]). Therefore, it would be advantageous to incorporate the teaching of Shrall of wherein the identified frequency limit is based on correlation of the identified number of active cores with a plurality of pre-identified frequency limits and a plurality of pre-identified numbers of active processor cores, wherein respective frequency limits of the plurality of pre-identified frequency limits are related to a respective number of active processor cores of the plurality of pre-identified numbers of active processor cores in order to improve the performance of the system.
Regarding claim(s) 18, the claim(s) 18 is the apparatus claim of the claim(s) 6. Lee further teaches a power control unit (PCU) configured for use with an electronic device, wherein the PCU comprises: circuitry to communicatively coupled with a multi-core processor; and logic ([Col. 6 Lines 60-61] “the term "processor complex" is used to denote a configuration of one or more processor cores” [Col. 8 Lines 41-44] “the power state controller 278 includes queues for storing requests and control logic for determining operating modes for the processors 262A-262D and 272A-272D.”). The claim(s) 18 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Lee in view of Piga and further in view of Shrall teaches all the limitations of the claim(s) 18.
Regarding claim 19, Lee in view of Piga and further in view of Shrall teaches all the limitations of the CPU of claim 18, as discussed above.
Shrall further teaches wherein the identified frequency limit is based on identification that the identified number of active cores is between two of the plurality of pre-identified numbers of active processor cores ([Col. 4 Lines 55-58] “for an N-core processor, N values are provided where each value corresponds to a maximum operating frequency possible for the particular silicon-based processor when the given number of cores is active.” As the number of active cores are determined, since the identified number is between two numbers, the identified number of active cores must be between two of the plurality of pre-identified number of active processor cores.).
Regarding claim 20, Lee in view of Piga and further in view of Shrall teaches all the limitations of the CPU of claim 20, as discussed above.
Shrall further teaches wherein the identified frequency limit is between two of the plurality of pre-identified frequency limits ([Col. 5 Lines 1-6] “Note that for the sets of frequencies present in both storage 210 and storage 220, typically with a fewer number of active cores a higher operating frequency is possible. Thus when only one core is active, the operating frequency can be higher than when N cores are active.” As the number of active cores gets bigger, the corresponding operating frequency gets lower. Furthermore, as discussed above, since the number of active cores is between a number lower than the number of active cores and another number higher than the number of active cores, the corresponding operating frequency must be between two operating frequencies that corresponds to other two number of active cores accordingly.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Rotem et al. (United States Patent Application Publication US 2006/0149975) teaches to manage operating points based on determined number of active cores and/or active core performance levels.
Goffman-Vinopal et al. (United States Patent Application Publication US 2021/0157381) teaches managing clock frequency in a multi-core IC including determining a minimum allowable operating frequency and maximum allowable operating clock frequency for the IC having a plurality of processor cores.
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/HYUN SOO KIM/Examiner, Art Unit 2176