DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gauthier et al. (US 9,197,403 B2), in view of Liao et al. ("A 7.7~10.3GHz 5.2mW -247.3dB-FOM Fractional-N Reference Sampling PLL with 2nd Order CDAC Based Fractional Spur Cancellation In 45nm CMOS," 2020 IEEE Custom Integrated Circuits Conference (CICC), March 2020, 4 pages), as cited in IDS 06/05/2025.
Regarding Claim 1, Gauthier et al. discloses in Figure 1 an apparatus, comprising:
a phase-locked loop (PLL) (110) comprising a phase detector (112), a voltage-controlled oscillator (VCO) coupled to the main sampler (115), and a fractional divider coupled to the VCO (114); and
a compensation circuit coupled to the PLL (120, 130, 140), the compensation circuit is to compensate an output of the main sampler to provide a compensated control signal for the VCO (using VCO Mod. within 130);
but does not explicitly teach a phase-locked loop (PLL) comprising a converter to provide an analog waveform from an input reference clock signal and a main sampler coupled to the converter to sample the analog waveform.
Liao et al. teaches in Figure 2 a phase-locked loop (PLL) comprising a converter to provide an analog waveform from an input reference clock signal (Ref-Sampling Phase Detector, 8-bit D-DAC) and a main sampler coupled to the converter to sample the analog waveform (Sampling Cap).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the PLL architecture of Liao et al. with the PLL apparatus of Gauthier et al. for the purpose of “consuming ignorable power” and suppressing “sampling noise and noise from reference voltages”. Liao et al., page 2, Col. 2, last 6 lines before Section “B. Second Order CDAC based Quantization Error Canceller”.
Allowable Subject Matter
Claims 14-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 14, the prior art does not disclose, teach or suggest a compensation circuit for a phase-locked loop (PLL), the compensation circuit comprising:
a digital-to-analog converter (DAC);
an integrator to integrate the amplified ripples; and
a feedback path from an output of the integrator to the DAC, wherein the DAC is to update its output based on a feedback signal on the feedback path;
in combination with all the other claimed limitations.
Claims 15-20 are allowed for depending from Claim 14.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 2-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art does not disclose, teach or suggest the apparatus, wherein to compensate the output of the main sampler, the compensation circuit is to provide a stepped waveform which increases in magnitude in consecutive clock cycles of the input reference clock signal;
in combination with all the other claimed limitations.
Claim 3 is objected to for depending from Claim 2.
Regarding Claim 4, the prior art does not disclose, teach or suggest the apparatus, wherein the PLL further comprises a no overlap clock coupled to the fractional divider, the no overlap clock is to provide a first clock signal and a second clock signal to control respective switches in the main sampler to provide a sample and hold capability for the main sampler;
in combination with all the other claimed limitations.
Claims 5-11 are objected to for depending from Claim 4.
Regarding Claim 12, the prior art does not disclose, teach or suggest the apparatus, wherein
the compensation circuit comprises a compensation sampler coupled to an output of the DAC, an output of the compensation sampler is coupled to the output of the main sampler,
in combination with all the other claimed limitations.
Claim 13 is objected to for depending from Claim 12.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wu et al. (US 9,735,670 B2) teaches a “power factor correction conversion device and control method thereof” (title), wherein Figure 2 further details the power factor correction device to include both a control circuit and a ripple calculation circuit,
but does not explicitly disclose the details within the ripple calculation circuit, including an integrator to integrate the amplified ripples; and a feedback path from an output of the integrator to the DAC, wherein the DAC is to update its output based on a feedback signal on the feedback path; as, for example, recited in Claim 14.
Salle et al. (US 10,367,464 B2) teaches a “digital synthesizer, communication unit and method therefor” (title), wherein Figure 3 further details a digital phase locked loop, including a frac TDC 370, a TDC decoder 350, a period normalization 375 and adder 357,
but does not explicitly disclose a feedback path from an output of the integrator to the DAC, wherein the DAC is to update its output based on a feedback signal on the feedback path; as, for example, recited in Claim 14.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIANA J. CHENG/Primary Examiner, Art Unit 2849