DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 21 are presented for examination.
Response to Amendment
The rejection of claims 1, 6 to 8, 11, 16 and 17 as being rejected under 35 U.S.C. 103 as obvious over Sugimura et al. is withdrawn.
Response to Arguments
Applicant’s arguments, see page 1, filed 4-27-2026, with respect to claims 11 and 13 have been fully considered and are persuasive. The objection of claim 13 has been withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 11 and 13 is rejected under 35 U.S.C. 103 as being unpatentable over Sugimura et al. (USPAP 2013/0231887 A1).
Claims 11 and 13:
Sugimura substantially teaches the claimed invention. Sugimura teaches a testing apparatus that tests a device under test (DUT) and includes one or more testing modules, the testing apparatus comprising: testing DUTs (300) either sequentially one at a time in a continuous series or may test the DUTs one at a time in an interrupted series (see fig. 1 and par. 0028). Sugimura teaches that the testing apparatus includes a plurality of control apparatuses (18) that can execute a test program managed by a different user to control the operation of the testing sections (32) assigned thereto (see par. 0042). Sugimura teaches that the testing apparatus enables the executed test programs to be edited for individual users, and a user can prepare overlapping test program that can execute overlapping tests (see par. 0042 to 0043).
Sugimura teaches that the control apparatus executes a first, second and third thread (40-1, 40-2, & 40-3) according to a plurality of test programs and a test module (20) transmits the test results of each test program to the control apparatus (see par. 0044). Sugimura teaches that the test module includes a first and a second memory bank (31-1 and 31-2) for storing the test results of each test section (see par. 0046).
Sugimura teaches that performing overlapping tests on the DUTs, the order in which each test started and ended may be reversed (see par. 0058 et seq.). Sugimura teaches that each thread executes a prescribed test item, and a user preferably sets in the test program an indication of whether each thread is to perform parallel testing or overlapping testing (see par. 0064).
Sugimura teaches that each control apparatus stores identification information when the execution of a thread corresponds to a test program (see par. 0096). Sugimura teaches that the identification information contains a context number, and the context number identifies the thread that issues the testing command (see par. 0098 et seq.).
Sugimura fails to specifically teach the limitation of: “wherein the plurality of test streams conforms to a non-memory protocol;” however, this teaching is obvious to the teachings of Sugimura because Sugimura teaches that a testing apparatus for testing DUTs perform either overlapping test or parallel testing based on test signals developed by one or more users. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Sugimura to include the limitation of: “wherein the plurality of test streams conform to a non-memory protocol” because Sugimura teaches that performing a plurality of test in either an overlapping form or in a parallel form on a plurality of DUTs reduces testing time (see par. 0054). This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a testing method and an apparatus for performing a plurality of testing of DUT’s in an overlapping form or parallel form to reduce testing time as taught by Sugimura (see par. 0054 et seq.).
As to the other limitation of the claims, Sugimura teaches that fails to specifically teach that the testing apparatus includes a connecting section (24) that connects the control apparatus to the test modules (20) (see if. 1 and par. 0036). Sugimura teaches that a universal or specialized high-speed serial bus may be used to connect the system controller to the control apparatus, which reads on “plurality of test streams confirm to the advanced eXtensible interface (AXI) protocol” (see par. 0039).
Allowable Subject Matter
Claims 12 and 14 to 18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 1 to 10, and 19 to 21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the prior art made of record teaches the system, method and apparatus for testing multiple DUT’s as detailed above; however, the prior art made of record, taken alone or in combination fails to teach or fairly suggest or render obvious the combination of elements with the novel element of the claims of: wherein the testbench processor is formed at least in part in field programmable gate array (FPGA) programmable logic circuitry.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shelly A Chase/Primary Examiner, Art Unit 2112
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