DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 21 are presented for examination.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6 to 8, 11, 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sugimura et al. (USPAP 2013/0231887).
Claim 1:
Sugimura substantially teaches the claimed invention. Sugimura teaches a test method and test apparatus for testing one or more device under test (DUT), the test apparatus (10) comprising a control apparatus (18) generating a plurality of test programs based on controls received from a system control section (26) (see fig. 1 and par. 0038). Sugimura teaches that the system control section stores in advance information relating to the testing that is necessary for executing the test items designated by the test programs, which reads on “memory comprising instructions to generate a plurality of test streams to send to a device under test” (see par. 0064). Sugimura teaches that control apparatuses (18) (“a testbench processor”) sequentially execute the test program for testing the one or more DUT’s (300) based on an assigned thread from a plurality of thread (40) (see par. 0030).
Sugimura teaches that a test module (20) includes a testing section (32) that tests the DUT using the received thread and corresponding testing program (see par. 0031). Sugimura teaches that a site number is allocated to each control apparatus and is stored in an assignment storage section (62) of the interface section (34) of the test module (see fig, 7, par. 0079 and 0093). Sugimura teaches that the command may include a context number that identifies the thread that send the command (see par. 107).
Sugimura dose not specifically teach a thread execution circuitry that switches context based on context identifiers corresponding to respective test streams of the plurality of test streams; however, this teaching is obvious to the teaching of Sugimura because Sugimura teaches that the test apparatus includes an editing apparatus (28) that enables a user to edit the execution order of the test program executed by the control apparatus (see par. 0039). Sugimura also teaches that configuration information associated with the testing section of the test module is used to decide the type of testing to be done by the testing program and its associated thread (see par. 0064).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Sugimura to include the limitation of “using thread execution circuitry that switches context based on context identifiers corresponding to respective test streams of the plurality of test streams” in the testing apparatus of Sugimura because Sugimura teaches that a method to reduce testing time for testing DUT’s includes a testing program being applied to the DUT’s through a test module being adjusted through an editing apparatus managed by a user. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a testing apparatus for reducing the testing time for testing DUT’s by applying test programs being adjusted by a user as taught by Sugimura (see par. 0043 and 0064).
As per claim 6, Sugimura teaches that the test apparatus may perform a single test testing one DUT at a time and may test one type of DUT with a single control apparatus, which reads on “wherein the testbench processor comprises a single instance of the thread execution circuitry” (see par. 0028 to 0029).
As per claims 7 and 8, Sugimura teaches that the control apparatus generates the test program and read or write commands for testing the DUT’s and the interface section (34) (response region) of the test module includes multiple memories for storing the test results (see par. 0035 and 0046). Sugimura teaches that the interface section includes components such as DUT map table (68), input/output section (64) and accessing section (74) for evaluating the testing of the DUT’s (see fig. 7 and par. 0078 et seq.).
Claim 11:
Sugimura substantially teaches the claimed invention. Sugimura teaches a test method and test apparatus for testing one or more device under test (DUT), the test apparatus (10) comprising a control apparatus (18) generating a plurality of test programs based on controls received from a system control section (26) (see fig. 1 and par. 0038). Sugimura teaches that the test apparatus includes a plurality of test modules (20) coupled to one or more device under test (DUT) (300) (see par. 0031). Sugimura teaches that testing the DUT’s includes identification information indicating sets of a control apparatus being stored in a storage section of the interface section (34) of the test module (see par. 0079). Sugimura teaches that a site number is allocated for each control apparatus and a context number is allocated for each thread 40 (see par. 0093 et seq.).
Sugimura teachers that each control apparatus writes the identification information i.e. the set of a site number and a context number prior to the execution of a new test program (see par. 0095 et seq.). Sugimura teaches that the test module includes a test interface having an input/output section (64) for judging whether the module number contained in the received command matches the module number of the test module as well as, judging if the set of site number and context number are contained in the received command matches (see par. 0109 to 0111).
Sugimura fails to specifically teach the limitation of “an integrated circuit to generate the plurality of test streams using an instance of thread execution circuitry that switches context based on the identifier; however, this teaching is obvious to the teachings of Sugimura since Sugimura teaches that a pointer storage section (70) of the interface section of the testing module may perform a switching operation switching the control apparatus based on the set of site number and a context number contained in the command (see par. 0085).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the testing apparatus of Sugimura to include the limitation of “an integrated circuit to generate the plurality of test streams using an instance of thread execution circuitry that switches context based on context identifiers” since Sugimura teaches that to reduce testing time for testing DUT’s includes a testing program being applied to the DUT’s through a test module that includes a pointer storage section for switching the control apparatus based on a set of site number and a context number contained in a command. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a testing apparatus for reducing the testing time for testing DUT’s as taught by Sugimura (see par. 0010).
As per claims 16 and 17, Sugimura teaches that the control apparatus generates the test program and read or write commands for testing the DUT’s and the interface section (34) (response region) of the test module includes multiple memories for storing the test results (see par. 0035 and 0046). Sugimura teaches that the interface section includes components such as DUT map table (68), input/output section (64) and accessing section (74) for evaluating the testing of the DUT’s (see fig. 7 and par. 0078 et seq.).
Allowable Subject Matter
Claims 2 to 5, 9 to 10, 12 to 15 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 19 to 21 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art teaches a test method and a test apparatus for testing one or more DUT’s as detailed above; however, the prior art made of record, fails to teach or fairly suggest or render obvious the combination of elements with the novel element of: thread execution circuitry comprising: “a first generator circuitry to generate a dynamic component of a test stream associated with the context identifier based on the command instructions;” and “recovery control circuitry to issue recovery instructions based on the context identifier of the response.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hilliges et al. (USPAP 2024/0369615) teaches an automated test equipment for testing one or more device under test.
Robertson et al. (USPAP 2020/0272701) teaches a system and method of verifying hardware that includes software configured to control its operation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/ Primary Examiner, Art Unit 2112