Prosecution Insights
Last updated: April 19, 2026
Application No. 17/971,109

AVOIDING RAID ARRAY OVERDRIVE USING NONVOLATILE MEMORY IN CACHE

Non-Final OA §101§103
Filed
Oct 21, 2022
Examiner
BERTRAM, RYAN
Art Unit
2137
Tech Center
2100 — Computer Architecture & Software
Assignee
International Business Machines Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
92%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
598 granted / 677 resolved
+33.3% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
12 currently pending
Career history
689
Total Applications
across all art units

Statute-Specific Performance

§101
7.0%
-33.0% vs TC avg
§103
48.2%
+8.2% vs TC avg
§102
23.5%
-16.5% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 677 resolved cases

Office Action

§101 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statement (IDS) submitted on 10/21/2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Interpretation Claims 5 and 7 are method claims interpreted, subject to the broadest reasonable interpretation, to include contingent limitations which do not need to be disclosed in the prior art (see MPEP 2111.04(II)) in order to reject the claim as a whole. Only those steps that must be performed are considered. In particular, claims 5 and 7 recite determining whether the cache has sufficient space for the extent. However, claim 5 does not recite any steps/limitations to be performed if the cache does not have sufficient space, and claim 7 does not recite any steps/limitations to be performed if the cache does have sufficient space. Accordingly, the only limitation of claim 5 and 7 that are required to be performed is the determination of whether the cache has sufficient space for the extent. Claims 5 and 7 may be combined to avoid such a contingent method claim interpretation. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 8-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because claims 8-14 are directed to a computer readable medium. Support in the specification, specifically paragraph 28, specifies that the medium may be implemented using a non-exhaustive list of storage device examples. Therefore, the computer readable medium may, under a broadest reasonable interpretation, be implemented using wireless techniques such as signals. As such, the claims are not limited to statutory subject matter and are therefore non-statutory. See M.P.E.P. 2106.1, which states, "When nonfunctional descriptive material is recorded on some computer- readable medium, in a computer or on an electromagnetic carrier signal, it is not statutory since no requisite functionality is present to satisfy the practical application requirement. Merely claiming nonfunctional descriptive material, i.e., abstract ideas, stored on a computer-readable medium, in a computer, or on an electromagnetic carrier signal, does not make it statutory." The Examiner suggests amending the claims to recite a “non-transitory” computer readable medium in order to overcome the rejection. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-2, 4, 8-9, 11, 15-16 and 18 rejected under 35 U.S.C. 103 as being unpatentable over Applicant’s Admitted Prior Art (AAPA) in view of Gupta et al. (US 2021/0334038) and further in view of Traut et al. (US 2015/0169450). Regarding claim 1, AAPA discloses a computer-implemented method, comprising: detecting overdrive of a RAID array [see paragraph 2; SSD becomes overdriven]; selecting an extent residing, at least in part, in the overdriven RAID array; staging, from the overdriven RAID array, data from the extent; freeing the original extent space in the overdriven RAID array [see paragraphs 4-5; data from a chosen extent is staged to a memory (cache) to free the data from the source array to release to overdrive condition]; destaging the extent data in the cache to a target RAID array; [see paragraph 5; extent data is then destaged from memory to target RAID array (the act of destaging data frees it from the memory/cache)]. AAPA does not expressly disclose a part of the extent resides in the cache, and that data missing from the extent is staged from storage to the cache. Gupta discloses a RAID storage system in which RAID strides (analogous to extents) are cached in cache memory. Prior to destaging the strides, missing data from the strides are staged to the cache memory [see paragraph 40]. Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the caching techniques in the system of AAPA. The motivation for doing so would have been to improve destage performance and allow data to be destaged from the cache using a single write operation [see Gupta, paragraphs 4 & 34]. Therefore, it would have been obvious to combine Gupta with AAPA for the benefits listed above, to obtain the invention as specified in claims 1-2, 4, 8-9, 11, 15-16 and 18. The combination of AAPA and Gupta does not expressly disclose and freeing space in the cache corresponding to the extent in response to completing the destaging Traut discloses a storage system utilizing a cache memory. When data is destaged from the cache, the cache space is freed up [see paragraph 4]. Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the cache freeing teachings of Traut in the system of Gupta and AAPA. The motivation for doing so would have been al allow the cache to accept new write requests [see Traut, paragraph 4]. Therefore, it would have been obvious to combine Traut with AAPA and Gupta for the benefits listed above, to obtain the invention as specified in claims 1-2, 4, 8-9, 11, 15-16 and 18. Regarding the claim 2, the combination discloses the computer-implemented method of claim 1, wherein detecting overdrive of the RAID array includes determining whether a write rate of the RAID array is above a write rate-based threshold [see AAPA, paragraph 2; SSD becomes overdriven by a high write workload]. Regarding claim 4, the combination discloses the computer-implemented method of claim 1, comprising launching write intercept for the extent [see AAPA, paragraph 5; write intercepts are performed]. Claims 8-9, 11, 15-16 and 18 recite similar limitations to that of claims 1-2 and 4 and are rejected using the same citations and interpretations. Claims 3, 5, 10, 12, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Gupta and Traut and further in view of Liu et al. (US 5,623,632). Regarding claim 3, the combination of AAPA, Gupta and Traut discloses the method of claim 1. The combination does not expressly disclose staging and destaging are performed in parallel. Liu discloses a storage system that utilizes a cache memory. In a write-through mode, data is written to the cache and destaged to storage at the same time (parallel) [see Col. 1, lines 14-23]. Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the parallel writing of Liu in the system of AAPA, Gupta and Traut. The motivation for doing so would have been to insure data consistency [see Liu, Col. 1, lines 14-23]. Therefore, it would have been obvious to combine Liu with AAPA, Gupta and Traut for the benefits listed above, to obtain the invention as specified in claims 3, 10 and 17. Regarding claim 5, the combination discloses the computer-implemented method of claim 1, comprising determining whether the cache has sufficient space for the extent [see Trout, paragraph 3; if space is available in cache], and in response to determining that the cache has sufficient space for the extent, using the cache as tier 0 for the extent until cache space is needed and/or the extent is determined to be cold [see Liu, Col. 1 line 14-24; in a write-back mode, data is maintained in cache for read/write accesses (interpreted as acting as tier 0) until space is needed in the cache]. Claims 10, 12, 17 and 19 recite similar limitations to that of claims 5 and 7 and are rejected using the same citations and interpretations. Claims 7, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over AAPA in view of Gupta and Traut and further in view of Bauer et al. (US 8,151,077). Regarding claim 7, the combination of AAPA, Gupta and Traut discloses the method of claim as discussed above. The combination does not expressly disclose determining whether the cache has sufficient space for the extent, and in response to determining that the cache does not have sufficient space for the extent, using the cache as a tunnel to stage the missing data from the overdriven RAID array to the cache and destage the data to the target RAID array simultaneously. Bauer discloses a storage system that utilizes a cache. When the cache is fully, it may be set to a write-through mode (interpreted the same as the claimed “tunnel”), wherein a write-through stores data to the cache and storage simultaneously [see Col. 2, lines 20-30]. Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the caching techniques of Bauer in the system of AAPA, Gupta and Traut. The motivation for doing so would have been to enhance processing efficiency [see Bauer, Col. 2, lines 20-30]. Therefore, it would have been obvious to combine Bauer with Gupta, AAPA and Traut for the benefits listed above, to obtain the invention as specified in claims 7, 14 and 20. Claims 14 and 20 recite similar limitations to that of claim 7 and are rejected using the same citations and interpretations. Allowable Subject Matter Claims 6, 13 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Zhang (US 2020/0272352) further teaches maintaining a mapping table for extents, and updating a mapping from a source device to a target device after migrating the extent. However, the prior art of record fails to disclose or render obvious the claim limitations directed towards updating a volume mapping table to directly point to the extent in the cache to improve the cache hit rate for the extent. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Gao (US 2019/0129815) – Generally teaches a storage system for migrating extents directly from a source storage device to a target storage device when the source storage is nearing an end-of-life. Sreedhar (US 2017/0329674) – Generally teaches using a cache to reduce rebuild time for data stored in degraded virtual disks. Montgomery (US 2012/0059994) – Generally teaches the use of a specific migration cache to move extents from one storage device to another. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RYAN BERTRAM/Primary Examiner, Art Unit 2137
Read full office action

Prosecution Timeline

Oct 21, 2022
Application Filed
Nov 01, 2023
Response after Non-Final Action
Dec 01, 2025
Non-Final Rejection — §101, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
92%
With Interview (+4.2%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 677 resolved cases by this examiner. Grant probability derived from career allow rate.

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