DETAILED ACTION
Claims 1-20 are present in the current application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, 8, 9, 13, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over “Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor” by Capalija et al. in view of U.S. Pub. No. 2016/0357608 A1 to Gupta et al. and further in view of U.S. Pub. No. 2014/0282579 A1 to Smiley et al.
As to claim 1, Capalija teaches a hardware retire circuit comprising:
a plurality of input queues (Task Queue/”…Fig. 6 shows the task queue unit as composed of four different queues…”), each input queue corresponding to an input stream of tasks and being configured to store input task identifiers (identifiers/taskq_ID) corresponding to tasks of the input stream (Task Queue figure 6/Section 4.4); and
processing logic configured to:
receive a completed task event (Task Completion Status Queue figure 6/Section 4.4); and
determine an input task at a head of an input queue for retirement (“…retire unit monitors the status is set of the task at the head of the status queue (the oldest task in flight)…” Section 4.4).
Capalija is silent with reference to determine whether a completed task queue identifier and a completed task identifier of the completed task event match an input task identifier of an input task at a head of an input queue having an input queue identifier corresponding to the completed task queue identifier,
in response to determining a match, pop the task at the head of the input queue and output a task retirement event corresponding to the input task and wherein each input queue of the plurality of input queues is associated with a corresponding input queue identifier.
Gupta teaches determine whether a completed task queue identifier (Reorder List 28) and a completed task identifier (Task A1/Tasks B1/ A3 /Task C1) of the completed task event match an input task identifier of an input task at a head of an input queue (oldest task) having an input queue identifier corresponding to the completed task queue identifier (figure 6) and
in response to determining a match, pop the task at the head of the input queue and output a task retirement event corresponding to the input task (Process Block 64) (“…At epoch t2, and referring also to FIG. 6, it is assumed for this example that task A1 completes. Because task A1 is the oldest task in the reorder list 28, as determined by decision block 62, it is removed from the reorder list 28 (retired) as indicated by process block 64. As will be discussed in more detail below, there was no memory access by this task A1, so the remaining process blocks of FIG. 6 may be skipped and the program loops back to decision block 62. If A1 had accessed memory and had been enrolled in the request list 42, that entry in the request list 42 would be removed at process block 64 as will be discussed below…Referring still to FIGS. 4, 5 and 6, at epoch t4, tasks B1 and A3 complete. New tasks C1 and B82 are allocated to processors 12 and identifiers for these tasks 20 are added to the reorder list 28, not at the end but according to the sequential execution order so that they follow task B1 and move task A2 and other pre-existing tasks to the left, This movement is provided by determining the sequential execution number 52 of tasks C1 and B2 and comparing those numbers to the sequential execution number associated with the tasks currently in the reorder list 28 being part of the sequential order store 32 so that all tasks in the reorder list are in the order of their sequential execution numbers 52. Per decision block 62, task B1 is retired as being a completed task that is the oldest task in the reorder lists 28…As shown at epoch t5, task C1 may then complete. Because task C1 is now the oldest task in the reorder list 28, at decision block 62, it is removed from the reorder list 28 and its write token 40 is returned and its checkpoint data is released per process block 65. Because C1 is retired, its information is removed from the request list 42. Because C1 is complete, the dependent task D1 may now be re-allocated…” paragraphs 0055/0063/0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Capalija with the teaching of Gupta because the teaching of Gupta would improve the system of Capalija by providing a technique for reclaiming resources after execution to allow for other processes to use the resources.
Smiley teaches wherein each input queue of the plurality of input queues is associated with a corresponding input queue identifier (Job Rings (0/1/M) 230A-C) (“…Incoming jobs from a higher-level processor, such as application processor 110 of FIG. 1, that are awaiting processing by processing engine 200 may be maintained in multiple job ring queues, shown as job ring 0-M 230A-C. In one embodiment, the job rings 230A-C may be located in memory close to the protocol processors 240A-C. However, in other embodiment, job rings 230A-C may be located in system memory near the assigning application processor. Job rings 230A-C may be implemented as hardware, software, firmware, or any combination of the above. For example, each job ring 230A-C may be implemented as a circular buffer. The job rings 230A-C may be configured to support the jobs (e.g., tasks) associated with one individual high-level processing thread of the higher-level processor. Each job ring 230A-C may support a unique number of incoming jobs, as shown with depths A, B, C in the FIG. 2…In one embodiment, each job ring 0-M 230A-C includes a request ring portion and a response ring portion. The request ring may include the job entries waiting to be processed by processing engine 200. The response ring may include the job entries that originated in the request ring and have been completely processed by the processing engine 200. The job entries in the response ring are to be retired back to the higher-level processor. Note that in embodiments of the disclosure, the number of protocol processors 240A-C does not have to match the number of coprocessors 252A-252B or job rings 230A-C…” paragraphs 0028/0029).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Capalija and Gupta with the teaching of Smiley because the teaching of Smiley would improve the system of Capalija and Gupta by providing a technique for concurrently processing jobs to allow for low latency in computing.
As to claim 2, Capalija teaches the hardware retire circuit of claim 1, further comprising a memory storing a ready-to-retire table storing a plurality of entries corresponding to completed task events previously received by the hardware retire circuit (figure 6/Task Completion Status Queue), wherein the processing logic is further configured to, after popping the task at the head of the input queue (“…retire unit monitors the status is set of the task at the head of the status queue (the oldest task in flight)…” Section 4.4).
Gupta teaches determining whether a second input task identifier of a second input task at an updated head of the input queue and the input queue identifier match an entry in the ready-to-retire table (figure 6/Task Completion Status Queue); and in response to determining a match: pop the task at the updated head of the input queue; remove the second input task from the ready-to-retire table; and output a second task retirement event corresponding to the second input task (“…At epoch t2, and referring also to FIG. 6, it is assumed for this example that task A1 completes. Because task A1 is the oldest task in the reorder list 28, as determined by decision block 62, it is removed from the reorder list 28 (retired) as indicated by process block 64. As will be discussed in more detail below, there was no memory access by this task A1, so the remaining process blocks of FIG. 6 may be skipped and the program loops back to decision block 62. If A1 had accessed memory and had been enrolled in the request list 42, that entry in the request list 42 would be removed at process block 64 as will be discussed below…Referring still to FIGS. 4, 5 and 6, at epoch t4, tasks B1 and A3 complete. New tasks C1 and B82 are allocated to processors 12 and identifiers for these tasks 20 are added to the reorder list 28, not at the end but according to the sequential execution order so that they follow task B1 and move task A2 and other pre-existing tasks to the left, This movement is provided by determining the sequential execution number 52 of tasks C1 and B2 and comparing those numbers to the sequential execution number associated with the tasks currently in the reorder list 28 being part of the sequential order store 32 so that all tasks in the reorder list are in the order of their sequential execution numbers 52. Per decision block 62, task B1 is retired as being a completed task that is the oldest task in the reorder lists 28…As shown at epoch t5, task C1 may then complete. Because task C1 is now the oldest task in the reorder list 28, at decision block 62, it is removed from the reorder list 28 and its write token 40 is returned and its checkpoint data is released per process block 65. Because C1 is retired, its information is removed from the request list 42. Because C1 is complete, the dependent task D1 may now be re-allocated…” paragraphs 0055/0063/0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Capalija and Smiley with the teaching of Gupta because the teaching of Gupta would improve the system of Capalija and Smiley by providing a technique for reclaiming resources after execution to allow for other processes to use the resources.
As to claim 6, Capalija teaches the hardware retire circuit of claim 1, further comprising: a completed task queue configured to store a plurality of completed task events comprising the completed task event (Task Completion Status Queue figure 6/Section 4.4).
Gupta teaches wherein the processing logic is configured to determine whether the completed task queue identifier (Reorder List 28) and the completed task identifier match the input task identifier (Task A1/Tasks B1/ A3 /Task C1) of an input task by: comparing the input task identifier of the input task at the head of the input queue associated with the completed task queue identifier with the completed task identifier (oldest task), and wherein the processing logic is further configured to, in response to determining a match, pop the completed task event from the completed task queue (Process Block 64) (“…At epoch t2, and referring also to FIG. 6, it is assumed for this example that task A1 completes. Because task A1 is the oldest task in the reorder list 28, as determined by decision block 62, it is removed from the reorder list 28 (retired) as indicated by process block 64. As will be discussed in more detail below, there was no memory access by this task A1, so the remaining process blocks of FIG. 6 may be skipped and the program loops back to decision block 62. If A1 had accessed memory and had been enrolled in the request list 42, that entry in the request list 42 would be removed at process block 64 as will be discussed below…Referring still to FIGS. 4, 5 and 6, at epoch t4, tasks B1 and A3 complete. New tasks C1 and B82 are allocated to processors 12 and identifiers for these tasks 20 are added to the reorder list 28, not at the end but according to the sequential execution order so that they follow task B1 and move task A2 and other pre-existing tasks to the left, This movement is provided by determining the sequential execution number 52 of tasks C1 and B2 and comparing those numbers to the sequential execution number associated with the tasks currently in the reorder list 28 being part of the sequential order store 32 so that all tasks in the reorder list are in the order of their sequential execution numbers 52. Per decision block 62, task B1 is retired as being a completed task that is the oldest task in the reorder lists 28…As shown at epoch t5, task C1 may then complete. Because task C1 is now the oldest task in the reorder list 28, at decision block 62, it is removed from the reorder list 28 and its write token 40 is returned and its checkpoint data is released per process block 65. Because C1 is retired, its information is removed from the request list 42. Because C1 is complete, the dependent task D1 may now be re-allocated…” paragraphs 0055/0063/0071).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Capalija and Smiley with the teaching of Gupta because the teaching of Gupta would improve the system of Capalija and Smiley by providing a technique for reclaiming resources after execution to allow for other processes to use the resources.
As to claims 8 and 15, see the rejection of claim 1 above, except for a non-transitory, computer readable medium and a processor.
Capalija teaches a non-transitory, computer readable medium (figure 1, Memory) and a processor (figure 1, Control Processor).
As to clams 9 and 16, see the rejection of claim 2 above.
As to claim 13, see the rejection of claim 6 above.
Claims 3, 10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over “Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor” by Capalija et al. in view of U.S. Pub. No. 2016/0357608 A1 to Gupta et al. and further in view of U.S. Pub. No. 2014/0282579 A1 to Smiley et al. as applied to claims 1, 8 and 15 above, and further in view of W.O. No. 00/29943 to Holmberg et al.
As to claim 3, Capalija as modified by Gupta and Smiley teaches the hardware retire circuit of claim 1, however it is silent with reference to wherein the processing logic comprises a plurality of retire sub-circuits corresponding to one of the one or more input queues, wherein a retire sub- circuit of the plurality of retire sub-circuits comprises:
a local ready-to-retire table of a memory of the retire sub-circuit; and a processing logic circuit configured to manage the input queue associated with the retire sub-circuit.
Holmberg teaches wherein the processing logic comprises a plurality of retire sub-circuits corresponding to one of the one or more input queues (queues), wherein a retire sub- circuit of the plurality of retire sub-circuits comprises:
a local ready-to-retire table of a memory (Shared Memory 11) of the retire sub-circuit (“…When the execution of a job is finished, the job has to be retired or committed. Such a retirement is performed by a committer 18 according to the scheduled commit order. Thus, the committer 18 cooperates with the shared memory 11 and the job queue 16 for performing a retirement in an appropriate manner. The committer 18 and the commit order will be further discussed below. The execution of one job may result in changes in the data stored in the shared memory, but may also give rise to new jobs or messages. Such internally created jobs or messages may be intended for external units or for the processors of the present system. Jobs and messages intended for external units are brought to the input/ output (I/O) unit 15, for further transmission to the right receiver. Internal jobs may also be directed along this path or directly into the job queue or even directly to a certain processor…” page 8 lines 28-33, page 9 lines 1-6); and a processing logic circuit configured to manage the input queue associated with the retire sub-circuit (Scheduler 17) (“…Fig. 3d illustrates another solution of a job queue useful in the present invention. The job queue 16 is here divided into three sections 28, each one corresponding to one particular processor. When a new job is entered into the job queue, the scheduler 17 sets the commit tag 27 according to the global order of the job. However, the scheduler 17 determines the position in the job queue according to the first algorithm. If a job is scheduled to the first processor, the job is entered into the first section of the job queue, if a job is scheduled to the second processor, the job is entered into the second section of the job queue and if a job is scheduled to the third processor, the job is entered into the third section of the job queue. When a processor becomes available, the first job in the section 28 that corresponds to that particular processor is selected for execution. Upon retirement, the commit tag 27 is used for ensuring that the retirement is performed in the right global order. This allows parallel dependent/ coupled queues towards the processors…” page 14 lines 4-17).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Capalija, Gupta and Smiley with the teaching of Holmberg because the teaching of Holmberg would improve the system of Capalija, Gupta and Smiley by providing a technique for retiring computing jobs in a sequenced or correct order (Holmberg page 9 lines 23-25).
As to claims 10 and 17, see the rejection of claim 3 above.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over “Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor” by Capalija et al. in view of U.S. Pub. No. 2016/0357608 A1 to Gupta et al. and further in view of U.S. Pub. No. 2014/0282579 A1 to Smiley et al. and further in view of W.O. No. 00/29943 to Holmberg et al. as applied to claims 3, 10 and 17 above, and further in view of U.S. Pub. No. 2008/0209172 A1 to Raikin et al.
As to claim 5, Capalija as modified by Gupta, Smiley and Holmberg teaches the hardware retire circuit of claim 3, however it is silent with reference to an arbitrator circuit configured to selectively grant the plurality of retire sub-circuits access to output the task retirement event to a signal semaphore circuit shared by the plurality of retire sub-circuits.
Raikin teaches an arbitrator circuit (Apparatus 120/First Unit 130) configured to selectively grant the plurality of retire sub-circuits access to output the task retirement event to a signal semaphore circuit shared by the plurality of retire sub-circuits (“…The apparatus 120 may include a first unit 130 to enable the ROB 110 to selectively disable a lock. The first unit 130 may enable the ROB upon identifying a lock acquire operation (LAO) associated with a CS entry point…The apparatus 120 may detect that the lock acquire instruction predicted to be the beginning of a CS is reaching retirement. Upon detecting that the lock acquire instruction is ready for retirement, the apparatus 120 will determine whether the corresponding store instruction for releasing the lock has already been dispatched. If so, then the apparatus 120 will stall retirement of the lock acquire instruction until CS memory accesses are complete and all related transactional instructions are ready for retirement. The apparatus 120 will then perform a bulk retirement of CS instructions without retiring either the lock acquire store or the lock release store. Thus, it will be as if these two stores never occurred. If, however, the lock release store was not yet dispatched, then the lock acquire instruction will be retired normally. In one embodiment, a counter (e.g., register) can be added to control the number of micro-operations (uops) for which the lock acquire instruction will wait before retiring…” paragraphs 0012/0016).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claim invention to modify the system of Capalija, Gupta, Smiley and Holmberg with the teaching of Raikin because the teaching of Raikin would improve the system of Capalija, Gupta, Smiley and Holmberg by providing a locking system that allows for control access to computing resources.
As to claims 12 and 19, see the rejection of claim 5 above.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5, 6, 8-10, 12, 13, 15-17 and 19 have been considered but are moot because the new ground of rejection relies on additional reference not applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 4, 7, 11, 14, 18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for allowance
The following is an examiner’s statement of reasons for allowance:
The closest prior art of records, (“Microarchitecture of a Coarse-Grain Out-of-Order Superscalar Processor” by Capalija et al. and U.S. Pub. No. 2016/0357608 A1 to Gupta et al.), taken alone or in combination do not specifically disclose or suggest the claimed recitations (claims 4, 7, 11, 14, 18 and 20), when taken in the context of claims as a whole.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES E ANYA whose telephone number is (571)272-3757. The examiner can normally be reached Mon-Fir. 9-6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KEVIN YOUNG can be reached at 571-270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CHARLES E ANYA/Primary Examiner, Art Unit 2194