DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). See the rejection under 35 U.S.C. 112(a) below.
Claim Objections
Claims 1-18 are objected to because of the following informalities:
Claim 1 line 4 "the rows" should be "the rows of input bits" as antecedently recited.
Claim 1 line 5 and 7; claim 2 line 3 “the columns" should be "the columns of the weight bits" as antecedently recited.
Claim 5 line 2-3 "the number of AND gates" should be "a number of the AND gates" because there is lack of antecedent basis for “the number” and the limitation should also recite “the AND gates” as antecedently recited in line 2.
Claim 5 line 3 "the number of elements" should be "a number of the elements of the input vector" because there is lack of antecedent basis for “the number” and the limitation “elements” should be “the elements of the input vector” as antecedently recited in line 2.
Claim 12 line 2-3 "the OR gate" should be "the one OR gate" as antecedently recited.
Claim 12 line 5 recites "the number of AND gates" should be "a number of AND gates" because there is lack of antecedent basis for “the number”.
Claim 13 line 9 “the plurality of columns” should be “the respective columns” as antecedently recited..
Claim 18 line 2-3 "each of memory cells" should be "each of the memory cell units" as antecedently recited.
Dependent claims are also objected for inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f), is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
"a first accumulation operator" in claims 1 and 14. Figure 1 illustrates a first accumulation operator 170 and [0069] describes the operator 170 may be implemented as a dynamic logic circuit, where the dynamic logic circuit may be in the form of a register and may include at least one of a dynamic flip-flop or a TSPC. However, merely describing the dynamic logic circuit in the form of a register fails to provide sufficient structure to perform the entire claimed functions, such as shifting and adding. In other words, a register, such as dynamic flip flop may be sufficient to perform shifting, but does not sufficiently perform adding operation.
“a second accumulation operator” in claim 8. Figure 5 illustrates a second accumulation operator 570. [0100] describes second accumulation operator 570 implementing with the dynamic logic circuit, as [0069] describes the dynamic logic circuit. However, as explained above, such described structure in [0069] is not sufficient to perform the entire claimed functions.
“a row enabling block” in claim 9. Figure 5 illustrates a row enabling block 580 includes AND gates and an OR gate to generate row enabling signals.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 1-12 and 14-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 8 and 14 recite “a first accumulation operator” and “a second accumulation operator”, which invoke 112(f) interpretation. However, the specification fails to provide sufficient structures to perform the entire claimed function as required under 112(f) interpretation. Figure 5 illustrates a first accumulation operator and a second accumulation operator and [0069] describes the first accumulation operator may be implemented as a dynamic logic circuit, where the dynamic logic circuit may be in the form of a register and may include at least one of a dynamic flip-flop or a TSPC. However, merely describing the dynamic logic circuit in the form of a register fails to provide sufficient structure to perform the entire claimed functions, such as shifting and adding. In other words, a register, such as dynamic flip flop may be sufficient to perform shifting, but does not sufficiently perform adding operation as required for one of the claimed functions. Accordingly, the specification fails to provide sufficient structure to perform the entire claimed functions when invoked under 112(f).
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-18 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 2-3, 10 recite "the memory cell unit". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets such limitation as "the memory cell".
Claim 13 line 2-4 recites "an IMC array comprising an IMC configured to share … and control". It is unclear what components (e.g., an IMC array or an IMC) perform the functions of sharing and controlling. For examination purposes, Examiner interprets the functions of sharing and controlling are performed by the IMC.
Claim 13 line 9 "each of the plurality of memory cells". There is lack of antecedent basis for “the plurality of memory cells”. For examination purposes, Examiner interprets as “each of the memory cell units".
Claim 14 line 2, 7; claim 17 line 2-3 recite "the memory cells". There is lack of antecedent basis for such limitation. For examination purposes, Examiner interprets as "the memory cell units" as antecedently recited.
Claim 14 line 7 recites "the weight bits being sequentially loaded to each of the memory cells according to the sub-clock signals". Such limitation renders the claim unclear and indefinite because claim 13 line 4-7 antecedently recites the weight bits are sequentially loaded from a memory cell array to perform matrix product operation according to the sub-clock signals, but claim 14 line 7 recites the weight bits are being sequentially loaded to each of the memory cells. Specification [0095, 0113] figure 8 describes the weight bits being sequentially loaded or read from the memory cell array. For examination purposes, Examiner interprets such limitation as “the weight bits being sequentially loaded from each of the memory cells according to the sub-clock signals”.
Claim 20 line 3 recites "the multi-bit matrix product operation". There is lack of antecedent basis for such limitation. Examiner interprets as "a multi-bit matrix product operation".
Claims 1, 8 and 14 recite limitations “a first accumulation operator" and "a second accumulation operator”, which invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. See explanation above in 112(a). Therefore, the claim is indefinite and is rejected under 35 U.S.C. 112(b).
Applicant may:
(a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f);
(b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)).
If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either:
(a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or
(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Badaroglu - US 20230031841.
Regarding claim 1, Badaroglu teaches an in-memory computing (IMC) unit (Badaroglu figure 8A [0021] illustrates a CIM circuitry [i.e., IMC unit]) comprising:
a memory cell configured to store a weight vector as columns of weight bits (Badaroglu figure 8A illustrates memory cells 502 [i.e., a memory cell], wherein figure 6 [0063] describes the memory cells 502 store weight bits w a plurality of columns [i.e., a weight vector as columns of weight bits), the memory cell unit further configured to apply an input vector to the weight vector, the input vector comprising rows of input bits (Badaroglu figure 6, the memory cells 502 [i.e., the memory cell unit] apply the activation signals [i.e., an input vector] to the weight vector, where the activation signals having rows of input bits), wherein the IMC unit is configured to apply the rows sequentially, as units of rows, to the columns (Badaroglu [0066,0078] activation circuitry 590 provides a first set of 599 of activation inputs to the columns of memory cells during first activation cycle, then the same operation is performed for other set of activation inputs during subsequent activation cycles, and repeat until the last cycle. Thus, the rows of input vector is sequentially applied to the columns);
a timing generator configured to, based on an external clock signal, generate sub-clock signals for selecting the columns as units of columns (Badaroglu figure 8A illustrates a frequency multiplier 802 [i.e., a timing generator] that generate a local clock having a frequency that is greater than the DCIM clock [i.e., an external clock signal], and as illustrated in figure 7, there is at least 8 local clock cycles generated [i.e., sub-clock signal]. [0079] describes during each cycle of the local clock, a column of memory cells is selected to perform operation [i.e., for selecting the columns as units of columns]. Alternative, the limitation “for selecting the columns as units of columns” is merely recited as an intended use/result of generating the sub-clock signals. Thus, such limitation is not given patentable weight);
a multiplying and accumulator (MAC) logic circuit configured to perform a single-bit matrix product operation between the weight bits and the input bits (Badaroglu Figure 4 [0061] illustrates implementation of each memory cell 502 having circuit, such as transistors 410 and 412 to implement NAND gate operation to perform bitwise multiplication. Thus, a combination of NAND gates and the bit column adder tree 650 corresponding to a multiply and accumulator logic circuit that configured to perform bitwise multiplication of a matrix of bits [i.e., a single bit matrix product operation] between the weight bits and the activation bits), the weight bits being sequentially loaded to the MAC logic circuit from the memory cell unit according to the sub-clock signals (Badaroglu figure 4 [0059] the weight bits stored in 424 of memory cells 502, which are loaded to the NAND gate [0061] according to the at least eight local clock cycles [i.e., the sub-clock signals]. Badaroglu [0079] describes the computations of a portion of memory cells are performed during each cycle until 8 cycles of the local clock is completed, thus, bit-wise multiplication is sequentially performed, thereby weight bits are sequentially loaded to the NAND gates for bit-wise multiplication); and
a first accumulation operator configured to output multi-bit matrix product operation results respectively corresponding to the input bits by shifting and adding operation results of the MAC logic circuit according to the sub-clock signals (Badaroglu figure 6 illustrates a combination of column accumulator 652 and weight-shift adder tree 512 [i.e., a first accumulation operator] adds multiple bits across the columns and generate multiple results of multi-bit across multiple activation cycles [0076]. [0064] describes the weight-shift adder tree 512 includes bit shift and add circuit to facilitate the performance of a bit shift and addition operation [i.e., by shifting and adding operation] of the operation results of the combination of NAND gates of memory cells and bit-column adder tree [i.e., the MAC logic circuit], which operates according to the at least 8 local clock cycles [i.e., the sub-clock signals]. Also see [0063] describes each word lines store a multi-bit weight, such as 8 bit weight, thus the operation between the input bits and weight bits generate multi-bit matrix product operation results corresponding to the applied input bits).
Regarding claim 7, Badaroglu teaches the IMC unit of claim 1, wherein the first accumulation operator is implemented as a dynamic logic circuit configured to operate according to the sub-clock signals (Badaroglu figure 6 illustrates the combination of column accumulator 652 and weight-shift adder tree 512 [i.e., the first accumulation operator], wherein [0080] the output of the column accumulator circuit 652 and the output of the weight-shift adder tree circuit 512 are provided after the eight local clock cycles. Thus, such circuits 652 and 512 are implemented as logic circuit that that operate at a different frequency [0076], where half latch circuits 608 operates at high frequency than the circuit 512 [i.e., dynamic logic circuit]), and the dynamic logic circuit has a register form and comprises at least one of a dynamic flip-flop or a true single phase clock (TSPC) (Badaroglu figure 6 illustrates the combination of circuits 652 and 512 has latch circuits 608 [i.e., a register form] that operates on a local clock as illustrated in figure 8A [i.e., a true single phase clock]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Badaroglu in view of Chen – US 20220392524
Regarding claim 5, Badaroglu teaches the IMC unit of claim 1, including the MAC logic circuit comprises: NAND gates respectively corresponding to elements of the input vector (Badaroglu figures 4 and 6 illustrate the combination of NAND gates and bit-column adder tree [i.e., the MAC logic circuit] comprises NAND gate in each of memory cell 502, thus the NAND gates corresponding to elements of the activation input vector as illustrated in figure 6), wherein the number of NAND gates is greater than or equal to the number of elements (Badaroglu figure 6 illustrates each memory cell 502 includes a NAND gate corresponding to a number of elements of input vectors. For example, figures 4 and 6 illustrate at least 4 memory cells 502 having 4 NAND gates, which is equal to 4 elements in 4 rows of input vector); and one shared adder configured to perform an addition operation on outputs of the NAND gates (Badaroglu figure 6 illustrates bit column adder tree 604 that perform an addition operation on outputs of the NAND gates from memory cells 502). Badaroglu does not teach AND gates to perform multiplication operation. However, Chen teaches AND gates to perform multiplication operation (Chen [0004] describes compute in memory array includes a binary multiplication circuit configured to multiply weight data by an activation input, wherein a multiplication of two one bit binary data value in a CIM bit cell may be implemented as a logical AND based operation (e.g., AND or NAND). Also see figure 8 illustrates similar structure in Badaroglu figure 6).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to substitute to the NAND gate implementation of each memory cells 502 of Badaroglu as illustrated in figure 6 with an AND gate to perform bit-wise multiplication for single bit matrix product operation between weight bits and input bits as described in [0004] of Chen. The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art, which is bit-wise multiplication, as Badaroglu describes [0061] implementation of a NAND gate for bit wise multiplication and Chen describes that bit wise multiplication can be implemented using AND gate or NAND gate. See MPEP 2141(III) (B) Simple substitution of one known element for another to obtain predictable results.
Regarding claim 6, the combined system of Badaroglu in view of Chen teaches the IMC unit of claim 5, wherein the MAC logic circuit is configured to perform the single-bit matrix product operation by performing multiplication operations between each of the weight bits and each of the input bits by using the AND gates and performing an addition operation on results of the multiplication operations by using the one shared adder (as modified, Badaroglu describes [0068] bit-wise multiplication [i.e., the single-bit matrix product operation], wherein the single bit multiplication is performed using AND operation by each of the weight bits and each of the activation bits via AND gate, and the adder tree 604 [i.e., the one shared adder] performs addition operation on results of the AND gates).
Claims 13-14, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Badaroglu
Regarding claim 13, Badaroglu teaches an in-memory computing (IMC) macro (Badaroglu figure 8A illustrates a CIM circuitry [i.e., IMC macro]) comprising:
an IMC array (Badaroglu figure 8A illustrates a combination of circuits 502, 650, 652, 512, 516, and 802 [i.e., an IMC array], where figure 6 illustrates those circuits having an array of components) comprising an IMC (Badaroglu figure 6 a combination of circuits 802, 502, 650, 652, and 512 [i.e., an IMC]) configured to share sub-clock signals that are generated based on an external clock signal and control respective columns having a crossbar structure (Badaroglu figure 6 illustrates at least components 502, 650, and 652 shared the 8 local clock cycles [i.e., sub-clock signals] generated based on DCIM clock [i.e., an external clock signal] and [0079] control columns of memory cells 502 [i.e., respective columns] having a crossbar structure as illustrated in figure 6), wherein the IMC is further configured to perform a matrix product operation between weight bits by units of columns thereof and input bits of an input vector (Badaroglu figures 4 and 6 illustrates the memory cells 502 perform a matrix product operation between weight bits and input bits of the activation input a [i.e., an input vector] by applying input bits to the columns of weight bits), the weight bits being sequentially loaded, according to the sub-clock signals, from a memory cell array comprising memory cell units (Badaroglu figure 4 [0059] the weight bits stored in 424 of memory cells 502 [i.e., memory cell units] of CIM array 501 [i.e., a memory cell array], which are loaded to the NAND gate [0061] according to the at least eight local clock cycles [i.e., the sub-clock signals]. Badaroglu [0079] describes the computations of a portion of memory cells are performed during each cycle until 8 cycles of the local clock is completed, thus, bit-wise multiplication is sequentially performed, thereby weight bits are sequentially loaded to the NAND gates for bit-wise multiplication); Badaroglu does not teach an enabling circuit configured to generate enabling signals for enabling the weight bits included in each of the plurality of columns, for each of the plurality of memory cells. However, another embodiment of Badaroglu an enabling circuit configured to generate enabling signals for enabling the weight bits included in each of the plurality of columns, for each of the plurality of memory cells (Badaroglu figure 8B teaches a clock gating circuitry [i.e., an enabling circuit] that configured to generate signals [i.e., enabling signals] for enabling the weights in each of the columns of memory cells. [0085] describes during a first cycle, the clock gate circuitry generate signals to deactivate signals for columns 4-7. [0086] further describes the clocking gate technique may be used to deactivate clock signals to other circuits that are unused. Thus, when columns are activated, such as columns 1-4, it enables the weight bits to be loaded for computation for that columns).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to modify the structure of figure 8A in Badaroglu to include a clock gating circuitry as illustrated in figure 8B to perform clock gating technique to deactivate unused columns. This modification would have been obvious because both embodiments are directed to in memory computing architecture. Furthermore, as recognized by Badaroglu [0085-0086], deactivating unused columns would reduce power consumption for the system.
Regarding claim 14, the combined system of Badaroglu teaches the IMC macro of claim 13, wherein the IMC comprises: the memory cell array, within which the memory cells are arranged in units of rows (Badaroglu figure 6 illustrates the CIM array 501 [i.e., the memory cel array] having memory cells 502 arranged in rows [i.e., units of rows]); a timing generator configured to generate the sub-clock signals based on the external clock signal (Badaroglu figure 8A illustrates a frequency multiplier 802 [i.e., a timing generator] that generate a local clock having a frequency that is greater than the DCIM clock [i.e., an external clock signal], and as illustrated in figure 7, there is at least 8 local clock cycles generated [i.e., sub-clock signal] within 1 clock cycle of DCIM) a multiplying and accumulator (MAC) logic array configured to perform a matrix product operation between the weight bits and the input bits through pipelining (Badaroglu figures 4 and 6 illustrates NAND gate implementation in each memory cell 502 and also illustrates bit-column adder tree 604, thus, a combination of NAND gates implementation and bit-column adder tree corresponds to a MAC logic array, that configured to perform bitwise multiplication between weight bits and input bits according to the number of clock cycles [i.e., performing matrix product operation through pipelining]), the weight bits being sequentially loaded to each of the memory cells according to the sub-clock signals (Badaroglu figure 4 [0059] the weight bits stored in 424 of memory cells 502 of CIM array 501, which are loaded to the NAND gate [0061] according to the at least eight local clock cycles [i.e., the sub-clock signals]. Badaroglu [0079] describes the computations of a portion of memory cells are performed during each cycle until 8 cycles of the local clock is completed, thus, bit-wise multiplication is sequentially performed, thereby weight bits are sequentially loaded to the NAND gates for bit-wise multiplication); and a first accumulation operator configured to output multi-bit matrix product operation results corresponding to the input bits by shifting and adding operation results of the MAC logic array according to the sub-clock signals (Badaroglu figure 6 illustrates a combination of column accumulator 652 and weight-shift adder tree 512 [i.e., a first accumulation operator] adds multiple bits across the columns and generate multiple results of multi-bit across multiple activation cycles [0076]. [0064] describes the weight-shift adder tree 512 includes bit shift and add circuit to facilitate the performance of a bit shift and addition operation [i.e., by shifting and adding operation] of the operation results of the combination of NAND gates of memory cells and bit-column adder tree [i.e., the MAC logic circuit], which operates according to the at least 8 local clock cycles [i.e., the sub-clock signals]. Also see [0063] describes each word lines store a multi-bit weight, such as 8 bit weight, thus the operation between the input bits and weight bits generate multi-bit matrix product operation results corresponding to the applied input bits).
Regarding claim 16, the combined system of Badaroglu teaches the IMC macro of claim 14, wherein the timing generator is driven according to a control signal for controlling generation of the sub-clock signals for each of the columns (Badaroglu [0083] describes the frequency multiplier 802 [i.e., the timing generator] refers to a circuit that receive a first clock having a first frequency and generate a second clock having a second different frequency, where the second frequency is a multiple of the first frequency. Thus, the frequency multiplier 802 is driven by the multiplication factor [i.e., a control signal] for controlling the generation of the multiple of the first frequency, such as 8 local clock cycles [i.e., the sub-clock signals] for each of the columns in the memory array 501).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over the combined system of Badaroglu as applied to claim 14 above, and further in view of Chen.
Regarding claim 17, the combined system of Badaroglu the IMC macro of claim 14, wherein the MAC logic array comprises MAC logic circuits respectively corresponding to the memory cells (Badaroglu figures 4 and 6 illustrate the combination of NAND gates and bit-column adder trees in each column corresponds to MAC logic circuits corresponding to the memory cells]), and each of the MAC logic circuits (Badaroglu figures 4 and 6, each column of NAND gates of memory cells 502 and the corresponding bit column adder tree [i.e., each of the MAC logic circuits]) comprises: NAND gates respectively corresponding to elements of the input vector; and one shared adder configured to perform an addition operation on outputs of the AND gates (Badaroglu figures 4 and 6 illustrate memory cells 502 of a column include NAND gates corresponding to a number of elements of input vectors. For example, figures 4 and 6 illustrate at least 4 memory cells 502 having 4 NAND gates, which is equal to 4 elements in 4 rows of input vector); and one shared adder configured to perform an addition operation on outputs of the NAND gates (Badaroglu figure 6 illustrates bit column adder tree 604 that perform an addition operation on outputs of the NAND gates from memory cells 502). Badaroglu does not teach AND gates to perform multiplication operation. However, Chen teaches AND gates to perform multiplication operation (Chen [0004] describes compute in memory array includes a binary multiplication circuit configured to multiply weight data by an activation input, wherein a multiplication of two one bit binary data value in a CIM bit cell may be implemented as a logical AND based operation (e.g., AND or NAND). Also see figure 8 illustrates similar structure in Badaroglu figure 6).
It would have been obvious for one of ordinary skills in the art before the effective filing date of the claimed invention to substitute to the NAND gate implementation of each memory cells 502 of Badaroglu as illustrated in figure 6 with an AND gate to perform bit-wise multiplication for single bit matrix product operation between weight bits and input bits as described in [0004] of Chen. The claim would have been obvious because the substitution of one known element for another would have yielded predictable results to one of ordinary skill in the art, which is bit-wise multiplication, as Badaroglu describes [0061] implementation of a NAND gate for bit wise multiplication and Chen describes that bit wise multiplication can be implemented using AND gate or NAND gate. See MPEP 2141(III) (B) Simple substitution of one known element for another to obtain predictable results.
Allowable Subject Matter
Claims 2-4, 8-12, 15, 18, and 20 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) and 112(a), and claim objections as set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 19 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2, 8, 9, 15, 18, and 19, the prior art of record does not teach or suggest a combination of limitations, such as the timing generator is configured to sequentially generate the sub-clock signals, at least some of which have different phases with respect to each other, for selecting the columns, based on an external clock signal that is generated outside of the IMC unit as required in claim 2; or a second accumulation operator configured to shift the multi-bit matrix product operation results by one bit and add the multi-bit matrix product operation results according to the sub- clock signals to output a multi-bit matrix product operation result corresponding to the input vector as required in claim 8; or a particular structure of the row enabling block 580 in figure 5 as required in claim 9 under 112(f) interpretation; or the timing generator is configured to generate overlapping clock signals obtained by overlapping sub-clock signals having different phases for each of the respective columns, and wherein the MAC logic array is pipelined by the overlapping clock signals to perform a single-bit matrix product operation as required in claim 15; or the enabling circuit comprises a row enabling block corresponding to each of memory cells, and wherein the row enabling block comprises: AND gates respectively corresponding to elements of the input vector, and one OR gate configured to perform an OR operation on outputs of the AND gates as required in claim 18; or the steps of shifting results of the single-bit matrix product operation by one bit and adding the single- bit matrix product operation results according to the sub-clock signals to output multi-bit matrix product operation results respectively corresponding to the input bits; and shifting the multi-bit matrix product operation results by one bit and adding the multi-bit matrix product operation results according to the sub-clock signals to output a multi-bit matrix product operation result corresponding to the input vector as required in claim 19.
Badaroglu – US 20230031841 teaches a system for performing multi-bit matrix operation using in memory computing structure as illustrated in figures 5A, 6, and figure 8, wherein the system includes a memory cell array having memory cells configured to perform bitwise multiplication using NAND gate, wherein the memory cell includes cell to store weight bit and NAND gate implementation to perform multiplication between weight bit and activation bit. Figure 8A illustrates a frequency multiplier that generate 8 local clock cycles for sequentially loading data to perform multiplication and addition, and figure 6 illustrates shared adder tree configured to add output of NAND gates of a column and also include shift adder tree to perform shifting and operation. However, Badaroglu does not teach or suggest the frequency multiplier to sequentially generate sub clock signals, which at least some of which have different phases with respect to each other as required in claim 2; or a second accumulation operator configured to shift the multi-bit matrix product operation results by one bit and add the multi-bit matrix product operation results according to the sub-clock signals as required in claim 8; or structure of the row enabling block as described in figure 5 as required in claims 9; or time generator configured to generate overlapping clock signals having different phases for each of the respective columns and pipelining the MAC logic array to perform a single bit matrix product operation as required in claim 15; or the structure implementation of the enabling circuit as required in claim 18; or the steps of shifting results of the single-bit matrix product operation by one bit and adding the single- bit matrix product operation results according to the sub-clock signals to output multi-bit matrix product operation results respectively corresponding to the input bits; and shifting the multi-bit matrix product operation results by one bit and adding the multi-bit matrix product operation results according to the sub-clock signals to output a multi-bit matrix product operation result corresponding to the input vector as required in claim 19.
Chen – US 20220392524 teaches digital compute in memory (DCIM) for performing multiplication and accumulation operation as illustrated in figures 7 and 8, wherein the DCIM includes memory cell array, where each memory cell is implemented to include a cell for storing and a logic gate for computation, such as AND-based logic gate [0004]. However, Chen does not teach or suggest the limitations as described above for claims 2, 8, 9, 15, 18, and 19.
Zheng – US 20220129519 teaches a hybrid compute in memory structure that configured to switch between analog CIM mode and digital CIM mode as illustrated in figures 5A and 5B, where in analog mode, the activation inputs and weights are multiplied within the memory cell in analog domain, and when in digital mode, the weight bits and activation bits are loaded into AND gate to perform operation as illustrated in figure 5B. However, Zheng does not teach or suggest the limitations as described above for claims 2, 8, 9, 15, 18, and 19.
Chou – US 20220351032 teaches a memory for artificial neural network acceleration that using a crossbar array of memristors to perform multiplication based on Ohms’ law, where activation inputs are applied via the rows to multiplied with the weight stored in the memory cells as conductance value, where activation inputs are input to AND gates corresponding to the rows to determine whether such activation input is enabled. However, Chou does not teach or suggest the limitations as described above for claims 2, 8, 9, 15, 18, and 19.
Studer – US 20210019147 teaches a digital processing in memory architecture for performing matrix multiplication using an array of memory cells having AND gate to perform multiplication operation as illustrated in figure 6A, where the weight bit are loaded into the AND gate based on a clock gate signal 56 to enable the memory bits. However, Studer does not teach or suggest the limitations as described above for claims 2, 8, 9, 15, 18, and 19.
Lee – US 20220244916 teaches a digital CIM architecture to perform matrix multiplication using the CIM memory array 110 as illustrated in figure 1, which includes a plurality of memory cells having multiplier implemented as an AND gate, as illustrated in figure 5, to perform multiplication and a shared adder tree to perform addition operation. However, Lee does not teach or suggest the limitations as described above for claims 2, 8, 9, 15, 18, and 19.
Therefore, the prior art of records does not teach or suggest the combination of limitations as required in claims 2, 8-9, 15, and 18-19. Accordingly, Claims 2-4, 8-12, 15, 18, and 20 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) and 112(a), and claim objections as set forth in this Office action and to include all of the limitations of the base claim and any intervening claims and claim 19 is allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUY DUONG whose telephone number is (571)272-2764. The examiner can normally be reached Mon-Friday 7:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
Prosecution Insights