DETAILED ACTION
1. This communication is in response to the amendments filed on April 1, 2026 for Application No. 17/972,051 in which Claims 1-13 are presented for examination.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
3. The amendments filed on April 1, 2026 have been considered. No claims have been amended. Thus, Claims 1-13 are pending and presented for examination.
4. Applicant's arguments filed April 1, 2026 with respect to the 35 U.S.C. 102 rejection have been fully considered but they are not persuasive.
Applicant’s Arguments on Pgs. 10-11 of Arguments/Remarks state:
“The Office Action, p. 6, relies on paragraph [0102] of Arthur as allegedly teaching the feature "an output unit configured to receive a signal output from the input unit to perform up- counting and generate an output signal while down-counting is performed" recited in claim 1. paragraph [0102] and related FIG. 7A of Arthur are reproduced below.
[…]
Nowhere does Arthur describe that the firing and emission of a spike via the pulse module 64 (i.e., the alleged 'generate an output signal', (to which Applicant does not concede)) via the pulse module 64 is "while down-counting is performed" as recited in claim 1.
In contrast, Arthur describes that "[w]hen the neuron receives an external signal comprising a spike from an excitatory neuron, the state counter 62 is incremented by a small integer (typically set to 1)" and "[i]f the state counter exceeds a threshold as determined by a comparator 63 [(i.e., based on being incremented, as noted by the Applicant)], then the neuron fires and emits a spike via a pulse module 64." Arthur, [0102].
At best, Arthur is limited to firing and emitting a spike via the pulse module 64 for cases in which the state counter 62 is incremented, not while the state counter 62 is being decremented. That is, for cases where the state counter 62 is being decremented and the count is less than the threshold, the comparator 63 would not trigger the pulse module 64 to fire and emit a spike.
Dependent claims 2-3 are patentable for at least the same reasons as the claims from which they depend and for the features further recited therein.
Thus, it is respectfully submitted that amended independent claim 1, including claims depending therefrom, define over Arthur.
Accordingly, the Applicant respectfully requests reconsideration, withdrawal of the rejection under 35 U.S.C. § 102(a)(1) and allowance of the instant claims.”
Examiner respectfully disagrees. Regarding the instant limitation “an output unit configured to receive a signal output from the input unit to perform up-counting and generate an output signal while down-counting is performed”, Arthur Par. [0102] teaches that when the neuron receives an external signal comprising a spike, the state counter is incremented (up-counting is performed when a signal is received) and further when the neuron receives an external signal comprising a spike from an inhibitory neuron, the state counter is decremented (down-counting is performed). Further, once the counter exceeds a threshold, then the neuron would correspondingly fire and emit a spike. Regarding Applicant’s allegation that the Arthur reference does not explicitly disclose the “[…] generate an output signal while down-counting is performed”, Examiner points to Applicant’s specification Par. [0027] (also cited by Applicant on Pg. 8 of Arguments/Remarks) which states “The counter performs up-counting in response to a signal transmitted by the comparator and then performs down-counting. The output generator receives a signal output from the counter and generates an output signal, and then outputs the generated output signal” – thus, it is not clear how the output signal is generated while down-counting is performed, if Applicant’s specification similarly supports a sequential/procedural interpretation of the transmission of signals. This is again similarly pointed out by instant claim 3 which states that the counter of the output unit receives a signal output from the comparator to “perform the up-counting and then perform the down-counting” – this similarly indicates that the operations performed by the output unit are sequential, not concurrent. Nonetheless, Arthur Par. [0158] states “For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved” – therefore, regarding Arthur Figure 7A, the steps of decrementing the counter and firing the spike/pulse (generating an output signal) may be performed concurrently. Further, Arthur Par. [0135] states “The state counter 62 continues the operations of incrementing when the electronic neuron 60 receives excitatory signals and decrementing when the neuron receives inhibitory signals. If at any time, the state counter 62 reaches a threshold value (e.g., about 255), the electronic neuron 60 fires and emits a spike signal. When the electronic neuron 90 spikes, the capacitor C is quickly discharged.” – thus, in scenarios where the counter reaches the threshold value, the increment/decrement operations may be performed simultaneously alongside the firing of the neuron.
If there is an explicit sequence/order of operations that are to be followed per the instant claims, Applicant should consider amending the claim language to better depict the concurrency/parallel operations, such that it is clear which operations are performed in which order. It must also be noted that the claims do not further define or characterize the “up-counting” and “down-counting” limitations – the claims merely state that “up-counting” and “down-counting” are performed without significantly more. The Independent claims are very broad/generic and simply lists these steps without stating what characterizes an event that comprises “up-counting” or “down-counting” to be respectively performed and hence it is not clear how this influences the state/configuration of the neuron circuit itself – the claims are disjoint in nature.
This applies to Independent Claim 1 and its respective dependents. Along with Independent Claim 7 (and its respective dependents) which recites substantially the same limitations in the form of a neuromorphic device.
Thus, the 35 U.S.C. 102 rejection is maintained.
5. Applicant's arguments filed April 1, 2026 with respect to the 35 U.S.C. 103 rejection have been fully considered but they are not persuasive.
Applicant’s Arguments on Pgs. 13-16 of Arguments/Remarks state:
“Independent claim 13
The cited references, alone or in combination, fail to teach or suggest at least the italicized features of claim 13.
[…]
First, regarding the features "operations of the integrator and the discharger are controlled by a first clock signal" and "operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal" recited in independent claim 13, the Office Action, p. 23, cites the features of a first comparator 310, a first counter 410, a second comparator 320, and a second counter 420 described with reference to FIGS. 2 and 8 (reproduced below) of Chun.
[…]
Particularly, the Office Action alleges that Chun's description of "[t]he first counter 410 counts the first comparison signal VC1 received from the first comparator 310 by using the first clock signal CLK1 (see FIG. 8) to output the first count value CV1," Chun, col. 9 lines 1-4, corresponds to "operations of the integrator and the discharger are controlled by a first clock signal" recited in claim 13. The Office Action also alleges that Chun's description of "[t]he second counter 420 counts the second comparison signal VC2 received from the second comparator 320 by using the second clock signal CLK2 (see FIG. 8) to output the second count value CV2," Chun, col. 9, 11. 5-8, corresponds to "operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal" recited in claim 13.
Applicant respectively disagrees.
Chun describes "[t]he switching circuit 100 may select one of an input voltage Vin for a charging operation and a reference voltage Vreffor a discharging operation," Chun, col. 7, 11. 5-7, "the integrating circuit 200 may remove an operation reset of the integrating circuit 200 and a direct current (DC) offset voltage of an input side of the integrating circuit 200 in response to a second control signal SC2," id., col., 7, 11. 20-25. Chun further describes "[t]he dual comparison circuit 300 outputs a first comparison signal VC1 by comparing the first voltage Vx from the integrating circuit 200 with afirst reference voltage Vrefl (see FIG. 2), and may output a second comparison signal VC2 by comparing a second reference voltage Vref2 (see FIG. 2) higher than the first reference voltage Vrefl with the first voltage Vx." Id., col. 7, 11. 26-32.
Even if the second comparator 320 and the second counter 420 of Chun could be applied to the "comparator" and the "counter" recited in claim 13, (to which Applicant does not concede), nowhere does Chun describe that operations of the second comparator 320 and the second counter 420 are controlled by two distinct clock signals. At best, Chun describes providing the second clock signal CLK2 to the second counter 420. None of the other voltage signals or voltages (i.e., input voltage Vin for a charging operation, reference voltage Vref for a discharging operation, first voltage Vx, first reference voltage Vrefl, second reference voltage Vref2), second control signal SC2, and comparison signals (i.e., first comparison signal VC1, second comparison signal VC2) in Chun constitute a clock signal.
Further, as to the first clock signal CLK1 (alleged "first clock signal") provided to the first counter 410 in Chun, nowhere does Chun describe that operations of the second comparator 320 and the second counter 420 are also controlled by the first clock signal CLK1.
That is, Chun fails to teach or suggest the feature "operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal," as recited in claim 13. (emphasis added). Further the Office Action fails to show a "output generator" that is also "controlled by the first clock signal and [the] second clock signal" as recited in claim 13."
further recited in claim 13.”
Examiner respectfully disagrees. Regarding the limitation “wherein operations of the integrator and the discharger are controlled by a first clock signal”, Examiner cited to Chun Col. 9 lines 1-4 which states that the first counter counts the first comparison signal received from the first comparator by using the first clock signal to output the first counter value. The first comparator is configured to output the first comparison signal by comparing the first voltage from the integrating circuit and the comparison circuit itself also comprises a fast discharge circuit configured to discharge the circuit after comparison (see Chun claim 14). Therefore, considering the broadest reasonable interpretation of the instant claim language, Chun teaches that the operations of the integrator and the discharger are controlled by a first clock signal, since the operations of the first comparator (involving operations of both the integrator/integrating circuit and discharger/discharge circuit) are controlled by a first clock signal.
Furthermore, regarding the limitation “wherein operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal”, Examiner cited to Chun Col. 9 lines 5-8 which states that the second counter counts the second comparison signal received from the second comparator by using the second clock signal to output the second count value. Hence, considering the broadest reasonable interpretation of the instant claim language, Chun teaches that the operations of the comparator, the counter, and the output generator are controlled by a second clock signal. Chun Figures 8 and 9 similarly depict how the operations of the comparator, counter, and output generator are controlled by both a first clock signal (CLK1) and a second clock signal (CLK2).
Applicant’s Arguments on Pgs. 16-17 of Arguments/Remarks state:
“Second, as Chun fails to teach or suggest the "second clock signal" by which the "operations of the comparator, the counter, and the output generator are controlled," Chun cannot teach or suggest the feature "generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal.
The Office Action, pp. 25-26, relies on paragraph [0067] and related FIG. 10 of Baker for curing the deficiencies of Chun as to the feature "generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal" recited in claim 13, stating that "the counter performs down-counting in response to the signals received." Paragraph [0067] and FIG. 10 of Baker are reproduced below.
[…]
Baker, at most, generally describes that "the counter 90 may increment and/or decrement a count once per clock cycle [CLOCK] (or other appropriate interval) based on whether the bit-stream is logic high or logic low." Baker, [0067]. Baker, however, fails to teach or suggest a second clock signal by which operations of the comparator 96 and the counter 90 are also controlled. Indeed, Baker only describes a single clock "CLOCK" provided to both the comparator 96 and the counter 90.
Accordingly, as Baker fails to teach or suggest the "second clock signal" by which the "operations of the comparator, the counter, and the output generator are controlled," recited in claim 13, Baker also fails to teach or suggest the feature "generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal" as further recited in claim 13.
Applicant believes this reply places the application in condition for allowance.
Accordingly, withdrawal of the rejections under 35 U.S.C. § 103(a) is respectfully requested.”
Examiner respectfully disagrees. Regarding the limitation “generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal, in a case in which the integrator is disconnected from the comparator when the state of the first clock signal is switched to the high state”, Examiner cited to Baker Par. [0067] which states that the counter may count the number of clock cycles that are either in the discharging state or the charging state by monitoring the signal path – the signal path may transition back and forth between high and low logic with the output of the comparator and the counter may increment/decrement a count once per clock cycle based on the stream being logic high or logic low. Hence, Baker teaches the counter generating an output signal through the output generator while performing down-counting in response to the second clock signal […]. Contrary to Applicant’s arguments, Baker seemingly discloses the use of two different clock signals as per Figure 10, as label 96 depicts a clock and counter label 96 also depicts another clock signal which is used for controlling counter operations – also better described by Par. [0062-0067].
Thus, the 35 U.S.C. 103 rejection is maintained.
Claim Rejections - 35 USC § 102
6. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arthur et al. (hereinafter Arthur) (US PG-PUB 20120150781).
Regarding Claim 1, Arthur teaches a neuron circuit that processes a signal transmitted through a synaptic array (Arthur, Par. [0139], “A low-power event-driven (LPED) electronic neuron circuit is a hardware realization of the LL-IF neuron described hereinabove.”, thus, a neuron circuit that processes a signal transmitted through a synaptic array is disclosed. Figure 1 better depicts the synaptronic system having a crossbar array interconnecting integrate and fire electronic neurons), the neuron circuit comprising:
an input unit configured to receive and integrate signals output from the synaptic array as input signals and discharge the integrated input signals until an amount of the integrated signals is less than or equal to a preset threshold (Arthur, Par. [0102], “FIG. 7A shows a diagram of an example implementation of a mixed-mode digital-analog, integrate and fire electronic neuron 60, according to the invention. The mixed-mode neuron maintains its membrane potential (state) in a digital state counter 62. When the neuron receives an external signal comprising a spike from an excitatory neuron, the state counter 62 is incremented by a small integer (typically set to 1).”, thus, an input unit configured to receive and integrate signals and discharge input signals until an amount of signals is less than or equal to a threshold is disclosed – See Figure 7A which shows how the circuit takes in an input of an external signal and discharges the signals to generate an according pulse/spike. As disclosed in Par. [0110], the capacitor may reach a threshold value by which a decay event may occur to quickly discharge the capacitor and according circuit); and
an output unit configured to receive a signal output from the input unit to perform up-counting and generate an output signal while down-counting is performed (Arthur, Par. [0102], “The mixed-mode neuron maintains its membrane potential (state) in a digital state counter 62. When the neuron receives an external signal comprising a spike from an excitatory neuron, the state counter 62 is incremented by a small integer (typically set to 1). When the neuron receives an external signal comprising a spike from an inhibitory neuron the state counter 62 is decremented by a small integer (typically set to 1). The increments and decrements are carried out in a power-efficient bit-wise fashion so that only those bits in the state counter 62 that need to change are modified. If the state counter exceeds a threshold as determined by a comparator 63, then the neuron fires and emits a spike via a pulse module 64.”, thus, an output unit configured to receive a signal output from the input unit to perform up-counting and generate an output signal/spike while down-counting is performed is disclosed).
Regarding Claim 2, Arthur teaches the neuron circuit of claim 1, wherein the input unit comprises:
an integrator configured to integrate the input signals (Arthur, Par. [0040], “A first implementation of the invention comprises a linear-leak integrate and fire (LL-IF) electronic neuron 80 as shown by an example block diagram in FIG. 3A. For each excitatory spike received by the LL-IF neuron 80, an input integrator module 81 increases a membrane potential V of the neuron by a certain amount s+, while for each inhibitory spike the neuron receives the input integrator module 81 decreases V by a certain amount s−.”, thus, an input integrator configured to receive and integrate signals is disclosed);
a discharger configured to linearly discharge a signal corresponding to a preset discharge amount from the integrated input signals until the amount of the integrated signals is less than or equal to the threshold (Arthur, Par. [0117-0118], “When the electronic neuron 60 spikes, the capacitor C is quickly discharged. Further, the following operations are executed: STEP1: The capacitor C slowly charges from a starting value (FIG. 9). If a spike event just occurred, the starting value is zero, otherwise the starting value is the charge the capacitor C already has. When the capacitor C reaches a first threshold value (e.g., 86.5% of its full charge), a decay event occurs and the following are executed: […]” & Par. [0125], “STEP 2: The capacitor C then slowly discharges as shown in FIG. 10, starting from the charge that it already has. When the capacitor C reaches a second threshold value (e.g., about 13.5% or 14.5% of its full charge), a decay event occurs and the following operations are executed: […]”, thus, a discharger is disclosed which linearly discharges a signal corresponding to a preset discharge amount from the integrated input signals until the amount is less than or equal to a threshold. Further, Figure 3A discloses a linear integrate and fire electronic neuron); and
a comparator configured to compare the threshold with a residual amount obtained by subtracting an amount of signal discharged by the discharger from an amount of the integrated input signals and transmit a signal to the output unit until the residual amount is less than or equal to the threshold (Arthur, Par. [0102], “The increments and decrements are carried out in a power-efficient bit-wise fashion so that only those bits in the state counter 62 that need to change are modified. If the state counter exceeds a threshold as determined by a comparator 63, then the neuron fires and emits a spike via a pulse module 64.”, therefore, a comparator configured to compare the threshold with a residual amount and transmit a signal to the output unit/pulse module. This is also depicted by Figure 7A).
Regarding Claim 3, Arthur teaches the neuron circuit of claim 2, wherein the output unit comprises:
a counter configured to receive a signal output from the comparator to perform the up-counting and then perform the down-counting (Arthur, Par. [0092], “Event-based neuron updates may also be utilized. The update rules described herein provide updates of an electronic neuron in a digital clock driven fashion, with one or more state variables changing in each time step. The neurons may be simulated in an event-based fashion such that state variables only change when an event occurs. This can be achieved by keeping a counter, K, for each neuron, which is set to zero each time an event occurs and increments by 1 in each time step. The state variable processes then change each time an event occurs according to this counter.”, thus, a counter is disclosed to receive a signal output from the comparator to perform up-counting/down-counting. This is also shown by Figure 7A); and
an output generator configured to receive a signal output from the counter to generate an output signal and output the generated output signal to a synaptic array connected to an output terminal (Arthur, Par. [0102], “If the state counter exceeds a threshold as determined by a comparator 63, then the neuron fires and emits a spike via a pulse module 64.”, thus, the pulse module is configured to receive a signal output from the counter to generate an output signal and output the generated signal to a synaptic array – See Figure 1 for synaptic array).
Claim Rejections - 35 USC § 103
8. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 4 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Arthur et al. (hereinafter Arthur) (US PG-PUB 20120150781), in view of Chun et al. (hereinafter Chun) (US Patent 10778238).
Regarding Claim 4, Arthur teaches the neuron circuit of claim 3.
Arthur does not explicitly disclose operations of the integrator and the discharger are controlled by a first clock signal, and operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal.
However, Chun teaches operations of the integrator and the discharger are controlled by a first clock signal (Chun, Col. 9 lines 1-4, “The first counter 410 counts the first comparison signal VC1 received from the first comparator 310 by using the first clock signal CLK1 (see FIG. 8) to output the first count value CV1.”, thus, the operations of the first comparator (which incorporate operations of both the integration unit and the discharge unit) are controlled by a first clock signal), and operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal (Chun, Col. 9 lines 5-8, “The second counter 420 counts the second comparison signal VC2 received from the second comparator 320 by using the second clock signal CLK2 (see FIG. 8) to output the second count value CV2.”, thus, the operations of the comparator, counter, and output are controlled by both a first and second clock signal).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit of claim 3, as disclosed by Arthur to include wherein operations of the integrator and the discharger are controlled by a first clock signal, and operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal, as disclosed by Chun. One of ordinary skill in the art would have been motivated to make this modification to increase resolution by using an additional clock signal having a higher frequency, hence improving precision and accuracy of the circuit (Chun, Col. 1 lines 50-56, “However, since typical dual-slope ADC performs counting using a clock signal, the resolution is determined based on the frequency of a clock signal used and the resolution may be increased by using a clock signal having a high frequency. However, there is a disadvantage in that an expensive clock generator may be required to generate the high frequency, thus, increasing cost.”).
Regarding Claim 7, Arthur teaches a neuromorphic device (Arthur, Par. [0002], “The present invention relates generally to neuromorphic and synaptronic systems, and more specifically to neuromorphic and synaptronic systems based on spike-timing dependent plasticity.”, thus, a neuromorphic device is disclosed) comprising:
a synaptic array including one or more synaptic elements (Arthur, Par. [0012], “FIG. 1 shows diagram of a neuromorphic and synaptronic system having a crossbar array interconnecting integrate and fire electronic neurons, in accordance with an embodiment of the invention;”, thus, a synaptic array including one or more elements is disclosed and better depicted by Figure 1); and
a neuron circuit connected to the synaptic array (Arthur, Par. [0139], “A low-power event-driven (LPED) electronic neuron circuit is a hardware realization of the LL-IF neuron described hereinabove.”, thus, a neuron circuit that processes a signal transmitted through a synaptic array is disclosed. Figure 1 better depicts the synaptronic system having a crossbar array interconnecting integrate and fire electronic neurons),
wherein the neuron circuit includes an input unit configured to receive and integrate signals transmitted through the synaptic array as input signals and discharge integrated input signals until an amount of the integrated input signals is less than or equal to a preset threshold (Arthur, Par. [0102], “FIG. 7A shows a diagram of an example implementation of a mixed-mode digital-analog, integrate and fire electronic neuron 60, according to the invention. The mixed-mode neuron maintains its membrane potential (state) in a digital state counter 62. When the neuron receives an external signal comprising a spike from an excitatory neuron, the state counter 62 is incremented by a small integer (typically set to 1).”, thus, an input unit configured to receive and integrate signals and discharge input signals until an amount of signals is less than or equal to a threshold is disclosed – See Figure 7A which shows how the circuit takes in an input of an external signal and discharges the signals to generate an according pulse/spike. As disclosed in Par. [0110], the capacitor may reach a threshold value by which a decay event may occur to quickly discharge the capacitor and according circuit), and an output unit configured to perform up-counting in response to a signal output from the input unit, a first clock signal, and a second clock signal (See introduction of Chun reference below for teaching of a second clock signal), and then generate an output signal while performing down-counting (Arthur, Par. [0102], “The mixed-mode neuron maintains its membrane potential (state) in a digital state counter 62. When the neuron receives an external signal comprising a spike from an excitatory neuron, the state counter 62 is incremented by a small integer (typically set to 1). When the neuron receives an external signal comprising a spike from an inhibitory neuron the state counter 62 is decremented by a small integer (typically set to 1). The increments and decrements are carried out in a power-efficient bit-wise fashion so that only those bits in the state counter 62 that need to change are modified. If the state counter exceeds a threshold as determined by a comparator 63, then the neuron fires and emits a spike via a pulse module 64.”, thus, an output unit configured to receive a signal output from the input unit to perform up-counting and generate an output signal/spike while down-counting is performed is disclosed. Arthur also discloses the use of a clock signal to provide time steps for neuron processing/output, as better described by Par. [0040]).
Arthur does not explicitly disclose a second clock signal
However, Chun teaches a second clock signal (Chun, Col. 5 lines 30-31, “ FIG. 9 is a diagram illustrating an example of a first clock signal and a second clock signal of FIG. 8”, therefore, a second clock signal is disclosed. Further, as shown by Figure 2, the second clock signal may be used by the second counter to perform up-counting in response to an outputted signal)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuromorphic device of claim 7, as disclosed by Arthur to include a second clock signal, as disclosed by Chun. One of ordinary skill in the art would have been motivated to make this modification to increase resolution using an additional clock signal having a higher frequency, hence improving precision and accuracy of the circuit (Chun, Col. 1 lines 50-56, “However, since typical dual-slope ADC performs counting using a clock signal, the resolution is determined based on the frequency of a clock signal used and the resolution may be increased by using a clock signal having a high frequency. However, there is a disadvantage in that an expensive clock generator may be required to generate the high frequency, thus, increasing cost.”).
Claim 8 recites substantially the same limitations as Claim 2 in the form of a neuromorphic device, therefore it is rejected under the same rationale.
Regarding Claim 9, Arthur in view of Chun teaches the neuromorphic device of claim 8, wherein the output unit comprises:
a counter configured to perform the up-counting in response to the signal output from the comparator and the first clock signal and the second clock signal, and then perform the down-counting and transmits a signal to an output generator (Arthur, Par. [0092], “Event-based neuron updates may also be utilized. The update rules described herein provide updates of an electronic neuron in a digital clock driven fashion, with one or more state variables changing in each time step. The neurons may be simulated in an event-based fashion such that state variables only change when an event occurs. This can be achieved by keeping a counter, K, for each neuron, which is set to zero each time an event occurs and increments by 1 in each time step. The state variable processes then change each time an event occurs according to this counter.”, thus, a counter is disclosed to receive a signal output from the comparator to perform up-counting/down-counting. This is also shown by Figure 7A. Further, Chun Col. 4 lines 17-23 states “The control circuit may include a first counter configured to count the first comparison signal, using the first clock signal, and output the first count value; a second counter configured to count the second comparison signal, using the second clock signal having a phase different from a phase of the first clock signal by 180 degrees, and outputting the second count value;” – hence, the second clock signal is used by the counter to perform counting); and
the output generator configured to receive the signal output from the counter to generate the output signal and output the generated output signal to a next synaptic array connected to an output terminal (Arthur, Par. [0102], “If the state counter exceeds a threshold as determined by a comparator 63, then the neuron fires and emits a spike via a pulse module 64.”, thus, the pulse module is configured to receive a signal output from the counter to generate an output signal and output the generated signal to a synaptic array – See Figure 1 for synaptic array).
The reasons of obviousness have been noted in the rejection of Claim 7 above and applicable herein.
Claim 10 recites substantially the same limitations as Claim 4 in the form of a neuromorphic device, therefore it is rejected under the same rationale.
10. Claims 5-6 and 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Arthur et al. (hereinafter Arthur) (US PG-PUB 20120150781), in view of Chun et al. (hereinafter Chun) (US Patent 10778238), further in view of Baker et al. (hereinafter Baker) (US PG-PUB 20080309530).
Regarding Claim 5, Arthur in view of Chun teaches the neuron circuit of claim 4.
Arthur in view of Chun does not explicitly teach performing the below operations when a state of the first clock signal is a low state:
when a state of the first clock signal is a low state,
the integrator is connected to the discharger, the integrator is connected to the comparator,
the discharger linearly discharges a signal corresponding to a discharge amount from the amount of the integrated input signals,
the comparator transmits an up-counting maintenance signal to the counter in response to the second clock signal until the residual amount is less than or equal to the threshold, and
wherein the counter performs up-counting in response to the up-counting maintenance signal and the second clock signal received from the comparator.
However, Baker teaches:
when a state of the first clock signal is a low state (Baker, Par. [0063], “Starting with the charging state (FIG. 9), the capacitor 98 may initially accumulate a charge (e.g., become more charged). To this end, the output of the comparator 96 is latched to logic low, which, as mentioned above, may occur when VBL is less than VREF.”, therefore, the state of the clock signal is low),
the integrator is connected to the discharger, the integrator is connected to the comparator (Baker, Par. [0063], “The logic low may be conveyed to switch 100 by the feedback signal path 102, and the switch 100 may close, thereby conducting the reference current IREF through one of the bit- lines 38, 40, 42, 44, or 46, as indicated by the larger arrows in FIG. 9.”, therefore, when the state is low, the switch is closed thereby connecting the integrator, discharger, and comparator to conduct current through),
the discharger linearly discharges a signal corresponding to a discharge amount from the amount of the integrated input signals (Baker, Par. [0063], “A portion of the electrons flowing through the reference current source 104 may be accumulated by the capacitor 98, as indicated by the smaller-horizontal arrows, and the remainder may be conducted through the memory element 64, i.e., the bit-line current IBIT, as indicated by the smaller vertical arrows. Thus, the capacitor 98 may accumulate a charge, and VBL may increase.”, thus, the discharger may discharge a signal corresponding to a discharge amount),
the comparator transmits an up-counting maintenance signal to the counter in response to the second clock signal until the residual amount is less than or equal to the threshold (Baker, Par. [0064], “The comparator 96 and the reference current source 104 may cooperate to charge the capacitor 98 for a discrete number of clock cycles. That is, when the delta-sigma modulator 88 transitions to the charging state, the delta-sigma modulator 88 may remain in this state for an integer number of clock cycles. In the illustrated embodiment, the comparator 96, the output of which is latched, changes state no more than once per clock cycle, so the switch 100, which is controlled by the output of the comparator 96, VFB, conducts current for a discrete number of clock cycles. As a result, the reference current source 104 conducts current IREF through the bit-line and into the capacitor 98 for an integer number of clock cycles.”, therefore, a comparator transmits an up counting signal to the counter in response to a clock signal until the amount is less than or equal to a threshold (See Figure 9 for illustration of this process), and
wherein the counter performs up-counting in response to the up-counting maintenance signal and the second clock signal received from the comparator (Baker, Par. [0067], “The counter 90 may count the number of clock cycles that the delta-sigma modulator 88 is in either the charging state or the discharging state by monitoring the bit-stream signal path 94. The bit-stream signal path 94 may transition back and forth between logic high and logic low with the output of the comparator 96, VFB, and the counter 90 may increment and/or decrement a count once per clock cycle (or other appropriate interval) based on whether the bit-stream is logic high or logic low. After the sensing time has passed, the counter 90 may output a signal indicative of the count on output terminals D0-D5. As explained below, the count may correspond, e.g., proportionally, to the bit-line current, IBIT.”, thus, the counter performed up-counting in response to the signals received from the comparator).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit of claim 4, as disclosed by Arthur in view of Chun to include when a state of the first clock signal is a low state, the integrator is connected to the discharger, the integrator is connected to the comparator, the discharger linearly discharges a signal corresponding to a discharge amount from the amount of the integrated input signals, the comparator transmits an up-counting maintenance signal to the counter in response to the second clock signal until the residual amount is less than or equal to the threshold, and wherein the counter performs up-counting in response to the up-counting maintenance signal and the second clock signal received from the comparator, as disclosed by Baker. One of ordinary skill in the art would have been motivated to make this modification to enable synchronized operations for either charging/discharging the circuit, hence improving timing control of circuit state changes (Baker, Par. [0067], “The counter 90 may count the number of clock cycles that the delta-sigma modulator 88 is in either the charging state or the discharging state by monitoring the bit-stream signal path 94. The bit-stream signal path 94 may transition back and forth between logic high and logic low with the output of the comparator 96, VFB, and the counter 90 may increment and/or decrement a count once per clock cycle (or other appropriate interval) based on whether the bit-stream is logic high or logic low.”)
Regarding Claim 6, Arthur in view of Chun teaches the neuron circuit of claim 4.
Arthur in view of Chun does not explicitly teach performing the below operations when a state of the first clock signal is in a high state:
when a state of the first clock signal is in a high state,
the integrator is disconnected from the discharger, and the integrator is disconnected from the comparator,
the integrator receives and integrates the input signals, and
the counter generates an output signal through the output generator in response to the second clock signal while the down-counting is performed.
However, Baker teaches:
when a state of the first clock signal is in a high state (Baker, Par. [0066], “In the present embodiment, the delta-sigma modulator 88 discharges the capacitor 98 for a discrete number of clock intervals. After each clock cycle of discharging the capacitor 98, the delta-sigma modulator 88 compares VBL to VREF. If VBL is still greater than VREF, then the comparator 96 may continue to output a logic high signal, i.e., VFB=1, and the switch 100 remains open.”, thus, the state of the clock signal is high),
the integrator is disconnected from the discharger, and the integrator is disconnected from the comparator (Baker, Par. [0065], “The logic high signal may be conveyed to the switch 100 by the feedback signal path 102, thereby opening the switch 100. As a result, the reference current source 104 may cease conducting current through the memory element 64 and into the capacitor 98, and the capacitor 98 may begin to discharge through the memory element 64.”, thus, when the state is high, the switch is open thereby disconnecting the integrator, discharger, and comparator, as current is not conducted through the circuit),
the integrator receives and integrates the input signals (Baker, Par. [0066], “In the present embodiment, the delta-sigma modulator 88 discharges the capacitor 98 for a discrete number of clock intervals. After each clock cycle of discharging the capacitor 98, the delta-sigma modulator 88 compares VBL to VREF. If VBL is still greater than VREF, then the comparator 96 may continue to output a logic high signal, i.e., VFB=1, and the switch 100 remains open.”, thus, the integrator still receives and integrates input signals), and
the counter generates an output signal through the output generator in response to the second clock signal while the down-counting is performed (Baker, Par. [0067], “The counter 90 may count the number of clock cycles that the delta-sigma modulator 88 is in either the charging state or the discharging state by monitoring the bit-stream signal path 94. The bit-stream signal path 94 may transition back and forth between logic high and logic low with the output of the comparator 96, VFB, and the counter 90 may increment and/or decrement a count once per clock cycle (or other appropriate interval) based on whether the bit-stream is logic high or logic low. After the sensing time has passed, the counter 90 may output a signal indicative of the count on output terminals D0-D5. As explained below, the count may correspond, e.g., proportionally, to the bit-line current, IBIT.”, thus, the counter performs down-counting in response to the signals received).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the neuron circuit of claim 4, as disclosed by Arthur in view of Chun to include when a state of the first clock signal is in a high state, the integrator is disconnected from the discharger, and the integrator is disconnected from the comparator, the integrator receives and integrates the input signals, and the counter generates an output signal through the output generator in response to the second clock signal while the down-counting is performed, as disclosed by Baker. One of ordinary skill in the art would have been motivated to make this modification to enable synchronized operations for either charging/discharging the circuit, hence improving timing control of circuit state changes (Baker, Par. [0067], “The counter 90 may count the number of clock cycles that the delta-sigma modulator 88 is in either the charging state or the discharging state by monitoring the bit-stream signal path 94. The bit-stream signal path 94 may transition back and forth between logic high and logic low with the output of the comparator 96, VFB, and the counter 90 may increment and/or decrement a count once per clock cycle (or other appropriate interval) based on whether the bit-stream is logic high or logic low.”)
Claim 11 recites substantially the same limitations as Claim 5 in the form of a neuromorphic device, therefore it is rejected under the same rationale.
Claim 12 recites substantially the same limitations as Claim 6 in the form of a neuromorphic device, therefore it is rejected under the same rationale.
Regarding Claim 13, Arthur teaches an operating method of a neuron circuit which includes an integrator, a discharger, a comparator, a counter, and an output generator and processes a signal transmitted through a synaptic array (Arthur, Par. [0139], “A low-power event-driven (LPED) electronic neuron circuit is a hardware realization of the LL-IF neuron described hereinabove.”, thus, a neuron circuit that processes a signal transmitted through a synaptic array is disclosed. Figure 1 better depicts the synaptronic system having a crossbar array interconnecting integrate and fire electronic neurons. See Figures 3A-3D & Figure 7 which explicitly show the neuron circuit having an input integrator, a discharger/capacitor, a comparator, a spike dependent state counter/counter, and an output generator/pulse module), wherein operations of the integrator and the discharger are controlled by a first clock signal and operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal (See introduction of Chun reference below for teaching of the operations being controlled by a first/second clock signal), the operating method comprising:
receiving, by the integrator, weighted signals transmitted through the synaptic array and integrating the weighted signals (Arthur, Par. [0040], “A first implementation of the invention comprises a linear-leak integrate and fire (LL-IF) electronic neuron 80 as shown by an example block diagram in FIG. 3A. For each excitatory spike received by the LL-IF neuron 80, an input integrator module 81 increases a membrane potential V of the neuron by a certain amount s+, while for each inhibitory spike the neuron receives the input integrator module 81 decreases V by a certain amount s−.”, thus, an input integrator configured to receive and integrate signals is disclosed), in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when a state of the first clock signal is in a high state (See introduction of Baker reference below for teaching of specific operations being performed when the clock signal is in a high/low state);
receiving input signals integrated by the integrator, linearly discharging a signal corresponding to a preset discharge amount from an amount of the integrated input signals (Arthur, Par. [0117-0118], “When the electronic neuron 60 spikes, the capacitor C is quickly discharged. Further, the following operations are executed: STEP1: The capacitor C slowly charges from a starting value (FIG. 9). If a spike event just occurred, the starting value is zero, otherwise the starting value is the charge the capacitor C already has. When the capacitor C reaches a first threshold value (e.g., 86.5% of its full charge), a decay event occurs and the following are executed: […]” & Par. [0125], “STEP 2: The capacitor C then slowly discharges as shown in FIG. 10, starting from the charge that it already has. When the capacitor C reaches a second threshold value (e.g., about 13.5% or 14.5% of its full charge), a decay event occurs and the following operations are executed: […]”, thus, a discharger is disclosed which linearly discharges a signal corresponding to a preset discharge amount from the integrated input signals until the amount is less than or equal to a threshold. Further, Figure 3A discloses a linear integrate and fire electronic neuron), comparing, by the comparator, a residual amount obtained by subtracting an amount of a signal discharged by the discharger from the amount of the integrated input signals with a preset threshold to transmit an up-counting maintenance signal to the counter until the residual amount is less than or equal to the preset threshold (Arthur, Par. [0102], “The increments and decrements are carried out in a power-efficient bit-wise fashion so that only those bits in the state counter 62 that need to change are modified. If the state counter exceeds a threshold as determined by a comparator 63, then the neuron fires and emits a spike via a pulse module 64.”, therefore, a comparator configured to compare the threshold with a residual amount and transmit a signal to the output unit/pulse module. This is also depicted by Figure 7A), and performing, by the counter, the up-counting in response to a signal received from the comparator and the second clock signal, in a case in which the integrator is connected to the discharger and the integrator is connected to the comparator when the state of the first clock signal is in a low state (See introduction of Baker reference below for teaching of specific operations being performed when the clock signal is in a high/low state); and
receiving, by the integrator, new weighted signals transmitted through the synaptic array, integrating the new weighted signals (Arthur, Par. [0040], “A first implementation of the invention comprises a linear-leak integrate and fire (LL-IF) electronic neuron 80 as shown by an example block diagram in FIG. 3A. For each excitatory spike received by the LL-IF neuron 80, an input integrator module 81 increases a membrane potential V of the neuron by a certain amount s+, while for each inhibitory spike the neuron receives the input integrator module 81 decreases V by a certain amount s−.”, thus, an input integrator configured to receive and integrate signals is disclosed), and generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal, in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when the state of the first clock signal is switched to the high state (See introduction of Baker reference below for teaching of specific operations being performed when the clock signal is in a high/low state).
Arthur does not explicitly disclose wherein operations of the integrator and the discharger are controlled by a first clock signal and operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal.
However, Chun teaches wherein operations of the integrator and the discharger are controlled by a first clock signal (Chun, Col. 9 lines 1-4, “The first counter 410 counts the first comparison signal VC1 received from the first comparator 310 by using the first clock signal CLK1 (see FIG. 8) to output the first count value CV1.”, thus, the operations of the first comparator (which incorporate operations of both the integration unit and the discharge unit) are controlled by a first clock signal), and operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal (Chun, Col. 9 lines 5-8, “The second counter 420 counts the second comparison signal VC2 received from the second comparator 320 by using the second clock signal CLK2 (see FIG. 8) to output the second count value CV2.”, thus, the operations of the comparator, counter, and output are controlled by both a first and second clock signal).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of a neuron circuit, as disclosed by Arthur to include wherein operations of the integrator and the discharger are controlled by a first clock signal, and operations of the comparator, the counter, and the output generator are controlled by the first clock signal and a second clock signal, as disclosed by Chun. One of ordinary skill in the art would have been motivated to make this modification to increase resolution by using an additional clock signal having a higher frequency, hence improving precision and accuracy of the circuit (Chun, Col. 1 lines 50-56, “However, since typical dual-slope ADC performs counting using a clock signal, the resolution is determined based on the frequency of a clock signal used and the resolution may be increased by using a clock signal having a high frequency. However, there is a disadvantage in that an expensive clock generator may be required to generate the high frequency, thus, increasing cost.”).
Arthur in view of Chun does not explicitly disclose:
in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when a state of the first clock signal is in a high state
performing, by the counter, the up-counting in response to a signal received from the comparator and the second clock signal, in a case in which the integrator is connected to the discharger and the integrator is connected to the comparator when the state of the first clock signal is in a low state
generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal, in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when the state of the first clock signal is switched to the high state
However, Baker teaches:
in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when a state of the first clock signal is in a high state (Baker, Par. [0065], “The logic high signal may be conveyed to the switch 100 by the feedback signal path 102, thereby opening the switch 100. As a result, the reference current source 104 may cease conducting current through the memory element 64 and into the capacitor 98, and the capacitor 98 may begin to discharge through the memory element 64.”, thus, when the state is high, the switch is open thereby disconnecting the integrator, discharger, and comparator, as current is not conducted through the circuit),
performing, by the counter, the up-counting in response to a signal received from the comparator and the second clock signal (Baker, Par. [0067], “The counter 90 may count the number of clock cycles that the delta-sigma modulator 88 is in either the charging state or the discharging state by monitoring the bit-stream signal path 94. The bit-stream signal path 94 may transition back and forth between logic high and logic low with the output of the comparator 96, VFB, and the counter 90 may increment and/or decrement a count once per clock cycle (or other appropriate interval) based on whether the bit-stream is logic high or logic low. After the sensing time has passed, the counter 90 may output a signal indicative of the count on output terminals D0-D5. As explained below, the count may correspond, e.g., proportionally, to the bit-line current, IBIT.”, thus, the counter performed up-counting in response to the signals received from the comparator), in a case in which the integrator is connected to the discharger and the integrator is connected to the comparator when the state of the first clock signal is in a low state (Baker, Par. [0063], “The logic low may be conveyed to switch 100 by the feedback signal path 102, and the switch 100 may close, thereby conducting the reference current IREF through one of the bit- lines 38, 40, 42, 44, or 46, as indicated by the larger arrows in FIG. 9.”, therefore, when the state is low, the switch is closed thereby connecting the integrator, discharger, and comparator to conduct current through),
generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal, in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when the state of the first clock signal is switched to the high state (Baker, Par. [0067], “The counter 90 may count the number of clock cycles that the delta-sigma modulator 88 is in either the charging state or the discharging state by monitoring the bit-stream signal path 94. The bit-stream signal path 94 may transition back and forth between logic high and logic low with the output of the comparator 96, VFB, and the counter 90 may increment and/or decrement a count once per clock cycle (or other appropriate interval) based on whether the bit-stream is logic high or logic low. After the sensing time has passed, the counter 90 may output a signal indicative of the count on output terminals D0-D5. As explained below, the count may correspond, e.g., proportionally, to the bit-line current, IBIT.”, thus, the counter performs down-counting in response to the signals received).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of a neuron circuit, as disclosed by Arthur in view of Chun to include in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when a state of the first clock signal is in a high state, performing, by the counter, the up-counting in response to a signal received from the comparator and the second clock signal, in a case in which the integrator is connected to the discharger and the integrator is connected to the comparator when the state of the first clock signal is in a low state, generating, by the counter, an output signal through the output generator while performing down-counting in response to the second clock signal, in a case in which the integrator is disconnected from the discharger and the integrator is disconnected from the comparator when the state of the first clock signal is switched to the high state, as disclosed by Baker. One of ordinary skill in the art would have been motivated to make this modification to enable synchronized operations for either charging/discharging the circuit, hence improving timing control of circuit state changes (Baker, Par. [0067], “The counter 90 may count the number of clock cycles that the delta-sigma modulator 88 is in either the charging state or the discharging state by monitoring the bit-stream signal path 94. The bit-stream signal path 94 may transition back and forth between logic high and logic low with the output of the comparator 96, VFB, and the counter 90 may increment and/or decrement a count once per clock cycle (or other appropriate interval) based on whether the bit-stream is logic high or logic low.”)
Conclusion
11. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Devika S Maharaj whose telephone number is (571)272-0829. The examiner can normally be reached Monday - Thursday 8:30am - 5:30pm.
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/DEVIKA S MAHARAJ/Examiner, Art Unit 2123
/ALEXEY SHMATOV/Supervisory Patent Examiner, Art Unit 2123
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