DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed August 1, 2024 fails to comply with 37 CFR 1.98(a)(1), which requires the following: (1) a list of all patents, publications, applications, or other information submitted for consideration by the Office; (2) U.S. patents and U.S. patent application publications listed in a section separately from citations of other documents; (3) the application number of the application in which the information disclosure statement is being submitted on each page of the list; (4) a column that provides a blank space next to each document to be considered, for the examiner’s initials; and (5) a heading that clearly indicates that the list is an information disclosure statement. The information disclosure statement has been placed in the application file, but the information referred to therein has not been considered.
The examiner notes that all information listed on the IDS has been considered. However, the applicant also submitted an NPL document (August 1, 2024) that was not listed on the IDS. While the NPL document has been placed in the file wrapper, the NPL has not been considered.
Claim Objections
The objection to Claims 10 and 15 – 20 for the limitation “calculate a difference between the current sensed data and the initial sensed data for the plurality of pixels and the initial sensed data for the plurality of pixels to remove noise included in the current sensed data” is withdrawn in light of the amendment to at least Claim 10.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6, 8 – 10, 15, 17 – 18, and 21 – 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (U.S. PG Pub 2017/0076660).
Regarding Claim 1, Lee teaches a degradation compensation circuit (Figure 5, Element 450. Paragraph 98) for compensating for degradation of a display device (Figure 1, Element 100. Paragraph 47), the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) configured to:
receive initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for each pixel coordinate, the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) indicating characteristic of each of a plurality of pixels of a display panel (Figure 1, Element 110. Paragraph 48) of the display device (Figure 1, Element 100. Paragraph 47), from a sensing circuit (Figure 5, Element 432. Paragraph 92) configured to sense pixel (Paragraph 48) signals corresponding to driving currents (Figure 5, Elements ELVDD1_L, ELVDD2_L, and ELVDD3_L. Paragraph 92) flowing through each of the plurality of pixels of the display panel (Figure 1, Element 110. Paragraph 48);
compare the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for the plurality of pixels;
determine that noise is included in the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) of a corresponding pixel (Paragraph 48) when a first difference among the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) of the plurality of pixels exceeds a reference value (Paragraph 92. The examiner notes that any signal will be deemed to meet this limitation since the instant claim does not limit the reference value.);
store a first noise level (Figure 5, Element RN + GN at time T1. Paragraph 95) of the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) exceeding the reference value (Paragraph 92. The examiner notes that any signal will be deemed to meet this limitation since the instant claim does not limit the reference value.) and a pixel coordinate of a corresponding pixel (Paragraph 48) when noise is determined to be included in the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94);
receive current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) for each pixel coordinate, the current sensed data indicating a degradation of each of the plurality of pixels of the display panel (Figure 1, Element 110. Paragraph 48) from the sensing circuit (Figure 5, Element 432. Paragraph 92);
modify a second noise level (Figure 5, Elements RS + RN + GN at T2. Paragraphs 92 and 96) of the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) corresponding to the pixel coordinate where the first noise level is stored, to the first noise level (Figure 5, Element RN + GN at time T1. Paragraph 95) of the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94);
calculate a second difference (Paragraph 97) between the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) and the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for the plurality of pixels to remove noise (Paragraph 97) included in the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96); and
extract degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) for each of the plurality of pixels based on the second difference (Paragraph 97).
Regarding Claim 6, Lee teaches the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) of claim 1 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to store therein a value of the second difference (Paragraphs 95 – 97) for each pixel (Paragraph 48) coordinate.
Regarding Claim 8, Lee teaches the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) of claim 1 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to:
receive the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) from the sensing circuit (Figure 5, Element 432. Paragraph 92) sensing the pixel (Paragraph 48) signal of the display panel (Figure 1, Element 110. Paragraph 48) during an initial operation (Figure 5, Element T1. Paragraph 95) of the display panel (Figure 1, Element 110. Paragraph 48); and
determine that the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) of the corresponding pixel (Paragraph 48) contains noise when there is data exceeding the reference value (Paragraph 92. The examiner notes that any signal will be deemed to meet this limitation since the instant claim does not limit the reference value.) among the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for the plurality of pixels (Paragraph 48).
Regarding Claim 9, Lee teaches the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) of claim 8 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to:
receive the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) from the sensing circuit (Figure 5, Element 432. Paragraph 92) in a preset period (Figure 5, Element T2. Paragraph 96) of a display period (Figure 5, Element T2. Paragraph 96) after the initial operation (Figure 5, Element T1. Paragraph 95) of the display panel (Figure 1, Element 110. Paragraph 48); and
modify the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) of the corresponding pixel containing the noise to the first noise level (Figure 5, Element RN + GN at time T1. Paragraph 95).
Regarding Claim 10, Lee teaches a display device (Figure 1, Element 100. Paragraph 47) comprising:
a display panel (Figure 1, Element 110. Paragraph 48) including a plurality of pixels (Paragraph 48);
a sensing circuit (Figure 5, Element 432. Paragraph 92) configured to sense pixel (Paragraph 48) signals corresponding to a driving currents (Figure 5, Elements ELVDD1_L, ELVDD2_L, and ELVDD3_L. Paragraph 92) flowing through each of the plurality of pixels from the display panel (Figure 1, Element 110. Paragraph 48), convert the pixel (Paragraph 48) signals into sensed data (Figure 5, Elements DR, DG, and DB. Paragraph 92), and provide the sensed data (Figure 5, Elements DR, DG, and DB. Paragraph 92) as initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) or current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96); and
a degradation compensation circuit (Figure 5, Element 450. Paragraph 98) configured to compensate for a degradation of each of the plurality of pixels (Paragraph 48) of the display panel (Figure 1, Element 110. Paragraph 48),
wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is configured to:
receive initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for each pixel coordinate, the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) indicating characteristic of each of a plurality of pixels of a display panel (Figure 1, Element 110. Paragraph 48), from the sensing circuit (Figure 5, Element 432. Paragraph 92);
compare the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for the plurality of pixels;
determine that noise is included in the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) of a corresponding pixel (Paragraph 48) when a first difference among the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) of the plurality of pixels exceeds a reference value (Paragraph 92. The examiner notes that any signal will be deemed to meet this limitation since the instant claim does not limit the reference value.);
store a first noise level (Figure 5, Element RN + GN at time T1. Paragraph 95) of the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) exceeding the reference value (Paragraph 92. The examiner notes that any signal will be deemed to meet this limitation since the instant claim does not limit the reference value.) and a pixel coordinate of a corresponding pixel (Paragraph 48) in a memory, when noise is determined to be included in the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94);
receive current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) for each pixel coordinate, the current sensed data indicating a degradation of each of the plurality of pixels of the display panel (Figure 1, Element 110. Paragraph 48) from the sensing circuit (Figure 5, Element 432. Paragraph 92);
modify a second noise level (Figure 5, Elements RS + RN + GN at T2. Paragraphs 92 and 96) of the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) corresponding to the pixel coordinate where the first noise level is stored, to the first noise level (Figure 5, Element RN + GN at time T1. Paragraph 95) of the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94);
calculate a second difference (Paragraph 97) between the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) and the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for each of the plurality of pixels to remove noise (Paragraph 97) included in the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96); and
extract degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) for each of the plurality of pixels based on the second difference (Paragraph 97).
Regarding Claim 15, Lee teaches the display device (Figure 1, Element 100. Paragraph 47) of claim 10 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to store a value of the second difference (Paragraphs 95 – 97) for each pixel (Paragraph 48) coordinate in the memory.
Regarding Claim 17, Lee teaches the display device (Figure 1, Element 100. Paragraph 47) of claim 10 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to:
receive the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) from the sensing circuit (Figure 5, Element 432. Paragraph 92) sensing the pixel (Paragraph 48) signal of the display panel (Figure 1, Element 110. Paragraph 48) during an initial operation (Figure 5, Element T1. Paragraph 95) of the display panel (Figure 1, Element 110. Paragraph 48); and
determine that the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) of the corresponding pixel (Paragraph 48) contains noise when there is data exceeding the reference value (Paragraph 92. The examiner notes that any signal will be deemed to meet this limitation since the instant claim does not limit the reference value.) among the initial sensed data (Figure 5, Elements DR, DG, and DB at T1. Paragraphs 92 and 94) for the plurality of pixels (Paragraph 48).
Regarding Claim 18, Lee teaches the display device (Figure 1, Element 100. Paragraph 47) of claim 17 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to:
receive the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) from the sensing circuit (Figure 5, Element 432. Paragraph 92) in a preset period of a display period (Figure 5, Element T2. Paragraph 96) after the initial operation (Figure 5, Element T1. Paragraph 95) of the display panel (Figure 1, Element 110. Paragraph 48); and
modify the current sensed data (Figure 5, Elements DR, DG, and DB at T2. Paragraphs 92 and 96) of the corresponding pixel containing the noise to the first noise level (Figure 5, Element RN + GN at time T1. Paragraph 95).
Regarding Claim 21, Lee teaches a display device (Figure 1, Element 100. Paragraph 47), comprising the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) of claim 1 (See Above).
Regarding Claim 22, Lee teaches the display device (Figure 1, Element 100. Paragraph 47) of claim 21 (See Above), further comprising the display panel (Figure 1, Element 110. Paragraph 48), which is an organic light-emitting diode display panel (Figure 1, Element 110. Paragraphs 5 – 6 and 48).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the difference (Paragraph 97)s between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub 2017/0076660) in view of Park et al. (U.S. PG Pub 2015/0220177).
Regarding Claim 7, Lee teaches the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) of claim 6 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to:
extract the degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) corresponding to the value of the second difference (Paragraph 97); and
apply the degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) to image data.
Lee is silent with regards to the value of the difference being from a preset lookup table.
Park et al. teach the value of the difference being from a preset lookup table (Paragraph 49).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the degradation compensating display of Lee with the lookup table of Park et al. The motivation to modify the teachings of Lee with the teachings of Park et al. is to provide common voltage compensations corresponding to the pattern of common voltage, as taught by Park et al. (Paragraph 49).
Regarding Claim 16, Lee teaches the display device (Figure 1, Element 100. Paragraph 47) of claim 15 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to:
extract the degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) corresponding to the value of the second difference (Paragraph 97); and
apply the degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) to image data.
Lee is silent with regards to the value of the difference being from a preset lookup table.
Park et al. teach the value of the difference being from a preset lookup table (Paragraph 49).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the degradation compensating display of Lee with the lookup table of Park et al. The motivation to modify the teachings of Lee with the teachings of Park et al. is to provide common voltage compensations corresponding to the pattern of common voltage, as taught by Park et al. (Paragraph 49).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub 2017/0076660) in view of Furukawa et al. (U.S. PG Pub 2017/0372656).
Regarding Claim 19, Lee teaches the display device (Figure 1, Element 100. Paragraph 47) of claim 10 (See Above), wherein the sensing circuit (Figure 5, Element 432. Paragraph 92) and a source driver (Figure 1, Element 150. Paragraph 64), and the source driver (Figure 1, Element 150. Paragraph 64) outputs a source signal corresponding to image data to the display panel (Figure 1, Element 110. Paragraph 48) and receives the pixel signal (Seen in Figure 1) for the plurality of pixels (Paragraph 48) from the display panel (Figure 1, Element 110. Paragraph 48),
wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is included in (Paragraph 63) a timing controller (Figure 1, Element 160. Paragraph 63), and the timing controller (Figure 1, Element 160. Paragraph 63) provides the image data to the source driver (Figure 1, Element 150. Paragraph 64), and
wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to:
apply the degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) to the image data to obtain compensated image data; and
supply the compensated image data to the source driver (Figure 1, Element 150. Paragraph 64).
Lee is silent with regards to wherein the sensing circuit is included in a source driver.
Furukawa et al. teach wherein the sensing circuit (Figure 2, Element 320. Paragraph 72) is included in a source driver (Figure 2, Element 30. Paragraph 72).
It would have been obvious to a person of ordinary skill in the art to modify the teachings of the degradation compensating display of Lee with the placement of the sensing circuit of Furukawa et al. The motivation to modify the teachings of Lee with the teachings of Furukawa et al. is to be able to drive and sense using the same signal line, thereby reducing the wiring running to the pixels, as taught by Furukawa et al. (Paragraph 75).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. PG Pub 2017/0076660) in view of Moon et al. (U.S. PG Pub 2017/0069238).
Regarding Claim 20, Lee teaches the display device (Figure 1, Element 100. Paragraph 47) of claim 10 (See Above), wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) and a source driver (Figure 1, Element 150. Paragraph 64), and the source driver (Figure 1, Element 150. Paragraph 64) outputs a source signal corresponding to image data to the display panel (Figure 1, Element 110. Paragraph 48), and wherein the degradation compensation circuit (Figure 5, Element 450. Paragraph 98) is further configured to apply the degradation compensation data (Figure 5, Elements DC_R, DC_G, and DC_B. Paragraph 82) to the image data received from a timing controller (Figure 1, Element 160. Paragraph 63).
Lee is silent with regards to wherein the degradation compensation circuit is included in a source driver.
Moon et al. teach wherein the degradation compensation circuit is included in a source driver (Paragraph 62).
Lee teaches a device which is different from the claimed interface apparatus by the substitution of the step(s) of the degradation compensation circuit is included in a source driver. Moon et al. teaches the substituted step(s) of the degradation compensation circuit is located in the data driver and their functions were known in the art to provide the degradation compensation circuit is included in a source driver.
The placement of the degradation compensation circuit of Lee could have been substituted with the placement of the degradation compensation circuit as taught by Moon et al. and the results would have been predictable and resulted in the degradation compensation circuit is included in a source driver. Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art at the time the invention was made.
Response to Arguments
Regarding the first argument, in which the applicant asserts that Lee fails to teach at least the specifics of “a sensing circuit configured to sense pixel signals corresponding to driving currents flowing through each of the plurality of pixels of the display panel.” The applicant argues that the Lee teaches sensing power voltage lines rather than sensing the pixel signals based on individual pixel driving currents. The examiner respectfully disagrees with the applicant’s assertion.
The examiner firstly disagrees with the applicant’s interpretation of the instant claim language. The instant limitation states “receive initial sensed data for each pixel coordinate, the initial sensed data indicating characteristics of each of a plurality of pixels of a display panel of the display device, from a sensing circuit configured to sense pixel signals corresponding to driving currents flowing through each of the plurality of pixels of the display panel (Emphasis Added).” This language does not require the limitation to only sense at a pixel level. Rather, the instant claim language, given the broadest reasonable interpretation by a person of ordinary skill in the art and in light of the instant Specification, requires the sensing signals corresponding to driving currents flowing through each of the pixels. Lee discloses:
[0048] The display panel 110 may include a plurality of pixels. In some example embodiments, each of the pixels may include a pixel circuit, a driving transistor, and an organic light emitting diode. In this case, the driving transistor may control a driving current flowing through the organic light emitting diode based on a data signal. The data signal is provided to the driving transistor via a data line DLm in response to a scan signal, and the scan signal is provided via a scan line SLn.
[0049] The power voltage generator 120 may generate a high power voltage ELVDD that is provided to the pixels through a high power voltage line ELVDD_L. The power voltage generator 120 may generate the high power voltage ELVDD to drive the pixels in the display panel 110. The high power voltage ELVDD may be provided to the pixels through the high power voltage line ELVDD_L.
[0050] In some example embodiments, the power voltage generator 120 may provide the high power voltage ELVDD having the same or substantially the same voltage level to red pixels, green pixels, and blue pixels in the display panel 110 through the one high power voltage line ELVDD_L.
[0051] In other example embodiments, the power voltage generator 120 may provide a first high power voltage to the red pixels through a first high power voltage line, a second high power voltage to the green pixels through a second high power voltage line, and a third high power voltage to the blue pixels through a third high power voltage. In some example embodiments, the first high power voltage, the second high power voltage, and the third high power voltage may have the same or substantially the same voltage level. In other example embodiments, the first high power voltage, the second high power voltage, and the third high power voltage may have different voltage levels from each other. Here, the red pixels may be the pixels that emit red color light, the green pixels may be the pixels that emit green color light, and the blue pixels may be the pixels that emit blue color light.
[0052] The power voltage generator 120 may generate a low power voltage and may provide the low power voltage to the pixels through a lower power voltage line. The power voltage generator 120 may not generate the high power voltage ELVDD while a sensing block of the degradation compensator 130 is operated.
[0053] The degradation compensator 130 may calculate an amount of the degradation that represents a degradation degree of the pixels by measuring a power current flowing through the high power voltage line ELVDD_L. The degradation compensator 130 may calculate a compensation amount of a degradation DC of the pixels based on the amount of the degradation and image data R, G, B provided to the pixels. As time passes, a power current flowing through the high power voltage line ELVDD_L may be changed, because the organic light emitting diode included in the pixel is degraded. Therefore, the degradation degree of the pixels may be calculated using a change amount of the power current flowing through the high power voltage line ELVDD_L (Paragraphs 48 – 53. Emphasis Added).”
Lee further discloses “A first sensing circuit 435 of the sensing block 432 may output an integration value of the power current flowing through the first high power voltage line ELVDD1_L as the red output data DR. A second sensing circuit 436 of the sensing block 432 may output an integration value of the power current flowing through the second high power voltage line ELVDD2_L as the green output data DG. A third sensing circuit 437 of the sensing block 432 may output an integration value of the power current flowing through the third high power voltage line ELVDD3_L as the blue output data DB (Paragraph 92. Emphasis Added).” Therefore, it is clear from the above disclosures of Lee that Lee is sensing pixels corresponding to the driving current flowing through each of the plurality of pixels. The Office is unmoved by the applicant’s argument and the rejection is maintained.
All other arguments are held moot in light of the above rejection and/or the response to the first argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Bi et al. (U.S. PG Pub 2017/0256199) and OK et al. (U.S. PG Pub 2020/0372861) disclose a corrector that can compensate a degradation value by comparing sensing data to a state when no degradation has occurred, similar to the instant invention.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW B SCHNIREL whose telephone number is (571)270-7690. The examiner can normally be reached Monday - Friday, 10 - 6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached at 571-272-0666. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.B.S/Examiner, Art Unit 2625
/WILLIAM BODDIE/Supervisory Patent Examiner, Art Unit 2625