DETAILED ACTION
Response to Amendment
The following is in reply to the applicant’s submission (e.g. amendment, remarks, etc.) filed on May 18, 2026.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Election/Restrictions
Claims 9 through 20 continue to remain as being withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on January 21, 2026.
Specification
The objections to the specification in the previous office action1 have been withdrawn in light of the amendments to the abstract.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 5, it is unclear if the phrase of “defect in a pin” (line 3) is referring to the previous phrase of “pin defect” (line 11 of Claim 1). What is the difference between the two phrases? For purposes of examination, each phrase will be treated as the same defect.
Claim Rejections - 35 USC § 103
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Publication 2019/0280405 to Iwai et al (hereinafter “Iwai”) in view of U.S. Publication 2018/0177087 to Kito et al (hereinafter “Kito”).
Claim 1: Iwai discloses an apparatus (e.g. Fig. 1A) for manufacturing a computer system, the apparatus comprising:
a collaborative robot (e.g. 1, Fig. 1A) including an end effector (e.g. 101, Fig. 1A or 1B);
a camera (e.g. 20, Fig. 7A) operatively coupled to the collaborative robot;
a memory (e.g. 12, Fig. 2) coupled to the collaborative robot (e.g. inside of 10, Fig. 1A); and
processing circuitry (e.g. 10, Figs. 1A, 2, 6) coupled to the memory, the processing circuitry configured to:
receive image data [from camera 20] of a computer component (e.g. 190, Fig. 6) having a plurality of pins (e.g. 190e, 190f), the image data collected by the camera operatively coupled to the collaborative robot (e.g. ¶ [0064]);
compare the image data of the computer component to a stored pin configuration (e.g. 199e, 199f of dummy 199) for the computer component (e.g. 190) to detect whether the computer component has a pin defect (e.g. ¶ [0050], [0064]);
determine, based on the image data when no pin defect is detected, a coordinate location (e.g. 700e, 700f, Fig. 6) for the computer component (e.g. ¶ [0066]); and
direct the collaborative robot to secure the computer component (e.g. 190) to a printed circuit board (PCB)(e.g. 700) using the end effector based on the coordinate location (e.g. ¶¶ [0066], [0067]).
Claim 2: Iwai discloses the apparatus for manufacturing of claim 1 wherein the collaborative robot in combination with the camera is configured to manufacture the computer system by securing the computer component (e.g. 190, Fig. 6) to the PCB (e.g. 700), the computer system including the PCB (e.g. ¶¶ [0064] to [0067]).
Although the term “defect” does not appear to be explicitly recited in Iwai, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that when no defect is detected, the entire goal of Iwai is to secure the pins of the computer component to the coordination location (holes 700e, 700f) of the PCB. Having a “pint defect” would certainly mean that the pins could not be secured to the coordinate location.
Alternatively, Kito teaches that a control unit (e.g. Fig. 8) can include as part of its algorithm (e.g. 104, 107, 108, etc.) when directing a computer component (e.g. 41) with pins (e.g. 45) to be mounted on PCBs (e.g. 43, Fig. 7), detecting defects in positioning. Kito discloses that pin defects are detected when there is a position deviation between the pins (e.g. 45) of the component and lands or holes on the PCB, such that when a defect occurs, the computer component is not placed on the PCB thus preventing any unreliable electrical connections (e.g. ¶¶ [0033], [0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Iwai by adding such an algorithm that detects defects in a pin, or pins, as taught by Kito, to thus prevent any unreliable electrical connections.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Iwai in view Kito, as applied to Claim 1, and further in view of U.S. Publication 2018/0331081 to Goh et al (hereinafter “Goh”).
Iwai, as modified by Kito, disclose the claimed apparatus as relied upon above in Claim 1, further including directing the collaborative robot to secure pins (e.g. 199e, 199f or 190e, 190f, Fig. 6) of the computer component (e.g. 199 or 190) to the PCB based on the image data (e.g. ¶ [0066]), the PCB configured as a server board (e.g. to serve computer components) where the collaborative robot is configured to secure to the PCB. Iwai does not mention that the computer components are vendor-sourced, i.e. vendor-sourced computer components.
Goh teaches that when manufacturing computer components with PCBs (e.g. Figs. 6A to 6C), the computer components can be vendor-sourced to allow different applications. In other words, by choosing computer components of different vendors, this allows for different PCB designs, hence different applications (e.g. ¶ [0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the component components of Iwai by allowing them to be chosen from different vendors (i.e. vendor-sourced computer components), as taught by Goh, to positively provide different PCB designs having a plurality of applications.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Iwai in view Kito, as applied to Claim 1, further in view of U.S. Publication 2021/0384661 to Coteus et al (hereinafter “Coteus”).
Iwai, as modified by Kito, disclose the claimed apparatus as relied upon above in Claim 1, further including that the computer component is a component having a pin configuration (e.g. 199e, 199f) stored in the memory (e.g. 12), and wherein to determine the coordinate location for the computer component comprises to determine the coordinate location (e.g. 700e, 700f, Fig. 6) based on the stored pin configuration.
While Iwai does mention that the computer component (e.g. 199, 190) is a capacitor, Iwai does not explicitly state that the computer component is a semiconductor memory socket component.
Coteus teaches that a variety of components can be directed to and assembled to a PCB, which can include capacitors, semiconductor memory sockets (DIMMs), inductors, etc., in manufacturing completed circuits for PCBs (e.g. ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the computer component of Iwai by utilizing it as semiconductor memory socket component, as taught by Coteus, in providing a complete PCB circuit that includes a variety of electrical components.
Claim 5, as best understood, is rejected under 35 U.S.C. 103 as being unpatentable over Iwai in view of Kito and Coteus, as applied to Claims 1 and 4 above, and further in view of U.S. Publication 2022/0101511 to Entman (hereinafter “Entman”).
Iwai, as modified by Kito and Coteus, disclose the claimed apparatus as relied upon above in Claims 1 and 4, further including that the image data comprises 3D image data and that the processing circuitry is configured to detect the in the pin. The modified Iwai apparatus does not mention any pixel resolution.
Entman teaches that a camera (e.g. 360, Fig. 7) capturing an image of workpieces (e.g. 320) in general can have a resolution of greater than 1 megapixel at 0.0053 mm per pixel (5.3 microns per pixel), which falls within the claimed range of a minimum of 64 megapixels with 0.0025 mm per pixel (e.g. ¶ [0109]). This resolution of the camera of Entman provides increased precision of subsequent operations (e.g. ¶ [0001]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the camera of Iwai by utilizing the high resolution taught by Entman, to provide increased precision when directing the computer component to the PCB.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Iwai in view of Kito, as applied to Claim 1, and further in view of U.S. Publication 2020/0212010 to Kinsley et al (hereinafter “Kinsley”).
Claim 6: Iwai, as modified by Kito, disclose the claimed apparatus as relied upon above in Claim 1, further including that the processing circuitry is configured to direct the collaborative robot to insert a plurality of pins into the PCB (e.g. Fig. 6) using the end effector, the pins configured to receive a component module.
Claim 7: Iwai, as modified by Kito, further teaches that the processing circuitry is configured to direct the collaborative robot to lift and insert the computer component into each of the openings of the PCB (e.g. Fig. 6), each of the openings configured to hold the computer components.
The modified Iwai apparatus does not teach that the pins are sockets and that the component module is specifically a semiconductor in-line memory module (DIMMs).
Kinsley teaches that PCBs (e.g. 270, Fig. 2B) can have a plurality of sockets (e.g. 273, 274) inserted within it to receive semiconductor in-line memory modules (DIMMs) (e.g. ¶ [0018]). Such a connection provides additional semiconductor applications (e.g. clock signaling, highly dense integrated circuitry, etc. ¶¶ [0003], [0009]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have substituted the openings and computer component of Iwai, for the sockets and DIMMs, respectively, taught by Kinsley, when directing the collaborative robot to lift and insert, to thereby provide additional semiconductor applications that include PCBs.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Iwai in view Kito.
Iwai discloses the claimed apparatus as relied upon above in Claim 1. Iwai does not teach direct inspection of the computer component for socket pin defects based on the image data.
To reiterate (from Claim 5 above), Kito teaches that a control unit (e.g. Fig. 8) can include as part of its algorithm (e.g. 104, 107, 108, etc.) when directing a computer component (e.g. 41) with pins (e.g. 45) to be mounted on PCBs (e.g. 43, Fig. 7), detecting defects in positioning. Kito discloses that as part of its camera, defects are detected from imaging when there is a position deviation between the pins (e.g. 45) of the component and lands or holes on the PCB (i.e. socket pin defects), such that when a defect occurs, the computer component is not placed on the PCB thus preventing any unreliable electrical connections (e.g. ¶¶ [0033], [0041]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the apparatus of Iwai by adding such an algorithm that detects defects in a pin thus providing direct inspection for socket pin defects, as taught by Kito, to positively prevent any unreliable electrical connections.
Response to Arguments
Applicant's arguments filed as part of their submission have been fully considered, but have not been deemed to be found as persuasive.
In regards to the merits of Iwai, applicant urges that Iwai does not teach “compare the image data…for the computer component” (lines 9-13 of Claim 1).
The examiner disagrees. In Iwai, it appears that the applicant has overlooked the use of a dummy computer component (199, Fig. 6) and the use its pins (199e, 199f) as a “stored pin configuration”. Iwai uses this stored pin configuration (of 199e, 199f) at the coordination location (700e, 700f) such that the image data (from camera) from this stored pin configuration can be used to secure the “plurality of pins” (190e, 190f) of the actual computer component (190) to the coordinate location of the PCB with the collaborative robot (e.g. P12, Fig. 6, ¶ [0064] to [0067]). As stated in the above rejection, whether or not Iwai has a “pin defect” can be based on whether or not the pins (190e, 190f) can be secured to the coordinate location. Alternatively, if applicant believes that the reference has to explicitly mention the term of a “defect”, the such a teaching of what may be considered to be a “pin defect” is disclosed by Kito. Therefore, Iwai alone, or in combination with Kito, disclose the limitations in question (e.g. “compare…component”, lines 9-13 of Claim 1) for all of the foregoing reasons.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., defects of sunken pins, or a known pin configuration for a given hardware) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
With respect to Claims 2 through 8, the applicants arguments stand or fall together with Claim 1.
Conclusion
Applicant's amendment filed as part of the submission has necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to A. DEXTER TUGBANG whose telephone number is (571)272-4570. The examiner can normally be reached Mon - Fri 8:00 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, THOMAS J. HONG can be reached at 571-272-0993. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A. DEXTER TUGBANG/Primary Examiner
Art Unit 3729
1 Non-Final action, mailed on February 18, 2026.
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