DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 25, 2026 has been entered. Claims 1-20 remain pending in the application.
Response to Arguments
Applicant's arguments filed June 25, 2026 have been fully considered but they are not persuasive.
Applicant argues that the combination of incorporating previously presented prior art reference Shimamune (Patent Number US 10,050,592 B2), hereafter referred to as Shimamune, into the circuit of previously presented prior art reference Shao (Patent Publication Number CN 114,637,366 A), hereafter referred to as Shao, is not obvious because Shimamune is not in the field of detection circuits. Examiner respectfully disagrees.
Applicant states that Shimamune does not include the word “detect”, and that therefore, Shimamune does not refer to detection circuits. However, merely showing a lack of a specific term does not counteract the disclosed function of a reference. In response to applicant's argument that Shimamune is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Shimamune is in the field of detection circuits, as Shimamune discloses an operational amplifier based circuit that outputs a controlled voltage by detecting the output of the circuit with a feedback loop to compare the output voltage with a predetermined reference voltage (Shimamune, Col. 2, lines 52-64). In other words, signal detection is a fundamental part of the operation of the circuit of Shimamune. Therefore, the circuit of Shimamune is a detection circuit and therefore, applicant’s argument is unconvincing and the rejections of claims 1-8 and 19-20 are maintained.
Applicant further argues that the combination of Shao and Ishida et al. (Patent Publication Number US 2019/0066938 A1), hereafter referred to as Ishida, to include the biasing circuit of Ishida in the system of Shao does not have sufficient motivation to combine and that the combination would destroy the functionality of Shao. Examiner respectfully disagrees.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, including the biasing circuit of Ishida in the system of Shao would have the effect of providing a controllable bias current to the amplifier of Shao. The controllable bias current would enable providing different bias levels to properly account for differences in circuit components in specific implementations of the proposed circuit to increase the reliability of the circuit (Ishida, Paragraph 59, lines 1-6). For the circuit of Shao, this could be differences in the external resistor having its resistance being detected. Therefore, there is sufficient motivation to include a controllable bias circuit in the system of Shao.
Furthermore, regarding applicant’s statement that the examiner has not explained how the modifications to Shao could be made without destroying the function of the system of Shao, examiner notes that as explained above, the modifications proposed to incorporate Ishida in the system of Shao have sufficient rationale to establish a prima facie case of obviousness. Therefore, it is the applicant’s burden to provide sufficient evidence to counteract the rejection of the examiner. Applicant’s assertion that the proposed modification would destroy the function of the system of Shao lacks any supporting evidence, and therefore applicant's arguments fail to comply with 37 CFR 1.111(b) because they amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Therefore, applicant’s argument is unconvincing and the rejections of claims 1-8 and 19-20 are maintained.
Applicant further argues that the amendments to independent claims 9 and 15 render claims 9-18 allowable because the cited references supposedly fail to disclose “a second transistor including a control terminal coupled to the feedback path, and a second terminal coupled to a detector output terminal and configured to provide an output current with a magnitude corresponding to a magnitude of a resistance at the detector output terminal” (for claims 9-14) and “a second transistor including a control terminal coupled to the feedback path, and a second terminal coupled to the system output” (for claims 15-18). However, Shao includes a transistor 4 (see Shao, Fig. 3) that corresponds to this claimed second transistor (see detailed claim mapping below). Therefore, applicant’s argument is unconvincing and the rejections of claims 9-18 are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 9-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The amendment to claim 9 includes “an output current with a magnitude corresponding to a magnitude of a resistance at the detector output terminal”. This limitation is new matter because the original claims, specification, and drawings do not describe in any fashion “a resistance at the detector output terminal”. As understood by the examiner, the output current corresponds to the resistance at the input of the detector, specifically the resistance of the external reference resistor, that is described as being situated at the input of the detector (see instant application Fig. 1, with external reference resistor REXT coupled to the input 124 of the external resistor detector 104). Therefore, the original claims, specification, and drawings do not provide support for the amendment to claim 9. Claims 10-14 are likewise rejected under this logic by virtue of their dependency on claim 9.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “an output current with a magnitude corresponding to a magnitude of a resistance at the detector output terminal”. This limitation is indefinite because the specification and drawings only refer to a resistance at the input terminal of the detector (see instant application Fig. 1, with external reference resistor REXT coupled to the input 124 of the external resistor detector 104). Therefore, it is unclear whether claim 9 refers to a resistance at the input terminal or the output terminal of the detector. Amending the limitation to refer to a resistance at the input terminal of the detector is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 10-14 are likewise rejected under this logic by virtue of their dependency on claim 9.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Ishida, Chen et al. (Patent Publication Number CN 113,252,974 A), hereafter referred to as Chen, and Shimamune.
Regarding claim 1, Shao discloses:
A system (Shao, Fig. 3) comprising: a system input (Fig. 3, Vx); a system output (Fig. 3, Vout3); an operational amplifier (Fig. 3, 1) comprising: a first amplifier signal input (Fig. 3, see positive input of 1) coupled to the system input (Fig. 3, see connection between positive input of 1 and Vx); a second amplifier signal input (Fig. 3, see negative input of 1); and an amplifier output (Fig. 3, see output of 1); but fails to disclose a first switch including a first terminal and including a second terminal coupled to the first amplifier signal input; a second switch including a first terminal coupled to the first amplifier signal input and a second terminal coupled to the second amplifier signal input; a first bias current source coupled between the first amplifier signal input and a common potential; a second bias current source coupled between the first terminal of the first switch and the common potential; a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.
However, Ishida teaches a first switch (Ishida, Fig. 8, S1L) including a first terminal (Fig. 8, see bottom terminal of S1L) and including a second terminal (Fig. 8, see top terminal of S1L) coupled to the first amplifier signal input (Fig. 8, see connection between S1L and positive input of amplifier COMP1); a first bias current source (Fig. 8, CC1) coupled between the first amplifier signal input and a common potential (Fig. 8, see connection between positive input of amplifier COMP1 and ground via CC1); a second bias current source (Fig. 8, iC1L) coupled between the first terminal of the first switch and the common potential (Fig. 8, see connection between S1L and ground via iC1L); but fails to teach a second switch including a first terminal coupled to the first amplifier signal input and a second terminal coupled to the second amplifier signal input; a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.
However, Chen teaches a second switch (Chen, Fig. 1, Q1) including a first terminal coupled to the first amplifier signal input (Fig. 1, see connection between Q1 and positive input of 102) and a second terminal coupled to the second amplifier signal input (Fig. 1, see connection between Q1 and negative input of 102); but fails to teach a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.
However, Shimamune teaches a third switch (Shimamune, Fig. 7, SW1) including a first terminal coupled to the amplifier output (Fig. 7, see connection between SW1 and output of amplifier OP) and including a second terminal (Fig. 7, see connection between SW1 and MN1); a first transistor (Fig. 7, MN1) including a first current terminal (Fig. 7, see drain of MN1), a second current terminal coupled to the common potential (Fig. 7, see source of MN1 and its connection to ground), and a control terminal coupled to the second terminal of the third switch (Fig. 7, see connection between gate of MN1 and SW1); and a fourth switch (Fig. 7, SW2) including a first terminal coupled to the system input (Fig. 7, see connection between SW2 and input of amplifier OP) and a second terminal coupled to the first current terminal of the first transistor (Fig. 7, see connection between SW2 and drain of MN1).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Ishida, Chen, and Shimamune to include the biasing circuit of Ishida in the system of Shao, which would have the effect of providing a controllable bias current to the operational amplifier of Shao (Ishida, Paragraph 122, lines 1-8), to include the switch of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 6, Paragraph 4, lines 1-3), and to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 2, Shao fails to disclose:
further comprising a first capacitor coupled between the second amplifier signal input and the common potential.
However, Chen further teaches further comprising a first capacitor (Chen, Fig. 1, Cout) coupled between the second amplifier signal input and the common potential (Fig. 1, see connection between Cout, ground, and negative input of amplifier 102).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Chen to include the capacitor of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 6, Paragraph 4, lines 1-3 and 15-19).
Regarding claim 3, Shao fails to disclose:
further comprising a second capacitor coupled between the control terminal of the first transistor and the common potential.
However, Chen further teaches further comprising a second capacitor (Chen, Fig. 1, C0) coupled between the control terminal of the first transistor (Fig. 1, see connection between C0 and output of amplifier 102, consider the combination of Shao in view of Shimamune as described above, and that the output of the operational amplifier is coupled to the gate of the first transistor) and the common potential (Fig. 1, see connection between C0 and ground).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Chen to include the capacitor of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 2, Paragraph 2, lines 10-12).
Regarding claim 4, Shao fails to disclose:
further comprising a second transistor including a first current terminal coupled to the system output, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch.
However, Shimamune further teaches further comprising a second transistor (Shimamune, Fig. 7, MN2) including a first current terminal (Fig. 7, see drain of MN2) coupled to the system output (Fig. 7, see connection between drain of MN2 and Vout2), a second current terminal (Fig. 7, see source of MN2) coupled to the common potential (Fig. 7, see connection between source of MN2 and ground), and a control terminal (Fig. 7, see gate of MN2) coupled to the second terminal of the third switch (Fig. 7, see connection between gate of MN2 and SW1).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 5, Shao fails to disclose:
further comprising a first resistor coupled between the system input and the first amplifier signal input.
However, Shimamune further teaches further comprising a first resistor (Shimamune, Fig. 3, R1) coupled between the system input and the first amplifier signal input (Fig. 3, consider connection between positive input of amplifier OP and output of amplifier OP via resistor R1, and connection between positive input of amplifier 1 of Shao, Fig. 3 and output of amplifier 1 of Shao, Fig. 3 to system input Vx, and how the combination of resistor R1 of Shimamune, Fig. 3 in the circuit of Shao would couple between the positive input of amplifier 1 and system input Vx in Shao, Fig. 3).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 6, Shao discloses:
A circuit (Shao, Fig. 3), comprising: an operational amplifier (Fig. 3, 1) including a first amplifier signal input (Fig. 3, see positive input of 1) coupled to a first circuit input (Fig. 3, see connection between positive input of 1 and REXT) and including a second amplifier signal input (Fig. 3, see negative input of 1) and an amplifier output (Fig. 3, see output of 1); but fails to disclose a first switch including a first terminal and including a second terminal coupled to the first amplifier signal input; a second switch including a first terminal coupled to the first amplifier signal input and a second terminal coupled to the second amplifier signal input; a first bias current source coupled between the first amplifier signal input and a common potential; a second bias current source coupled between the first terminal of the first switch and the common potential; a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor; a first capacitor coupled between the second amplifier signal input and the common potential; and a second capacitor coupled between the control terminal of the first transistor and the common potential.
However, Ishida teaches a first switch (Ishida, Fig. 8, S1L) including a first terminal (Fig. 8, see bottom terminal of S1L) and including a second terminal (Fig. 8, see top terminal of S1L) coupled to the first amplifier signal input (Fig. 8, see connection between S1L and positive input of amplifier COMP1); a first bias current source (Fig. 8, CC1) coupled between the first amplifier signal input and a common potential (Fig. 8, see connection between positive input of amplifier COMP1 and ground via CC1); a second bias current source (Fig. 8, iC1L) coupled between the first terminal of the first switch and the common potential (Fig. 8, see connection between S1L and ground via iC1L); but fails to teach a second switch including a first terminal coupled to the first amplifier signal input and a second terminal coupled to the second amplifier signal input; a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor; a first capacitor coupled between the second amplifier signal input and the common potential; and a second capacitor coupled between the control terminal of the first transistor and the common potential.
However, Chen teaches a second switch (Chen, Fig. 1, Q1) including a first terminal coupled to the first amplifier signal input (Fig. 1, see connection between Q1 and positive input of 102) and a second terminal coupled to the second amplifier signal input (Fig. 1, see connection between Q1 and negative input of 102); a first capacitor (Fig. 1, Cout) coupled between the second amplifier signal input and the common potential (Fig. 1, see connection between Cout, ground, and negative input of amplifier 102); and a second capacitor (Fig. 1, C0) coupled between the control terminal of the first transistor (Fig. 1, see connection between C0 and output of amplifier 102, consider the combination of Shao in view of Shimamune as described above, and that the output of the operational amplifier is coupled to the gate of the first transistor) and the common potential (Fig. 1, see connection between C0 and ground), but fails to teach a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.
However, Shimamune teaches a third switch (Shimamune, Fig. 7, SW1) including a first terminal coupled to the amplifier output (Fig. 7, see connection between SW1 and output of amplifier OP) and including a second terminal (Fig. 7, see connection between SW1 and MN1); a first transistor (Fig. 7, MN1) including a first current terminal (Fig. 7, see drain of MN1), a second current terminal coupled to the common potential (Fig. 7, see source of MN1 and its connection to ground), and a control terminal coupled to the second terminal of the third switch (Fig. 7, see connection between gate of MN1 and SW1); a fourth switch (Fig. 7, SW2) including a first terminal coupled to the system input (Fig. 7, see connection between SW2 and input of amplifier OP) and a second terminal coupled to the first current terminal of the first transistor (Fig. 7, see connection between SW2 and drain of MN1).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Ishida, Chen, and Shimamune to include the biasing circuit of Ishida in the system of Shao, which would have the effect of providing a controllable bias current to the operational amplifier of Shao (Ishida, Paragraph 122, lines 1-8), to include the switch and capacitors of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 2, Paragraph 2, lines 10-12 and Page 6, Paragraph 4, lines 1-3 and 15-19), and to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 7, Shao fails to disclose:
further comprising a second transistor including a first current terminal coupled to a system output, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch.
However, Shimamune further teaches further comprising a second transistor (Shimamune, Fig. 7, MN2) including a first current terminal (Fig. 7, see drain of MN2) coupled to a system output (Fig. 7, see connection between drain of MN2 and Vout2), a second current terminal (Fig. 7, see source of MN2) coupled to the common potential (Fig. 7, see connection between source of MN2 and ground), and a control terminal (Fig. 7, see gate of MN2) coupled to the second terminal of the third switch (Fig. 7, see connection between gate of MN2 and SW1).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 8, Shao fails to disclose:
further comprising a first resistor coupled between the external resistor and the first amplifier input.
However, Shimamune further teaches further comprising a first resistor (Shimamune, Fig. 3, R1) coupled between the first circuit input and the first amplifier input (Fig. 3, consider connection between positive input of amplifier OP and output of amplifier OP via resistor R1, and connection between positive input of amplifier 1 of Shao, Fig. 3 and output of amplifier 1 of Shao, Fig. 3 to system input Vx, and how the combination of resistor R1 of Shimamune, Fig. 3 in the circuit of Shao would couple between the positive input of amplifier 1 and system input Vx in Shao, Fig. 3).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 19, Shao further discloses:
wherein the first amplifier signal input is a non-inverting input of the operational amplifier (Shao, Fig. 3, see positive input of 1) and the second amplifier signal input is an inverting input of the operational amplifier (Fig. 3, see negative input of 1).
Regarding claim 20, Shao further discloses:
wherein the system output supplies a current indicative of a resistance of an external resistor coupled to the system input (Shao, Page 6, last paragraph, lines 1-5).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Chen.
having an external terminal (Fig. 3, Vx) adapted to be coupled to an external physical resistor (Fig. 3, REXT), the circuit
Regarding claim 9, Shao discloses:
A circuit (Shao, Fig. 3) comprising: an external terminal (Fig. 3 Vx); an operational amplifier (Fig. 3, 1) including a first amplifier signal input (Fig. 3, see positive input of 1) coupled to the external terminal (Fig. 3, see connection between positive input of 1 and Vx) and including a second amplifier signal input (Fig. 3, see negative input of 1) and an amplifier output (Fig. 3, see output of 1); a feedback path (Fig. 3, see path from output of 1 through transistor 3 to positive input of 1) including a first terminal coupled to the amplifier output (Fig. 3, see path from output of 1 through transistor 3 to positive input of 1 and note output of 1) and a second terminal coupled to the external terminal (Fig. 3, see path from output of 1 through transistor 3 to positive input of 1 and note terminal Vx), a second transistor (Fig. 3, see transistor 4) including a control terminal coupled to the feedback path (Fig. 3, see connection between gate of transistor 4 and output of amplifier 1), and a first current terminal coupled to a detector output terminal (Fig. 3, consider drain terminal of transistor 4) and configured to provide an output current (Page 6, last paragraph, lines 1-5) with a magnitude corresponding to a magnitude of a resistance at the detector output terminal (Page 7, Paragraph 1, lines 1-2 and Paragraph 3, lines 2-4), but fails to disclose a first capacitor coupled between the second amplifier signal input and a common potential.
However, Chen teaches a first capacitor (Chen, Fig. 1, Cout) coupled between the second amplifier input and the common potential (Fig. 1, see connection between Cout, ground, and negative input of amplifier 102).
Shao and Chen are both considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Chen to include the capacitor of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 6, Paragraph 4, lines 1-3 and 15-19).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Chen as applied to claim 9 above, and further in view of Ishida.
Regarding claim 10, Shao fails to disclose:
further comprising: a first switch including a first terminal and including a second terminal coupled to the first amplifier signal input; a second switch including a first terminal coupled to the first amplifier signal input and a second terminal coupled to the second amplifier signal input; a first bias current source coupled between the first amplifier signal input and the common potential; and a second bias current source coupled between the first terminal of the first switch and the common potential.
However, Chen further teaches a second switch (Chen, Fig. 1, Q1) including a first terminal coupled to the first amplifier signal input (Fig. 1, see connection between Q1 and positive input of 102) and a second terminal coupled to the second amplifier signal input (Fig. 1, see connection between Q1 and negative input of 102); but fails to teach a first switch including a first terminal and including a second terminal coupled to the first amplifier signal input; a first bias current source coupled between the first amplifier signal input and the common potential; and a second bias current source coupled between the first terminal of the first switch and the common potential.
However, Ishida teaches a first switch (Ishida, Fig. 8, S1L) including a first terminal (Fig. 8, see bottom terminal of S1L) and including a second terminal (Fig. 8, see top terminal of S1L) coupled to the first amplifier signal input (Fig. 8, see connection between S1L and positive input of amplifier COMP1); a first bias current source (Fig. 8, CC1) coupled between the first amplifier signal input and a common potential (Fig. 8, see connection between positive input of amplifier COMP1 and ground via CC1); a second bias current source (Fig. 8, iC1L) coupled between the first terminal of the first switch and the common potential (Fig. 8, see connection between S1L and ground via iC1L).
Shao, Chen, and Ishida are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Chen and Ishida to include the switch of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 6, Paragraph 4, lines 1-3), and to include the biasing circuit of Ishida in the system of Shao, which would have the effect of providing a controllable bias current to the operational amplifier of Shao (Ishida, Paragraph 122, lines 1-8).
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Chen as applied to claim 9 above, and further in view of Shimamune.
Regarding claim 11, Shao and Chen fail to disclose:
wherein the feedback path comprises: a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the external terminal and a second terminal coupled to the first current terminal of the first transistor.
However, Shimamune teaches wherein the feedback path comprises: a third switch (Shimamune, Fig. 7, SW1) including a first terminal coupled to the amplifier output (Fig. 7, see connection between SW1 and output of amplifier OP) and including a second terminal (Fig. 7, see connection between SW1 and MN1); a first transistor (Fig. 7, MN1) including a first current terminal (Fig. 7, see drain of MN1), a second current terminal coupled to the common potential (Fig. 7, see source of MN1 and its connection to ground), and a control terminal coupled to the second terminal of the third switch (Fig. 7, see connection between gate of MN1 and SW1); and a fourth switch (Fig. 7, SW2) including a first terminal coupled to the system input (Fig. 7, see connection between SW2 and input of amplifier OP) and a second terminal coupled to the first current terminal of the first transistor (Fig. 7, see connection between SW2 and drain of MN1).
Shao, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 12, Shao fails to disclose:
further comprising a second capacitor coupled between the control terminal of the first transistor and the common potential.
However, Chen further teaches further comprising a second capacitor (Chen, Fig. 1, C0) coupled between the control terminal of the first transistor (Fig. 1, see connection between C0 and output of amplifier 102, consider the combination of Shao in view of Shimamune as described above, and that the output of the operational amplifier is coupled to the gate of the first transistor) and the common potential (Fig. 1, see connection between C0 and ground).
Shao, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Chen to include the capacitor of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 2, Paragraph 2, lines 10-12).
Regarding claim 13, Shao and Chen fail to disclose:
wherein the second current terminal of the second transistor is coupled to the common potential, and the control terminal of the second transistor is coupled to the second terminal of the third switch.
However, Shimamune further teaches wherein the second current terminal of the second transistor is coupled to the common potential (Shimamune, Fig. 7, consider connection between source of MN2 and ground), and the control terminal of the second transistor is coupled to the second terminal of the third switch (Fig. 7, consider connection between gate of MN2 and SW1)
Shao, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 14, Shao and Chen fail to disclose:
further comprising a first resistor coupled between the external terminal and the first amplifier signal input.
However, Shimamune further teaches further comprising a first resistor (Shimamune, Fig. 3, R1) coupled between the external terminal and the first amplifier signal input (Fig. 3, consider connection between positive input of amplifier OP and output of amplifier OP via resistor R1, and connection between positive input of amplifier 1 of Shao, Fig. 3 and output of amplifier 1 of Shao, Fig. 3 to system input Vx, and how the combination of resistor R1 of Shimamune, Fig. 3 in the circuit of Shao would couple between the positive input of amplifier 1 and system input Vx in Shao, Fig. 3).
Shao, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Claims 15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Ishida and Chen.
Regarding claim 15, Shao discloses:
A system (Shao, Fig. 3) comprising: a system input (Fig. 3, Vx); a system output (Fig. 3, Vout3); an operational amplifier (Fig. 3, 1) comprising: a first amplifier signal input (Fig. 3, see positive input of 1) coupled to the system input (Fig. 3, see connection between positive input of 1 and Vx); a second amplifier signal input (Fig. 3, see negative input of 1); and an amplifier output (Fig. 3, see output of 1), wherein the amplifier output is an amplification of a difference between the first amplifier signal input and the second amplifier signal input (Page 6, Paragraph 12, lines 1-3); and a feedback path (Fig. 3, see path from output of 1 through transistor 3 to positive input of 1) including a first terminal coupled to the amplifier output (Fig. 3, see path from output of 1 through transistor 3 to positive input of 1 and note output of 1) and a second terminal coupled to the system input (Fig. 3, see path from output of 1 through transistor 3 to positive input of 1 and note terminal Vx); and a second transistor (Fig. 3, see transistor 4) including a control terminal coupled to the feedback path (Fig. 3, see connection between gate of transistor 4 and output of amplifier 1), and a second terminal coupled to the system output (Fig. 3, consider drain of transistor 4), but fails to disclose a first switch including a first terminal and including a second terminal coupled to the first amplifier signal input; a second switch including a first terminal coupled to the first amplifier signal input and a second terminal coupled to the second amplifier signal input; a first bias current source coupled between the first amplifier signal input and a common potential; a second bias current source coupled between the first terminal of the first switch and the common potential.
However, Ishida teaches a first switch (Ishida, Fig. 8, S1L) including a first terminal (Fig. 8, see bottom terminal of S1L) and including a second terminal (Fig. 8, see top terminal of S1L) coupled to the first amplifier signal input (Fig. 8, see connection between S1L and positive input of amplifier COMP1); a first bias current source (Fig. 8, CC1) coupled between the first amplifier signal input and a common potential (Fig. 8, see connection between positive input of amplifier COMP1 and ground via CC1); a second bias current source (Fig. 8, iC1L) coupled between the first terminal of the first switch and the common potential (Fig. 8, see connection between S1L and ground via iC1L), but fails to teach a second switch including a first terminal coupled to the first amplifier signal input and a second terminal coupled to the second amplifier signal input.
However, Chen teaches a second switch (Chen, Fig. 1, Q1) including a first terminal coupled to the first amplifier signal input (Fig. 1, see connection between Q1 and positive input of 102) and a second terminal coupled to the second amplifier signal input (Fig. 1, see connection between Q1 and negative input of 102).
Shao, Ishida, and Chen are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Ishida and Chen to include the biasing circuit of Ishida in the system of Shao, which would have the effect of providing a controllable bias current to the operational amplifier of Shao (Ishida, Paragraph 122, lines 1-8) and to include the switch of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 6, Paragraph 4, lines 1-3).
Regarding claim 17, Shao fails to disclose:
further comprising a first capacitor coupled between the second amplifier input and the common potential.
However, Chen further teaches further comprising a first capacitor (Chen, Fig. 1, Cout) coupled between the second amplifier input and the common potential (Fig. 1, see connection between Cout, ground, and negative input of amplifier 102).
Shao, Ishida, and Chen are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Chen to include the capacitor of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 6, Paragraph 4, lines 1-3 and 15-19).
Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Ishida and Chen as applied to claim 15 above, and further in view of Shimamune.
Regarding claim 16, Shao, Ishida, and Chen fail to disclose:
wherein the feedback path comprises: a third switch including a first terminal coupled to the amplifier output and including a second terminal; a first transistor including a first current terminal, a second current terminal coupled to the common potential, and a control terminal coupled to the second terminal of the third switch; and a fourth switch including a first terminal coupled to the system input and a second terminal coupled to the first current terminal of the first transistor.
However, Shimamune teaches wherein the feedback path comprises: a third switch (Shimamune, Fig. 7, SW1) including a first terminal coupled to the amplifier output (Fig. 7, see connection between SW1 and output of amplifier OP) and including a second terminal (Fig. 7, see connection between SW1 and MN1); a first transistor (Fig. 7, MN1) including a first current terminal (Fig. 7, see drain of MN1), a second current terminal coupled to the common potential (Fig. 7, see source of MN1 and its connection to ground), and a control terminal coupled to the second terminal of the third switch (Fig. 7, see connection between gate of MN1 and SW1); and a fourth switch (Fig. 7, SW2) including a first terminal coupled to the system input (Fig. 7, see connection between SW2 and input of amplifier OP) and a second terminal coupled to the first current terminal of the first transistor (Fig. 7, see connection between SW2 and drain of MN1).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Shimamune to include the output and feedback loop of Shimamune in the system of Shao, which would have the effect of providing a stable output current (Shimamune, Col. 1, lines 36-39).
Regarding claim 18, Shao fails to disclose:
further comprising a second capacitor coupled between the control terminal of the first transistor and the common potential.
However, Chen further teaches further comprising a second capacitor (Chen, Fig. 1, C0) coupled between the control terminal of the first transistor (Fig. 1, see connection between C0 and output of amplifier 102, consider the combination of Shao in view of Shimamune as described above, and that the output of the operational amplifier is coupled to the gate of the first transistor) and the common potential (Fig. 1, see connection between C0 and ground).
Shao, Ishida, Chen, and Shimamune are all considered to be analogous to the claimed invention because they are in the same field of improving detection circuits. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Shao to incorporate the teachings of Chen to include the capacitor of Chen in the system of Shao, which would have the effect of facilitating sampling periods to measure circuit parameters (Chen, Page 2, Paragraph 2, lines 10-12).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wang et al. (Patent Publication Number US 2022/0361304 A1) discloses (Fig. 9) a circuit for detecting the value of an external resistor and providing an output current accordingly.
Li et al. (Patent Publication Number CN 107,656,123 A) discloses (Fig. 3) a circuit for detecting the value of an external resistor.
Lechner et al. (Patent Publication Number EP 176,915 A) discloses (Fig. 1) an operational amplifier with a switch coupling its two inputs.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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