DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-25 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12, 14-25 are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US20210271595) hereinafter Chen in view of Adhikesvalu et al hereinafter (Adhik).
As to claim 1, Chen discloses a circuit board a server architecture, the circuit board including a plurality of input and output ports (I/O ports) and one or more processing circuitries coupled to the I/O ports, the one or more processors (Fig. 1 with a plurality of backboards such as 132a, 132b composing a server, and interconnected via a core NTB CKT comprises i/o ports to interconnect) to: access cable information pertaining to a cable coupled to one of the I/O ports (Fig. 2, and para. 0028);
And Chen does not explicitly disclose configure, based on the cable information, logic at a memory circuitry of the server architecture.
Adhik teaches configure, based on the cable information, logic at a memory circuitry of the server architecture (Fig. 2, and step 210, and para. 0032). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claims 2, 17, and 23, Adhik discloses the circuit board, wherein the cable information includes at least one of a cable part number, a cable version number, a cable serial number, a cable identification (ID), a cable type, a cable maximum bandwidth, a cable maximum frequency, a cable maximum speed of transmission, cable loss, one or more cable supported interconnect protocols, cable length, cable width, cable diameter, cable fiber bend radius, or an identification of one or more port protocols configurable to the cable (Fig. 3, and para. 0033, where memory details cable specifics). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claims 3, 18 and 24, Adhik discloses the circuit board, wherein configuring the logic includes configuring system integration (SI) settings at the memory circuitry to provide interoperability between the cable and the circuit board (Fig. 2, step 210, and para. 0038). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claims 4,19, and 25, Adhik discloses the circuit board, wherein the SI settings are second SI settings, and configuring the logic includes changing first SI settings stored at the memory circuitry to the second SI settings based on the cable information (Fig. 2, and memory that comprises multiple configurations, para. 0038). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claims 5, and 20, Adhik discloses the circuit board, the one or more processors to further detect a mismatch as between the cable and a circuit board that includes the memory circuitry, wherein the circuit board that includes the memory circuitry one of corresponds to the circuit board of the server architecture, or corresponds to another circuit board different from the circuit board of the server architecture (Fig. 5, step 510, where mismatch is detected, para. 0048). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claims 6,and 21, Adhik discloses the circuit board, wherein the one or more processors are to further cause generation and transmission of a report based on the mismatch (Fig. 5, and para. 0050). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claim 7, Adhik discloses the circuit board, wherein the memory circuitry is part of the circuit board (Fig. 5, and step 525, where the cable memory is defective, para. 0048). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claim 8, Adhik discloses the circuit board, wherein the circuit board is a first circuit board, and wherein the memory circuitry is part of a second circuit board of the server architecture (Fig. 5, and step 525, where the cable memory is defective, para. 0048). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claim 9, Chen discloses a server architecture including a motherboard, a circuit board, and a cable structure communicatively coupling the motherboard to the circuit board, (Fig. 1 with a plurality of board interconnected) wherein: the motherboard includes: a plurality of first input and output ports (I/O ports) and one or more processing circuitries coupled to the first I/O ports, the one or more processors (Fig. 2 illustrating plurality of interconnections, para. 0028) to:
Chen teaches access cable information pertaining to a cable of the cable structure (Fig.2, and para. 0032); and configure, based on the cable information, logic at a first memory circuitry ((Fig.2, and step 210); the cable structure includes a second memory circuitry storing the cable information; and the circuit board includes second I/O ports, the cable structure coupling the motherboard to the circuit board by way of the first I/O ports and the second I/O ports (Fig. 3, show the coupling of one board 305 to a plurality of boards such as 315-a or 315-b, and enabling a new configuration , step 410, para. 0033). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claim 10, Chen discloses the server architecture, wherein the first memory circuitry is part of the circuit board (Fig. 1 with network IF CKT132a, para. 0018).
As to claim 11, Chen discloses the server architecture, wherein the circuit board includes another motherboard, a fabric extender, or a backplane of the server architecture (Fig. 2, with circuit boards, para. 0048).
As to claim 12, Chen discloses the server architecture, wherein the motherboard includes a Baseboard Management Controller (BMC), and wherein the one or more processors are processing circuitries of the BMC (Fig. 2, with BMC 150a, para. 0048)
As to claim 14, Chen discloses the server architecture, wherein the logic at the first memory circuitry corresponds to an I/O port (Fig. 1 with network IF CKT132a, para. 0018).
As to claim 15, Chen discloses the server architecture, wherein the logic at the first memory circuitry corresponds to one of the first I/O ports (Fig. 1 with network IF CKT132a, para. 0018).
As to claim 16, Chen discloses a non-transitory computer-readable storage medium comprising instructions stored thereon, that when executed by one or more processing circuitries of a circuit board of a server architecture, cause the one or more processors to perform operations (Fig. 1 with circuit boards and a plurality of processors, para. 0018) including:
Adhik teaches accessing cable information pertaining to a cable of the server architecture (Fig. 2, and step 205, para. 0032); and configuring, based on the cable information, logic at a memory circuitry of the server architecture (Fig. 2, and step 210, and para. 0032). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
As to claim 22, Chen discloses a method to be performed at one or more processors of a circuit board of a server architecture, cause the one or more processors to perform instructions (Fig. 1 with circuit boards and a plurality of processors, para. 0018) including:
Adhik teaches accessing cable information pertaining to a cable of the server architecture (Fig. 2, and step 205, para. 0032); and configuring, based on the cable information, logic at a memory circuitry of the server architecture (Fig. 2, and step 210, and para. 0032). One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the flexible cable system of Adhik in the system of Chen to change out system needs on the fly and avoid manual intervention, (para. 0009).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen/Adhik as applied to claim 9 above, and further in view of Yu et al (US11462872), hereinafter Yu.
As to claim 13, Chen/Adhik does not explicitly the server architecture, wherein the logic at the first memory circuitry corresponds to a re-timer device of the server architecture.
Yu teaches wherein the logic at the first memory circuitry corresponds to a re-timer device of the server architecture (Fig.2, and module 182, para. 0032). One of ordinary skill in the art before the effective date of the claimed invention would have been motived to use Yu in the system of Chen/Adhik to support multiple connector type at the same connection port, para. 0010).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20170111215, US7356433, and US9531596, among other teach the management of cable types in a server system.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184