DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1- 25 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 7, 8, 16, 22, and 23 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Steward et al (US20150289405) hereinafter Steward.
As to claim 1, Steward discloses a circuit board with server architecture, the circuit board including a plurality of input and output ports (I/O ports) and one or more processing circuitries coupled to the I/O ports, (Fig. 12 comprising of a plurality of boards coupled by cables, para. 0155, and I/O ports Fig. 13, para. 0156) the one or more processors to:
Steward also teaches access cable information pertaining to a cable coupled to one of the I/O ports (Fig. 1 illustrates the interconnect topology between the frame control center and each frame unit, para. 0012. Fig. 3, and para. 0102 teaches the exchange of cable information); and configure, based on the cable information, logic at a memory circuitry of the server architecture (Fig. 6, and para. 0103 where the operational signal is used to configure local frame unit).
As to claims 2, 17, and 23, Steward discloses the circuit board, wherein the cable information includes at least one of a cable part number, a cable version number, a cable serial number, a cable identification (ID), a cable type, a cable maximum bandwidth, a cable maximum frequency, a cable maximum speed of transmission, cable loss, one or more cable supported interconnect protocols, cable length, cable width, cable diameter, cable fiber bend radius, or an identification of one or more port protocols configurable to the cable (Fig. 1, and para. 013).
As to claim 7, Steward discloses the circuit board, wherein the memory circuitry is part of the circuit board (Fig. 1, and para. 0010, where the frame unit is a circuit board).
As to claim 8, Steward discloses the circuit board, wherein the circuit board is a first circuit board, and wherein the memory circuitry is part of a second circuit board of the server architecture (Fig. 1, with memory 136 in sub frame 176, para. 0124).
As to claim 16, Steward discloses a non-transitory computer-readable storage medium comprising instructions stored thereon, that when executed by one or more processing circuitries of a circuit board of a server architecture (Fig. 12 comprising of a plurality of boards coupled by cables, para. 0155, and I/O ports Fig. 13, para. 0156), cause the one or more processors to perform operations including: accessing cable information pertaining to a cable of the server architecture (Fig. 1 illustrates the interconnect topology between the frame control center and each frame unit, para. 0012. Fig. 3, and para. 0102 teaches the exchange of cable information); and configuring, based on cable information, logic at a memory circuitry of the server architecture (Fig. 6, and para. 0103 where the operational signal is used to configure local frame unit).
As to claim 22, Steward discloses a method to be performed at one or more processors of a circuit board of a server architecture, cause the one or more processors to perform instructions including: accessing cable information pertaining to a cable of the server architecture (Fig. 12 comprising of a plurality of boards coupled by cables, para. 0155, and I/O ports Fig. 13, para. 0156). Steward also teaches access cable information pertaining to a cable coupled to one of the I/O ports (Fig. 1 illustrates the interconnect topology between the frame control center and each frame unit, para. 0012. Fig. 3, and para. 0102 teaches the exchange of cable information; and configuring, based on the cable information, logic at a memory circuitry of the server architecture (Fig. 6, and para. 0103 where the operational signal is used to configure local frame unit).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-11, 14, 15, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Steward et al (US20150289405) hereinafter Steward in view of Smith et al (US20160062939) hereinafter Smith.
As to claim 9, Steward discloses a server architecture including a motherboard, a circuit board, and a cable structure communicatively coupling the motherboard to the circuit board, (Fig. 12 comprising of a plurality of boards coupled by cables, para. 0155) wherein: the motherboard includes: a plurality of first input and output ports (I/O ports) and one or more processing circuitries coupled to the first I/O ports, the one or more processors to: access cable information pertaining to a cable of the cable structure (Fig. 13, para. 0156); and configure, based on the cable information, logic at a first memory circuitry (Fig. 1, and FRU 172, with memory 158, and para 0070);
and Steward discloses the circuit board includes second I/O ports, the cable structure coupling the motherboard to the circuit board by way of the first I/O ports and the second I/O ports (Fig. 1, and I/O ports on frame subcircuits such as 176, comprising memory such as 136, para. 0124).
Smith teaches the cable structure includes a second memory circuitry storing the cable information (Fig. 3, and para. 0034). One of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use the cable capability of Smith in the system of Steward to couple the system’s sub systems to gain the programming flexibility of this cable, (para. 0009).
As to claim 10, Steward discloses the server architecture, wherein the first memory circuitry is part of the circuit board (Fig. 1, and memory 158 in sub frame 172, para. 0124).
As to claim 11, Steward discloses the server architecture, wherein the circuit board includes another motherboard, a fabric extender, or a backplane of the server architecture (Fig. 25, and para. 0051).
As to claims 14, and 15, Steward discloses the server architecture, wherein the logic at the first memory circuitry corresponds to an I/O port (Fig. 1, and I/O ports on frame subcircuits such as 176, comprising memory such as 136, para. 0124).
As to claim 25, Smith discloses the method, wherein the memory circuitry is a first memory circuitry, and wherein accessing cable information includes accessing the cable information from a second memory circuitry storing the cable information (Fig. 3, and para. 0034). One of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to use the cable capability of Smith in the system of Steward to couple the system’s sub systems to gain the programming flexibility of this cable, (para. 0009).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Steward/Smith in view of Itkin (US20180239730).
As to claim 12, Steward/Smith does not explicitly disclose the server architecture, wherein the motherboard includes a Baseboard Management Controller (BMC), and wherein the one or more processors are processing circuitries of the BMC.
Itkin teaches the server architecture, wherein the motherboard includes a Baseboard Management Controller (BMC), and wherein the one or more processors are processing circuitries of the BMC. (Fig. 1, and para. 0033, where BMC serves said purpose. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the controller of Itkin in the system of Steward/Smith to add this remote management capability with little overhead, (para. 0010)
Allowable Subject Matter
Claims 3 – 6, 13, 18 – 21, and 24 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER ANTHONY DALEY whose telephone number is (571)272-3625. The examiner can normally be reached 7 - 3:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached at 571 2724176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights