Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This Office Action responds to the Election of Restriction Requirement filed on 11/20/2025 and IDS filed on 10/25/2022, 4/21/2023, and 3/23/2026.
Claims 1-14, 18, 19, 23-25, and 28 are pending.
Election/Restrictions
3. Applicant’s election without traverse of Group I (Claims 1-13) in the reply filed on 11/20/2025 is acknowledged.
4. Claims 14, 18, 19, 23-25, and 28 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 11/20/2025.
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim(s) 1-4, and 8-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kao et al. (U.S. Pat. No. 10,685,166 B1) in view of Chhabria et al. (U.S. Pub. No. 2022/0067481 A1).
As per claim 1, Kao discloses:
A 3D modeling (three-dimensional modeling) method, the method comprising:
obtaining geometric data representing a 3D structure and input parameters including factors determining an attribute of the 3D structure (See Figures 2A-2F, See Col 13; Line 62 to Col 14; Line 15, i.e. layout artwork … a corresponding techfile or technology file, See Col 14; Line 55-57, i.e. layout artwork stores only the geometric…technologies file is used to store…thickness…the materials);
generating, by a computer system comprising a memory that stores instructions and a processor that executes the instructions, grid data from the geometric data (See Figures 2A-2F, See Col 17; Lines 16 to Col 18; Line 3, i.e. a layout simulation or analysis module may consider the meshes and/or nodes in at least the overlapping portion of an existing model in the generation or discretization of the 3D model for the region);
sequentially generating at least one piece of down-sampled data from the grid data (See Figures 2A-2F, See Col 18; Lines 4-47, i.e. layout artwork pertaining to the identified region may be optionally simplified or reduced at 212C based at least in part upon one or more criteria… analysis module may reduce the observed or predicted processing bottleneck at 214C based at least in part upon the criticality of the circuit portions);
generating a 3D feature map by pre-processing the input parameters (See Figures 2A-2F, See Col 18; Lines 18 to Col 19; Line 59, i.e. identifying or generating a first 3D model for the region may include processing of the pertinent layout artwork corresponding to the identified region for which the first 3D model is to be generated. For generating a 3D shape in the first 3D model, a layout simulation or analysis module may identify two- or one-dimensional shape data from the pertinent layout artwork (e.g., for geometric or location data) and optionally from the corresponding technology file (e.g., for definitions of thickness, materials, etc.) at 210D ) and
generating attribute profile data, representing a profile of the attribute in the 3D structure, from the at least one piece of down-sampled data and the 3D feature map (See Figure 2D, i.e. 218 – associate properties with the 3D object, See Col 18; Lines 18 to Col 19; Line 59, i.e. One or more properties needed for subsequent analyses may be associated with the 3D object in the first 3D model at 218D, See Figure 2E & 2F, See Col 20; Line 5 to Col 22; Line 15 –[prior art determine properties base on flow diagram of Figure 2A and 2B-2F is considered as the generating as cited above])
Kao does not teach the limitations: generating attribute profile data in the 3D structure based on at least one machine learning model respectively corresponding to at least one stage.
However, Chhabria teach the limitations: generating attribute profile data in the 3D structure based on at least one machine learning model respectively corresponding to at least one stage (See Para [0020]-0023], i.e. power maps input into a three-dimensional (3D) CNN model…determine the plurality of coefficient maps, See Para [0037]-[0041], See Figure 2).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Chhabria
into the teaching of Kao because it would allow for engineer to determine voltage drop
more accurately in a circuit design (See Para [0016]).
As per claim 2, Kao and Chhabria discloses all of the features of claim 1 as discloses above wherein Kao also discloses wherein the generating the grid data comprises interpolating a grid of the geometric data to have a constant interval (See Figures 2A-2F, See Col 18; Lines 4-47, i.e. layout artwork pertaining to the identified region may be optionally simplified or reduced at 212C based at least in part upon one or more criteria… analysis module may reduce the observed or predicted processing bottleneck at 214C based at least in part upon the criticality of the circuit portions).
As per claim 3, Kao and Chhabria discloses all of the features of claim 2 as discloses above wherein Kao also discloses wherein the interval corresponds to a minimum interval in the grid of the geometric data (See Figures 2A-2F, See Col 18; Lines 4-47, i.e. layout artwork pertaining to the identified region may be optionally simplified or reduced at 212C based at least in part upon one or more criteria… analysis module may reduce the observed or predicted processing bottleneck at 214C based at least in part upon the criticality of the circuit portions –[prior art mesh considered as the minimum interval as cited above]).
As per claim 4, Kao and Chhabria discloses all of the features of claim 1 as discloses above wherein Kao also discloses wherein the generating the grid data comprises setting values, corresponding to a region except a region of interest of the 3D structure, to zero (See Figure 2A, i.e. 204 – identify a region, See Col 6; Lines 45-60, i.e. identify a region of interest in the layout window, See Col 9 ; Lines 58-67, i.e. identify a region of interest 112).
As per claim 8, Kao and Chhabria discloses all of the features of claim 1 as discloses above wherein Chhabria also discloses training the at least one machine learning model based on a loss function, wherein the loss function is based on an average and a variance of the attribute profile data (See Para [0132], i.e. adopted. L1 loss and an Adam optimizer are used for backpropagation).
As per claim 9, Kao and Chhabria discloses all of the features of claim 8 as discloses above wherein Kao also discloses wherein the training the at least one machine learning model comprises setting, to zero, the loss function in association with data corresponding to a region except a region of interest of the 3D structure (See Figure 2A, i.e. 204 – identify a region, See Col 6; Lines 45-60, i.e. identify a region of interest in the layout window, See Col 9 ; Lines 58-67, i.e. identify a region of interest 112).
As per claim 10, Kao and Chhabria discloses all of the features of claim 1 as discloses above wherein Kao also discloses wherein the 3D structure corresponds to a device of an integrated circuit, the input parameters comprise process parameters used in manufacturing the integrated circuit, and the attribute profile data represents a doping profile in the device (See Figures 2A-2F, See Col 13; Line 62 to Col 14; Line 15, i.e. layout artwork … a corresponding techfile or technology file, See Col 14; Line 55-57, i.e. layout artwork stores only the geometric…technologies file is used to store…thickness…the materials).
As per claim 11, Kao and Chhabria discloses all of the features of claim 1 as discloses above wherein Kao also discloses generating profile data corresponding to a grid of the geometric data by interpolating a grid of the attribute profile data (See Figure 2D, i.e. 218 – associate properties with the 3D object, See Col 18; Lines 18 to Col 19; Line 59, i.e. One or more properties needed for subsequent analyses may be associated with the 3D object in the first 3D model at 218D, See Figure 2E & 2F, See Col 20; Line 5 to Col 22; Line 15).
As per claim 12, Kao discloses:
A system, comprising: at least one processor; and a non-transitory storage medium configured to store instructions, wherein, when executed by the processor, the instructions cause the system (See Col 4; Lines 34-46) to:
obtain geometric data representing a 3D structure and input parameters including factors determining an attribute of the 3D structure (See Figures 2A-2F, See Col 13; Line 62 to Col 14; Line 15, i.e. layout artwork … a corresponding techfile or technology file, See Col 14; Line 55-57, i.e. layout artwork stores only the geometric…technologies file is used to store…thickness…the materials);
generate grid data from the geometric data (See Figures 2A-2F, See Col 17; Lines 16 to Col 18; Line 3, i.e. a layout simulation or analysis module may consider the meshes and/or nodes in at least the overlapping portion of an existing model in the generation or discretization of the 3D model for the region);
sequentially generate at least one piece of down-sampled data from the grid data (See Figures 2A-2F, See Col 18; Lines 4-47, i.e. layout artwork pertaining to the identified region may be optionally simplified or reduced at 212C based at least in part upon one or more criteria… analysis module may reduce the observed or predicted processing bottleneck at 214C based at least in part upon the criticality of the circuit portions);
generate a 3D feature map by pre-processing the input parameters (See Figures 2A-2F, See Col 18; Lines 18 to Col 19; Line 59, i.e. identifying or generating a first 3D model for the region may include processing of the pertinent layout artwork corresponding to the identified region for which the first 3D model is to be generated. For generating a 3D shape in the first 3D model, a layout simulation or analysis module may identify two- or one-dimensional shape data from the pertinent layout artwork (e.g., for geometric or location data) and optionally from the corresponding technology file (e.g., for definitions of thickness, materials, etc.) at 210D ); and
generate attribute profile data, representing a profile of the attribute in the 3D structure, from the at least one piece of down-sampled data and the 3D feature map (See Figure 2D, i.e. 218 – associate properties with the 3D object, See Col 18; Lines 18 to Col 19; Line 59, i.e. One or more properties needed for subsequent analyses may be associated with the 3D object in the first 3D model at 218D, See Figure 2E & 2F, See Col 20; Line 5 to Col 22; Line 15 –[prior art determine properties base on flow diagram of Figure 2A and 2B-2F is considered as the generating as cited above]).
Kao does not teach the limitations: generate attribute profile data in the 3D structure based on at least one machine learning model respectively corresponding to at least one stage.
However, Chhabria teach the limitations: generate attribute profile data in the 3D structure based on at least one machine learning model respectively corresponding to at least one stage (See Para [0020]-0023], i.e. power maps input into a three-dimensional (3D) CNN model…determine the plurality of coefficient maps, See Para [0037]-[0041], See Figure 2).
Therefore, it would have been obvious to a person of ordinary skill in the
art at the effective filing date of the invention to incorporate the teaching of Chhabria
into the teaching of Kao because it would allow for engineer to determine voltage drop
more accurately in a circuit design (See Para [0016]).
As per claim 13, Kao and Chhabria discloses all of the features of claim 1 as discloses above wherein Kao also discloses a non-transitory computer-readable storage medium comprising instructions allowing at least one processor to perform the 3D modeling method of claim 1 when the instructions are executed by the at least one processor (See Col 4; Lines 34-46).
Allowable Subject Matter
7. Claims 5-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
8. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not teach the limitations of claim 5, wherein claims 6 and 7 depend directly and/or indirectly from claim 5.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NHA T NGUYEN whose telephone number is (571)270-1405. The examiner can normally be reached M-F 8:00AM-5:00PM.
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/NHA T NGUYEN/Primary Examiner, Art Unit 2851
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