DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6 April 2026 is entered.
Response to Arguments
Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
The disclosure is objected to because of the following informalities: it is unclear whether the language “…subpixel…” describes (i) only a light emitting device, or (ii) both a light emitting device and its corresponding circuit elements.
[0068] of the instant application suggests that language “…subpixel…” captures only the light emitting device to which at least one of the circuit elements1 is connected ([0068]: “…first subpixel…connected to a circuit element…”).
[0095], [0098] of the instant application suggest that language “…subpixel…” captures both the light emitting device and at least one of the aforementioned circuit elements ([0095]: “…portions…at which the red subpixel R2 and the blue subpixel B…contact the first line…”; [0098]: “…green subpixel G contacts the second line…”)3.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
i. The above objection to the specification identifies instances within the disclosure wherein the language “…subpixel…” corresponds to (i) only a light emitting device (Figure 2: Comprising ED), and (ii) both the light emitting device and its corresponding circuit elements (Comprising DT, T1…T5, Cstg).
Because claim 1 is amended to describe both the subpixels’ shape (i.e. vertices and edges), as well as its connection to one of first and second lines (Circuit schematic of Figure 2 showing gate lines G1, G2 connected to T1, T2, T5), the language “…subpixel…” is interpreted to capture both the light emitting device and its corresponding circuit elements.
ii. The “…first connection portion…” “…second connection portion…” and “…third connection portion…” recited in claim 1 are not described in the specification.
By virtue of the claimed “…connection portion(s)…” capturing a scope greater than the disclosure’s use of the language “…portion(s)…”4 and Figure 2’s illustration of gate line connections being formed with gates of transistors in the subpixel circuits, the “…connection portion(s)…” are treated as instances of the common practice5 of using simplified visual placeholders for circuitry which may form the identified connection.
iii. Claim 12 is amended with language similar to that identified above with reference to claim 1, and is rejected on similar grounds.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
i. Claims 1 – 4, 6 – 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (2019/0181205) and Li (2021/0134223) in view of Han et al. (2020/0395418; hereinafter Han; this combination of references hereinafter referred to as HLK).
Regarding claim 1, Kim discloses a display apparatus [0001] comprising:
a first driving circuit supplying a gate signal ([0057]: “…scan driving circuit may…supply the scan signals…”) through a first line (Figure 4: Comprising one of SLk, SLk+1) and supplying the gate signal through a second line (Comprising other one of SLk, SLk+1);
a display panel including a first pixel (Comprising e.g. P1) and a second pixel (Comprising e.g. P2), the first pixel including:
a first subpixel (Comprising e.g. RP) connected to the first line (Comprising SLk),
a second subpixel (Comprising BP) connected to the second line (Comprising SLk+1), and
a third subpixel (Comprising GP1) connected to the first line (Comprising SLk); and
a second driving circuit (Comprising 70 of Figure 2; [0048]) supplying a data signal ([0049]: Data driving circuit generating and suppling data voltages to data lines) to the first subpixel (Comprising RP) and the third subpixel (Comprising GP1) and supplying the data signal to the second subpixel (Comprising BP);
the first subpixel (Comprising RP), second subpixel (Comprising BP), and third subpixel (Comprising GP1) each including a plurality of vertices and a plurality of edges each connecting to two adjacent vertices (Each among subpixels RP, BP, GP1 represented with corresponding emission part RE, BE, GE1 formed with four corners and two pair of parallel sides).
Kim does not make an outright statement of first and second times, during which first and second lines are supplied the gate signal, wherein during said first time, the first and third subpixels supplied the data signal, and during said second time, the second subpixel is supplied the data signal. However, please consider the following.
[i] Despite lacking the claim language “…first time…” and “…second time…” descriptive of when respective ones of first and second lines are supplied a gate signal, said gate signal is indeed transmitted to scan lines “…sequentially…” [0057]. The verbiage “…sequentially…” is understood to communicate respective ones among scan lines are transmitted a gate signal one after another, at corresponding times in a sequence. The timing with which scan lines SLk and SLk+1 in Figure 4 of Kim (analogous teachings of first and second lines) are transmitted a gate signal, thus reads fairly on the claimed first and second times.
[ii] Pixels’ receiving data voltages occurs commensurate with the timing of the scan signal applied to said pixel’s associated scan line [0057]. The illustration in Figure 4 of first (Comprising RP) and third (Comprising GP1) subpixels’ coupling to the shared scan line (SLk) thus communicates said subpixels’ receiving of a data signal at a same “…first…” time, differing from the “…second…” time at which the second (Comprising BP) subpixel, coupled to a differing scan line (SLk+1), receives a data signal (In keeping with the aforementioned sequence). The aforementioned is interpreted to be an indirect, but fair reading upon the claimed subject matter.
It would obvious to one having ordinary skill in the art before the filing date of the claimed invention that the apparatus of Kim provides a fair reading upon the apparatus being provided wherein first and second times, during which first and second lines are supplied the gate signal, wherein during said first time, the first and third subpixels supplied the data signal, and during said second time, the second subpixel is supplied the data signal, as claimed, in view of the reasoning above.
Kim does not explicitly disclose the apparatus wherein the second time is delayed from the first time by one sub-frame.
In the same field of endeavor, Li’s display [0002] array substrate [0003] is provided wherein sub-images of sub-pixels coupled to first and second scanning lines are furnished during respective ones of first and second sub-frames [0097]. This is among measures by which sufficient space for pixel circuitry is furnished in high resolution displays [0043]. As much is suggested by Kim’s cursorily mentioning of “…sequentially…” transmitting scan signals [0057] that lacks discussion of timing relative to the frame. Li’s efficient wiring scheme is functionality from which Kim stands to benefit.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the second time is delayed from the first time by one sub-frame, in view of the teaching of Li, to efficiently wire pixel circuitry a high resolution display.
Kim in view of Li does not explicitly disclose the apparatus wherein the first subpixel connected to a line through a first connection portion extending from an edge of the first subpixel and offset from any vertex of the first subpixel, the second subpixel connected to a line through a second connection portion extending from at least one vertex of the second subpixel, and the third subpixel connected to a line through a third connection portion extending from at least one vertex of the third subpixel.
In the same field of endeavor, Han discloses a display and its manufacturing method [0002] forming the first subpixel (Figure 3A: Comprising one among 311…314) connected to a line ([0072]: Gate line) through a first connection portion (Comprising 350) extending from an edge of the first subpixel and offset from any vertex of the first subpixel (Note positioning away from corners, sides of respective ones among 311…314), the second subpixel (Comprising second, differing one among 311...314) connected to a line ([0072]: Gate line) through a second connection portion (Comprising 350) extending from at least one vertex of the second subpixel (Note positioning away from corners, sides of respective ones among 311…314), and the third subpixel (Comprising third, differing one among 311…314) connected to a line ([0072]: Gate line) through a third connection portion (Comprising 350) extending from at least one vertex of the third subpixel l (Note positioning away from corners, sides of respective ones among 311…314). This structure is among measures implemented to simplify the manufacturing process [0090].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the first subpixel connected to a line through a first connection portion extending from an edge of the first subpixel and offset from any vertex of the first subpixel, the second subpixel connected to a line through a second connection portion extending from at least one vertex of the second subpixel, and the third subpixel connected to a line through a third connection portion extending from at least one vertex of the third subpixel, in view of the teaching of Han, to simplify the manufacturing process.
Regarding claim 2, HLK discloses the display apparatus of claim 1. Kim discloses the apparatus (Figure 4) wherein the first subpixel is a red subpixel (Comprising RP).
Kim does not explicitly disclose the apparatus wherein the second subpixel is a green subpixel, and the third subpixel is a blue subpixel.
In the same field of endeavor, Li discloses a display [0002] whose pixel units (Figure 6) are formed wherein the first subpixel is a red subpixel (Comprising R), the second subpixel is a green subpixel (Comprising G), and the third subpixel is a blue subpixel (Comprising B; note example of R and B coupled to same scan line e.g. G11). This is among measures by which sufficient space for pixel circuitry is furnished in high resolution displays [0043].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the second subpixel is a green subpixel, and the third subpixel is a blue subpixel, in view of the teaching of Li, to more efficiently wire display pixels.
Regarding claim 3, HLK discloses the display apparatus of claim 1. Kim discloses the apparatus (Figure 4) wherein the first subpixel is a green subpixel (Comprising GP2), the second subpixel is a red subpixel (Comprising RP), and the third subpixel is a blue subpixel (Comprising BP).
Regarding claim 4, HLK discloses the display apparatus of claim 1. Kim discloses the apparatus (Figure 4) wherein the first subpixel (Comprising RP) is disposed more upward than the second subpixel (Comprising BP) in a first axis direction (e.g. Parallel to direction of DLj).
Regarding claim 6, HLK discloses the display apparatus of claim 1. Kim discloses the apparatus wherein the first time and the second time are successive (“…sequentially supply the scan signals to the scan lines…” [0057] comprising SLk, SLk+1 in Figure 4).
Regarding claim 7, HLK discloses the display apparatus of claim 1. Kim discloses the apparatus wherein the first driving circuit comprises a gate driver [0057], and the second driving circuit comprises a data driver [0049].
Regarding claim 8, HLK discloses the display apparatus of claim 1. Kim discloses the apparatus (Figure 4) comprising: n+1 number of gate lines connected to the first driving circuit to transfer the gate signal ([0057]: Scan driving circuit supplies scan signals to scan lines) to a plurality of subpixels (Comprising RE, BE, GE1, GE2) included in the display apparatus, where n is an integer larger than 1 (Two scan lines {SLk, SLk+1}; brevity of illustration for convenience sake [0061] implying more); and m number of data lines connected to the second driving circuit to transfer the data signal ([0049]: Data driving circuit supplies data voltages to data lines) to the plurality of subpixels (Comprising RE, BE, GE1, GE2), where m is an integer larger than 1 (Three data lines {DLj…DLj+1}; brevity of illustration for convenience sake [0061] implying more).
Regarding claim 9, HLK discloses the display apparatus of claim 8. Kim discloses the apparatus wherein the n+1 number of gate lines include the first line ([0070]: SLk–1), the second line (Figure 4: Comprising SLk), and the third line (Comprising SLk+1).
ii. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over HLK, as applied to claim 1 above, and further in view of Hwang et al. (2011/0260952; hereinafter Hwang).
Regarding claim 5, HLK discloses the display apparatus of claim 1.
HLK does not explicitly disclose the apparatus wherein virtual lines connecting centers of the first subpixel, the second subpixel, and the third subpixel to each other form a triangular shape.
However, Hwang teaches a display device whose subpixel arrangement ([0003]; Figure 3) is provided wherein virtual lines connecting centers of the first subpixel, the second subpixel, and the third subpixel (Corresponding to one of SPR, SPG, SPB) to each other form a triangular shape (Of “…Delta Arrangement…”). This is among measures by which favorable aperture ratio and luminance are preserved [0010].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein virtual lines connecting centers of the first subpixel, the second subpixel, and the third subpixel to each other form a triangular shape, in view of the teaching of Hwang, to preserve a favorable aperture ratio and luminance.
iii. Claims 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over HLK, as applied to claim 1 above, and further in view of Park et al. (2018/0342572; hereinafter Park).
Regarding claims 10 and 11, HLK discloses the display apparatus of claim 1. Kim discloses the apparatus (Figure 4) wherein the second line (Comprising SLk+1) is a line disposed more downward than the first line (Comprising SLk).
HLK fails to explicitly disclose the apparatus wherein the first line is a line disposed at an uppermost end among a plurality of lines connected to the first driving circuit, wherein the display panel further includes a dummy pixel disposed more upward than the first line, wherein the dummy pixel is connected to the first line, and a portion at which the dummy pixel contacts the first line is disposed in the first line.
In the same field of endeavor, Park discloses a display [0002] formed wherein the first line (Figure 3: Comprising S21, S31; coupled to PXL2, PXL3) is a line disposed at an uppermost end among a plurality of lines (Comprising S21/S31…S1n) connected to the first driving circuit (Comprising SDV1, SDV2, SDV3), wherein the display panel further includes a dummy pixel (Figure 15: Comprising at least one of DMP1…DMP5) disposed more upward than the first line (To which PXL2, PXL3 are coupled; see S21, S31 in Figure 3), wherein the dummy pixel (Examples of at least one of DMP2, DMP3) is connected (By DSL1 in Figure 16, through DMP4 [0307]) to the first line (Comprising S2p; corresponding to earlier example of S21 in Figure 3), and a portion at which the dummy pixel (e.g. DMP2) contacts the first line is disposed in the first line (Comprising S21/S2p). This is among measures taken to equalize the load of signal lines [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the first line is a line disposed at an uppermost end among a plurality of lines connected to the first driving circuit, wherein the display panel further includes a dummy pixel disposed more upward than the first line, wherein the dummy pixel is connected to the first line, and a portion at which the dummy pixel contacts the first line is disposed in the first line, in view of the teaching of Kim, to equalize signal line load.
iv. Claims 12 – 15, 17 – 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Lee (2019/0355301), Li and Sakaigawa (2015/0331291) in view of Han (this combination of references hereinafter referred to HSLLK).
Regarding claim 12, Kim discloses a display panel ([0001]; Figure 4) comprising:
a first line (Comprising one of SLk, SLk+1) transferring a gate signal [0070];
a second line (Comprising other one of SLk, SLk+1) transferring the gate signal (Scan signals supplied to scan lines [0057] in respective pixel area [0061]);
a first pixel (Comprising e.g. P1) including:
a first subpixel (Comprising e.g. RP) connected to the first line (Comprising e.g. SLk), a second subpixel (Comprising GP2) connected to the second line (Comprising SLk+1), and a third subpixel (Comprising GP1) connected to the first line (Comprising SLk); and a third line (Comprising DLj) transferring a data signal to the first subpixel (Comprising RP); and
a fourth line (Comprising DLj+1) transferring the data signal to the second subpixel (Comprising BP);
the first subpixel (Comprising RP), second subpixel (Comprising BP), and third subpixel (Comprising GP1) each including a plurality of vertices and a plurality of edges each connecting to two adjacent vertices (Each among subpixels RP, BP, GP1 represented with corresponding emission part RE, BE, GE1 formed with four corners and two pair of parallel sides).
Kim does not make an outright statement of first and second times, during which first and second lines are supplied the gate signal, wherein during said first time, the third line transferring a data signal to the first subpixel, during said second time, the fourth line transferring the data signal to the second subpixel.
However, please consider the following.
[i] Despite lacking the claim language “…first time…” and “…second time…” descriptive of when respective ones of first and second lines are supplied a gate signal, said gate signal is indeed described by Kim as being transmitted to scan lines “…sequentially…” [0057]. The verbiage “…sequentially…” is understood to communicate respective ones among scan lines are transmitted a gate signal one after another, at corresponding times in a sequence. The timing with which scan lines SLk and SLk+1 in Figure 4 of Kim (analogous teachings of first and second lines) are transmitted a gate signal, thus reads fairly on the claimed first and second times.
[ii] Pixels’ receiving data voltages occurs commensurate with the timing of the scan signal applied to said pixel’s associated scan line [0057]. The illustration in Figure 4 of first subpixel’s (Comprising RP) coupling to the scan line (SLk; analogous to the claimed first line) communicates said subpixel’s receiving of a data signal, transmitted by the analogous teaching of a third line (Comprising DLj), at a “…first…” time, differing from a “…second…” time at which the second subpixel (Comprising GP2), coupled to a differing scan line (SLk+1), receives its data signal, transmitted by the analogous teaching of a fourth line (Comprising DLj+1). The aforementioned is interpreted to be an indirect, but fair reading upon the claimed subject matter.
It would obvious to one having ordinary skill in the art before the filing date of the claimed invention that the disclosure of Kim provides a fair reading upon the apparatus being provided, facilitating first and second times, during which first and second lines are supplied the gate signal, wherein during said first time, the third line transferring a data signal to the first subpixel, during said second time, the fourth line transferring the data signal to the second subpixel, as claimed, in view of the reasoning above.
Kim does not explicitly disclose the panel wherein a third line transferring a data signal to the first subpixel and the third subpixel at the first time.
In the same field of endeavor, Lee discloses display pixel driving [0001] wherein first and second pixel units of a pair ([0031]; Comprising 10a, 10b of Figure 1) are coupled to the same scan and data lines [0029]. Coupling to a shared scan line facilitates the aforementioned two colors’ receiving data at the same time.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Kim to be modified wherein a third line transferring a data signal to the first subpixel and the third subpixel at the first time, in view of the teaching of Lee, to reduce the relative size driving circuitry.
Kim in view of Lee do not explicitly disclose the panel wherein the second time is delayed from the first time by one sub-frame.
In the same field of endeavor, Li’s display [0002] array substrate [0003] is provided wherein sub-images of sub-pixels coupled to first and second scanning lines are furnished during respective ones of first and second sub-frames [0097]. This is among measures by which sufficient space for pixel circuitry is furnished in high resolution displays [0043]. As much is suggested by Kim’s cursorily mentioning of “…sequentially…” transmitting scan signals [0057] that lacks discussion of timing relative to the frame. Li’s efficient wiring scheme is functionality from which Kim stands to benefit.
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the second time is delayed from the first time by one sub-frame, in view of the teaching of Li, to efficiently wire pixel circuitry a high resolution display.
Kim, Lee and Li does not explicitly disclose the apparatus wherein the first subpixel on a first side of the first line and at a first connection point on the first line, the third subpixel on the first side of the first line and at a second connection point on the first line.
In the same field of endeavor, Sakaigawa discloses a display ([0003]; Figure 13) including the first subpixel (Comprising 49B of 48B) on a first side (In direction parallel with DTL, “…below…” with respect to the orientation of the figure) of the first line (Comprising *SCL2) and at a first connection point (Comprising *2P) on the first line (Comprising *SCL2), the third subpixel (Comprising 49W of 48B) on the first side (i.e. “…below…”) of the first line (Comprising *SCL2) and at a second connection point (Comprising *3P) on the first line (Comprising *SCL2). This is among measures implemented to increase pixel density [0007].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the first subpixel on a first side of the first line and at a first connection point on the first line, the third subpixel on the first side of the first line and at a second connection point on the first line, in view of the teaching of Sakaigawa, to increase pixel density.
Kim, Lee and Li in view of Sakaigawa do not explicitly disclose the apparatus wherein the first subpixel connected to the first line through a first connection portion extending from an edge of the first subpixel and offset from any vertex of the first subpixel, the second subpixel connected to the second line through a second connection portion extending from at least one vertex of the secondsubpixel, and the third subpixel connected to the first line through a third connection portion extending from at least one vertex of the third subpixel.
In the same field of endeavor, Han discloses a display and its manufacturing method [0002] forming the first subpixel (Figure 3A: Comprising one among 311…314) connected to a line ([0072]: Gate line) through a first connection portion (Comprising 350) extending from an edge of the first subpixel and offset from any vertex of the first subpixel (Note positioning away from corners, sides of respective ones among 311…314), the second subpixel (Comprising second, differing one among 311...314) connected to a line ([0072]: Gate line) through a second connection portion (Comprising 350) extending from at least one vertex of the second subpixel (Note positioning away from corners, sides of respective ones among 311…314), and the third subpixel (Comprising third, differing one among 311…314) connected to a line ([0072]: Gate line) through a third connection portion (Comprising 350) extending from at least one vertex of the third subpixel l (Note positioning away from corners, sides of respective ones among 311…314). This structure is among measures implemented to simplify the manufacturing process [0090].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the first subpixel connected to a line through a first connection portion extending from an edge of the first subpixel and offset from any vertex of the first subpixel, the second subpixel connected to a line through a second connection portion extending from at least one vertex of the second subpixel, and the third subpixel connected to a line through a third connection portion extending from at least one vertex of the third subpixel in view of the teaching of Han, to simplify the manufacturing process.
Regarding claim 13, HSLLK discloses the display panel of claim 12. Kim discloses the panel (Figure 4) wherein the first subpixel is a red subpixel (Comprising RP).
Kim does not explicitly disclose the panel wherein the second subpixel is a green subpixel, and the third subpixel is a blue subpixel.
In the same field of endeavor, Li discloses a display [0002] whose pixel units (Figure 6) are formed wherein the first subpixel is a red subpixel (Comprising R), the second subpixel is a green subpixel (Comprising G), and the third subpixel is a blue subpixel (Comprising B; note example of R and B coupled to same scan line e.g. G11). This is among measures by which sufficient space for pixel circuitry is furnished in high resolution displays [0043].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein the second subpixel is a green subpixel, and the third subpixel is a blue subpixel, in view of the teaching of Li, to more efficiently wire display pixels.
Regarding claim 14, HSLLK discloses the display panel of claim 12. Kim discloses the panel (Figure 4) wherein the first subpixel is a green subpixel (Comprising GP2), the second subpixel is a red subpixel (Comprising RP), and the third subpixel is a blue subpixel (Comprising BP).
Regarding claim 15, HSLLK discloses the display panel of claim 12. Kim discloses the panel (Figure 4) wherein the first subpixel (Comprising RP) is disposed more upward than the second subpixel (Comprising BP) in a first axis direction (e.g. Parallel to direction of DLj).
Regarding claim 17, HSLLK discloses the display panel of claim 12. Kim discloses the panel wherein the first time and the second time are successive (“…sequentially supply the scan signals to the scan lines…” [0057] comprising SLk, SLk+1 in Figure 4).
Regarding claim 18, HSLLK discloses the display panel of claim 12. Kim discloses the panel (Figure 4) wherein the first line (Comprising SLk) and the second line (Comprising SLk+1) are connected to a first driving circuit ([0057]: Scan driving circuit), and the third line (Comprising e.g. DLj) and the fourth line (Comprising DLj+1) are connected to a second driving circuit ([0049]: Data driving circuit).
Regarding claim 19, HSLLK discloses the display panel of claim 18. Kim discloses the panel wherein the first driving circuit comprises a gate driver ([0057]: Scan driving circuit), and the second driving circuit comprises a data driver ([0049]: Data driving circuit).
Regarding claim 20, HSLLK discloses the display panel of claim 12. Kim discloses the panel comprising: n+1 number of gate lines connected to a first driving circuit to transfer the gate signal ([0057]: Scan driving circuit supplies scan signals to scan lines) to a plurality of subpixels (Comprising RE, BE, GE1, GE2) included in the display panel, where n is an integer larger than 1 (Two scan lines {SLk, SLk+1}; brevity of illustration for convenience sake [0061] implying more); and m number of data lines connected to a second driving circuit to transfer the data signal ([0049]: Data driving circuit supplies data voltages to data lines) to the plurality of subpixels (Comprising RE, BE, GE1, GE2), where m is an integer larger than 1 (Three data lines {DLj…DLj+1}; brevity of illustration for convenience sake [0061] implying more).
Regarding claim 21, HSLLK discloses the display panel of claim 20. Kim discloses the panel (Figure 4) wherein the n+1 number of gate lines include the first line (Comprising SLk) and the second line (Comprising SLk+1), and the m number of data lines include the third line (Comprising e.g. DLj) and the fourth line (Comprising DLj+1).
v. Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over HSLLK as applied to claim 12 above, and further in view of Hwang.
Regarding claim 16, HSLLK discloses the display panel of claim 12.
HSLLK does not explicitly disclose the panel wherein virtual lines connecting centers of the first subpixel, the second subpixel, and the third subpixel form a triangular shape.
However, Hwang teaches a display device whose subpixel arrangement ([0003]; Figure 3) is provided wherein virtual lines connecting centers of the first subpixel, the second subpixel, and the third subpixel (Corresponding to one of SPR, SPG, SPB) to each other form a triangular shape (Of “…Delta Arrangement…”). This is among measures by which favorable aperture ratio and luminance are preserved [0010].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the panel of Kim to be modified wherein virtual lines connecting centers of the first subpixel, the second subpixel, and the third subpixel to each other form a triangular shape, in view of the teaching of Hwang, to preserve a favorable aperture ratio and luminance.
vi. Claims 22, 23 are rejected under 35 U.S.C. 103 as being unpatentable over HSLLK, as applied to claim 18 above, and further in view of Park.
Regarding claims 22 and 23, HSLLK discloses the display panel of claim 18. Kim discloses the panel (Figure 4) wherein the second line (Comprising SLk+1) is a line disposed more downward than the first line (Comprising SLk).
HSLLK fails to explicitly disclose the panel wherein the first line is a line disposed at an uppermost end among a plurality of lines connected to the first driving circuit, wherein the fourth subpixel is a dummy pixel disposed more upward than the first line.
In the same field of endeavor, Park discloses a display [0002] formed wherein the first line (Figure 3: Comprising S21, S31; coupled to PXL2, PXL3) is a line disposed at an uppermost end among a plurality of lines (Comprising S21/S31…S1n) connected to the first driving circuit (Comprising SDV1, SDV2, SDV3), wherein the fourth subpixel is a dummy pixel (Figure 15: Comprising at least one of DMP1…DMP5) disposed more upward than the first line (To which PXL2, PXL3 are coupled; see S21, S31 in Figure 3). This is among measures taken to equalize the load of signal lines [0006].
It would be obvious to one having ordinary skill in the art before the filing date of the claimed invention for the apparatus of Kim to be modified wherein wherein the first line is a line disposed at an uppermost end among a plurality of lines connected to the first driving circuit, wherein the fourth subpixel is a dummy pixel disposed more upward than the first line, in view of the teaching of Park, to equalize signal line load.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to Aaron Midkiff whose telephone number is (571)270-5875. The examiner can normally be reached Monday - Friday, 8:00am - 4:00pm.
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/AARON MIDKIFF/
Examiner, Art Unit 2621
/AMR A AWAD/Supervisory Patent Examiner, Art Unit 2621
1 [0065], Figure 2: Transistors DT, T1…T5 and capacitor Cstg.
2 Identifying visual outline designated with reference numeral “…R…” assumed to correspond to at least one of corresponding light emitting device anode or cathode; [0060].
3 Figure 2: In light of T1, T2, T5 contacting gate lines (G1, G2; interpreted as analogous to e.g. 610 and 620 in Figure 6).
4 [0095], [0098]: Contact holes connecting subpixels and (first, second) lines.
5 Evidentiary reference Kim et al. (2018/0062107) | Figure 2, [0052]: sub-pixel connection to lines visualized as direct, but acknowledged to comprise at least one thin film transistor of which sub-pixel circuitry is comprised.
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