DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed March 11, 2026 have been entered and considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-4, 12-13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Morita et al. (US 20150318400 A1), in view of Yamazaki (US 9865743 B2), Ito et al. (US 8741702 B2) and Jung et al. (CN 103618004 A).
Regarding claim 1, Morita et al. teaches:
An electronic device, comprising:
a substrate [1, paragraph [0129], Fig. 3];
a transistor [TFT, paragraph [0014], Fig. 3] disposed on the substrate [1] and comprising a source electrode [5 (left), paragraph [0129], Fig. 3], a drain electrode [5 (right), paragraph [0129], Fig. 3], and a gate electrode [2, paragraph [0129], Fig. 3]; and
a first insulating layer [3, paragraph [0129], Fig. 3] disposed between the source electrode [5 (left)] and the gate electrode [2] and between the drain electrode [5 (right)] and the gate electrode [2],
wherein the first insulating layer [3] has a first portion and a second portion, the first portion is defined as a portion overlapped with the source electrode [5 (left)] and the drain electrode [5 (right)], the second portion is defined as a portion not overlapped with the source electrode [5 (left)] and the drain electrode [5 (right)]
wherein the transistor [TFT] comprises a semiconductor layer [4, paragraph [0091], [0097], Fig. 3], the source electrode [5 (left), Fig. 3] and the drain electrode [5 (right), Fig. 3] are in contact with a portion of the semiconductor layer [4, Fig. 3] and expose another portion of the semiconductor layer [4, Fig. 3].
an orthographic projection of the another portion of the semiconductor layer [4, Fig. 3] on the substrate [1, Fig. 3] is less than the orthographic projection of the gate electrode [2, Fig. 3] on the substrate [1, Fig. 3].
Morita et al. does not teach:
a minimum thickness of the first portion is greater than a minimum thickness of the second portion.
wherein an orthographic projection of the semiconductor layer on the substrate is greater than an orthographic projection of the gate electrode on the substrate.
Yamazaki teaches:
a minimum thickness of the first portion is greater than a minimum thickness of the second portion. [102, Col. 34, Lines 27-33, Fig. 24B]
wherein an orthographic projection of the semiconductor layer [106, Col. 25, Lines 62-67 to Col. 26, Lines 1-7, Fig. 21B] on the substrate [100, Fig. 21B] is greater than an orthographic projection of the gate electrode [104, Col. 25, Lines 62-67 to Col. 26, Lines 1-7, Fig. 21B] on the substrate [100, Fig. 21B].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Yamazaki into the teachings of Morita et al. to include a minimum thickness of the first portion is greater than a minimum thickness of the second portion. Wherein an orthographic projection of the semiconductor layer on the substrate is greater than an orthographic projection of the gate electrode on the substrate, for the purpose of creating more contact surface area, increasing density, preparing feature for subsequent processing, enabling better connections, enhancing electrical performance, and improving performance, efficiency and reliability. See also, MPEP2144.04(VI)(C) Rearrangement of Parts and MPEP2144.04(IV)(A) Changes in Size/Proportion.
Morita et al. and Yamazaki do not teach:
in a cross section, an upper surface of the another portion has an arc edge.
Ito et al. teaches:
in a cross section [Col. 5, Lines 33-40, Fig. 2A2], an upper surface of the another portion has an arc edge [Col. 9, Lines 57-60, Fig. 2A2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ito et al. into the teachings of Morita et al. and Yamazaki to include in a cross section, an upper surface of the another portion has an arc edge, for the purpose of creating more contact surface area, increasing density, preparing feature for subsequent processing, enabling better connections, and enhancing electrical performance.
Morita et al., Yamazaki and Ito et al. do not teach:
wherein a maximum distance between the source electrode and the drain electrode in a direction is equal to a maximum length of the another portion of the semiconductor layer in the direction.
Jung et al. teaches:
wherein a maximum distance between the source electrode [5, paragraph [0049], Fig. 2B] and the drain electrode [6, paragraph [0049], Fig. 2B] in a direction is equal to a maximum length of the another portion of the semiconductor layer [3, paragraph [0049], Fig. 2B] in the direction.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Jung et al. into the teachings of Morita et al., Yamazaki and Ito et al. to include the wherein a maximum distance between the source electrode and the drain electrode in a direction is equal to a maximum length of the another portion of the semiconductor layer in the direction, for the purpose of reducing the size of the channel length between source and drain electrodes, increasing the turn-on current of thin-film transistors and improving their performance. See also MPEP 2144.05 Obviousness of Similar and Overlapping Ranges, Amounts and Proportions.
It should be noted that the limitation “wherein a maximum distance between the source electrode and the drain electrode in a direction is equal to a maximum length of the another portion of the semiconductor layer in the direction” is not new and is a known limitation in the art. The limitation can also be seen in various prior art references such as:
US 20100227442 A1 [Fig. 2F, 3B], JP 2008072011 A [Fig. 3C-4], US 20100155717 A1 [Fig. 4], US 20120119207 A1 [Fig. 3(e)], US 20130009111 A1 [Fig. 1], US 20090142887 A1 [Fig. 3-6, 9-12], and US 20120104384 A1 [Fig. 2, 4-5].
Regarding claim 3, Morita et al., Yamazaki, Ito et al. and Jung et al. teach the electronic device of claim 1.
Morita et al. further teaches:
the first insulating layer [3, paragraph [0129], Fig. 3] is in contact with the semiconductor layer [4, paragraph [0129], Fig. 3].
Regarding claim 4, Morita et al., Yamazaki, Ito et al. and Jung et al. teach the electronic device of claim 3.
Morita et al. further teaches:
wherein the semiconductor layer [4, paragraph [0129], Fig. 3] is disposed between the source electrode [5 (left), Fig. 3] and the gate electrode [2, Fig. 3] and between the drain electrode [5 (right), Fig. 3] and the gate electrode [2, Fig. 3].
Regarding claim 12, Morita et al., Yamazaki, Ito et al. and Jung et al. teach the electronic device of claim 1.
Yamazaki further teaches:
wherein in the cross section, an upper surface of the second portion has an oblique edge and a horizontal edge connected to each other, there is an angle between the oblique edge and the horizontal edge, and the angle is greater than 90 degrees and less than 180 degrees. [See Fig. 24B below]
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MPEP 2125(I) Drawings can be used as prior art: Drawings and pictures can anticipate claims if they clearly show the structure which is claimed. In re Mraz, 455 F.2d 1069, 173 USPQ 25 (CCPA 1972). However, the picture must show all the claimed structural features and how they are put together. Jockmus v. Leviton, 28 F.2d 812 (2d Cir. 1928). The origin of the drawing is immaterial. For instance, drawings in a design patent can anticipate or make obvious the claimed invention as can drawings in utility patents. When the reference is a utility patent, it does not matter that the feature shown is unintended or unexplained in the specification. The drawings must be evaluated for what they reasonably disclose and suggest to one of ordinary skill in the art. In re Aslanian, 590 F.2d 911, 200 USPQ 500 (CCPA 1979). See MPEP § 2121.04 for more information on prior art drawings as "enabled disclosures."
Regarding claim 13, Morita et al., Yamazaki, Ito et al. and Jung et al. teach the electronic device of claim 12.
Yamazaki further teaches:
wherein the oblique edge of the second portion is aligned with a side edge of the source electrode [116a, Fig. 24B] or a side edge of the drain electrode [116b, Fig. 24B].
Regarding claim 21, Morita et al., Yamazaki, Ito et al. and Jung et al. teach the electronic device of claim 1.
Morita et al. further teaches:
wherein the first insulating layer [3, Fig. 3] further has a third portion [Fig. 3], the third portion is defined as a portion not overlapped with the source electrode [5 (left), Fig. 3] and the drain electrode [5 (right), Fig. 3] and overlapped with the gate electrode [2, Fig. 3].
Morita et al., Yamazaki, Ito et al. and Jung et al. disclose the above claimed subject matter.
However, Morita et al., Yamazaki and Jung et al. do not teach:
wherein the first insulating layer further has a third portion, the third portion is defined as a portion not overlapped with the source electrode and the drain electrode and overlapped with the gate electrode, and a minimum thickness of the third portion is equal to the minimum thickness of the first portion.
Ito et al. teaches:
wherein the first insulating layer [402, Col. 6, Lines 3-20; Col. 9, Lines 1-28, Fig. 2A2] further has a third portion, the third portion is defined as a portion not overlapped with the source electrode [405a, Col. 5, Line 40, Fig. 2A2] and the drain electrode [405b, Col. 5, Line 40, Fig. 2A2] and overlapped with the gate electrode [401, Col. 6, Lines 3-6, Fig. 2A2], and a minimum thickness of the third portion is equal to the minimum thickness of the first portion [Fig. 2A2].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ito et al. into the teachings of Morita et al., Yamazaki, Ito et al. and Jung et al. to include wherein the first insulating layer further has a third portion, the third portion is defined as a portion not overlapped with the source electrode and the drain electrode and overlapped with the gate electrode, and a minimum thickness of the third portion is equal to the minimum thickness of the first portion, for the purpose of improving heat dissipation, preventing short circuits, and improving performance. See also, MPEP2144.04(VI)(C) Rearrangement of Parts and MPEP2144.04(IV)(A) Changes in Size/Proportion.
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Morita et al. (US 20150318400 A1), in view of Yamazaki (US 9865743 B2), Ito et al. (US 8741702 B2) and Jung et al. (CN 103618004 A) as applied to claim 1 above, and further in view of Song et al. (US 9443881 B2).
Regarding claim 2, Morita et al., Yamazaki, Ito et al. and Jung et al. teach the electronic device of claim 1.
Morita et al., Yamazaki, Ito et al. and Jung et al. do not teach:
wherein a difference between the minimum thickness of the first portion and the minimum thickness of the second portion is greater than or equal to 0.01 micrometers and less than the minimum thickness of the first portion.
Song et al. teaches:
wherein a difference [g1, Fig. 23] between the minimum thickness [t1, Fig. 23] of the first portion and the minimum thickness [t2, Fig. 23] of the second portion is greater than or equal to 0.01 micrometers and less than the minimum thickness [t1, Fig. 23] of the first portion. [Col. 15, Lines 34-47, Fig. 23]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Song et al. into the teachings of Morita et al., Yamazaki, Ito et al. and Jung et al. to include wherein a difference between the minimum thickness of the first portion and the minimum thickness of the second portion is greater than or equal to 0.01 micrometers and less than the minimum thickness of the first portion, for the purpose of increasing density, and symmetry within the device, and creating better connections between features, therefore improving performance.
Regarding claim 15, Morita et al., Yamazaki, Ito et al., Jung et al. and Song et al. teach the electronic device of claim 2.
Song et al. further teaches:
wherein the second portion [area corresponding to t2, Fig. 23] is a recess of the first insulating layer [140, Col. 15, Lines 34-47, Fig. 23], and a depth [g1, Fig. 23] of the recess is substantially equal to the difference.
Response to Arguments
Applicant’s arguments with respect to independent claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on pages 1-5, Section: Discussion of Claim Rejection under 35 U.S.C. 103, in remarks filed March 11, 2026 that the current prior art of record does not teach the amended limitations of independent claim 1. Examiner agrees with Applicant; However, after a new line of search and consideration of the prior art, the amended limitations of independent claim m1 can be overcome by newly cited reference Jung et al. (CN 103618004 A). It should be noted that the amended limitation is a known limitation in the art and is not new.
Applicant argues on page 5, Section: Discussion of Claim Rejection under 35 U.S.C. 103, in remarks filed March 11, 2026 that due to the amendment to independent claim 1, dependent claims 2-4, 12-13, 15 and 21 should also be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
In summary, the amended limitations of independent claim 1 can be overcome by newly cited reference Jung et al. (CN 103618004 A). All claims directly or indirectly dependent on independent claim 1 are also rejected for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID MICHAEL HELBERG whose telephone number is (571)270-1422. The examiner can normally be reached Mon.-Fri. 8am-5pm EST.
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/D.M.H./Examiner, Art Unit 2815 05/07/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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