Prosecution Insights
Last updated: April 19, 2026
Application No. 17/973,941

SEMICONDUCTOR MODULE

Non-Final OA §103
Filed
Oct 26, 2022
Examiner
EHRLICH, ALEXANDER JOSEPH
Art Unit
2828
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co. Ltd.
OA Round
3 (Non-Final)
64%
Grant Probability
Moderate
3-4
OA Rounds
3y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allow Rate
21 granted / 33 resolved
-4.4% vs TC avg
Strong +57% interview lift
Without
With
+57.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
36 currently pending
Career history
69
Total Applications
across all art units

Statute-Specific Performance

§103
52.7%
+12.7% vs TC avg
§102
21.0%
-19.0% vs TC avg
§112
23.8%
-16.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 33 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/4/25 has been entered. Response to Amendment Examiner acknowledges the amending of claims 1, 5-10, 12-15 and cancellation of claims 2-4, 11, and additional amending of claim 1 in supplemental amendment. Response to Arguments Applicant argues cited prior art does not disclose first protruding portion is disposed closer to one of the pair of short sides than to both of the pair of long sides (Remarks 8/4/25 pg. 2 + Remarks 10/8/25 pg. 1). Examiner agrees. New art is cited to read on this limitation, Jones (US-9888601-B2). Applicant argues cited prior art does not disclose the case part has a partition that partitions the inside of the peripheral portion to define a space in which the plurality of semiconductor elements is disposed (Remarks 8/4/25 pgs. 2-3). Examiner disagrees. Murayama discloses gaps within the case part that function as partitions to define the requisite space. See claim 1 rejection. def. partition (noun) – something that divides (Merriam-Webster def. 2) Applicant argues cited prior art does not disclose the outer periphery of the first protruding portion has a clearance from the inner periphery of the through-hole. Applicant argues that “clearance” inherently requires a non-zero distance (Remarks 8/4/25 pgs. 2-3, EXIN 10/8/25). Examiner agrees. New art is cited to read on this limitation, Yoshiaki (JP-2001102438-A). Applicant argues cited prior art does not make obvious placing the second protrusion portions opposite/diagonal the first protrusion portion (Remarks 8/4/25 pgs. 2-3, Remarks 10/8/25 pg. 1). Examiner agrees. New art is cited to read on this limitation, Yoshiaki (JP-2001102438-A). Applicant argues cited prior art does not disclose the second protruding portion/side surface of base clearance being greater than the first protruding portion/through-hole clearance (8/4/25 Remarks pg. 3). Examiner agrees. Claim 7, 12-15 (and 10 via dependency) 35 USC 103 rejections withdrawn. Claim Objections Claim 5, 8 objected to because of the following informalities: “along the one of the pair of short sides” should read “along . Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5-6, 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Murayama (JP-2020174159-A, machine translation “Murayama_English” cited and included) in view of Jones (US-9888601-B2) and Yoshiaki (JP-2001102438-A, machine translation “Yoshiaki_English” cited and included herewith) Regarding claim 1, Murayama discloses a semiconductor module (fig. 1 10, line 45) comprising: a base part (fig. 1 20 + semiconductor unit (shown in fig. 5 40), lines 45+46) having a plurality of semiconductor elements (fig. 5 45+46, lines 129-130) and a cooling unit configured to cool the plurality of semiconductor elements (fig. 5 41+43a/b+42+44 cools 45+46, lines 141-144); the base part having a rectangular shape with a pair of short sides and a pair of long sides in a plan view (fig. 7 rectangular 20 w/ short sides (top + bottom in fig. 7) and long sides (left + right fig. 7)); and a case part attached to the base part (fig. 1 30 attached to 20 defines interior space for 45+46, lines 45-47) and having a peripheral portion formed in a rectangular frame shape (fig. 7 case part 30 attached to 20 w/ peripheral portion 34a-d in rectangular frame shape, lines 97-101), a partition that partitions inside of the peripheral portion to define a space in which the plurality of semiconductor elements are disposed (fig. 1 30 attached to 20 defines interior space for 45+46 and fig. 5 gaps created by 42+43 serve as partitions defining space for 45+46, lines 45-47 + 129-136 + 167-177); a side wall configured to extend from the peripheral portion and disposed to surround the base part (fig. 7 side wall 32a-d extends from 34a-d to surround 20, lines 175-176), a pair of second protruding portions protruding from the side wall toward a side surface of the base part (fig. 7 36b protrudes from 32c, 36a protrudes from 32a toward side surface of 20, see combined fig. X 2PP), wherein the second protruding portions sandwich a corner of the base part (fig. 7 top left 36b + 36a sandwich top left corner of 20). Murayama does not disclose a through-hole disposed closer to one of the pair of short sides than to both of the pair of long sides; and a first protruding portion protruding from the peripheral portion toward a main surface of the base part and inserted into the through-hole. Jones discloses a semiconductor module arrangement with a base part with a through-hole disposed closer to one of a pair of base short sides than to both of a pair of base long sides (fig. 2 base 300 has through-hole 301 closer to short side than to both long sides, col. 6 lines 50-51), a first protruding portion protruding from a peripheral portion toward a main surface of the base part and inserted into the through-hole (figs. 1C/2 protruding portion 70+71+72 protrudes from peripheral portion of case part 200 toward main surface of the base part (top of 300) and inserted into 301, col. 7 lines 50-55), wherein the first protruding portion has an outer periphery that follows a shape of an inner periphery of the through-hole (figs. 1C/2 70+71+72 has outer periphery following shape of 301 inner periphery). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a through-hole and first protruding portion in the manner required by claim 1 to allow for accurate relative positioning of the components of the device (Jones col. 6 lines 10-30). Placing the through-hole and protruding portion in the peripheral short side region would help avoid interference between hole/protrusion and the centrally-located semiconductor chips + short side protrusion (as opposed to long) would provide stability for the more vulnerable/flexible axis of the rectangular device. Murayama, as modified, does not disclose the first protruding portion outer periphery having a clearance from the inner periphery of the through-hole; and the pair of second protrusions are disposed opposite other one of the pair of short sides and other one of the pair of long sides such that the pair of second protrusions sandwich a corner located diagonally to one corner out of four corners of the base part that is closest to the through-hole. Yoshiaki discloses a substrate housing case with a first protrusion + outer periphery having a clearance from an inner periphery of an associated through-hole (fig. 1+4+5 first protrusion 63 has clearance from inner periphery of through-hole 27A, pg. 7 final 4 paragraphs), and a second protrusion disposed at an opposite corner of the device from the first protrusion + through-hole (fig. 1+4 second protrusion 27B opposite corner from 63 and 27A). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the Jones first protrusion with a clearance from an inner periphery of the through-hole to prevent damage to protrusion/through-hole + increase tolerance while still allowing for sufficient stability (pg 3 [0012] to pg. 4 [0017], pg. 7 second from last par., pg. 10 first 3 par.). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to set the first protrusion at the corner opposite the second “sandwiching” protrusions to allow for more uniform constraint of base/case during thermal expansion, having first and second protrusions on a same side would allow for opposite side to expand more freely putting additional strain on other components. PNG media_image1.png 773 567 media_image1.png Greyscale Combined fig. X Regarding claim 5, Murayama, as modified, discloses the semiconductor module according to claim 1, wherein the first protruding portion has a shape in which a dimension along the one of the pair of long sides of the base part is longer than a dimension along one of the pair of short sides of the base part. def. along (preposition) – in a line next to something long (Cambridge Dictionary def. B1) See annotated fig. 1C + Fig. 1C first protruding portion schematic. Symmetric cylindrical region depicted. Dimension along long side (angled line left to right) longer than dimension along short side (perfectly horizontal line into page) PNG media_image2.png 548 883 media_image2.png Greyscale Annotated fig. 1C PNG media_image3.png 629 860 media_image3.png Greyscale Fig. 1C first protruding portion schematic Regarding claim 6, Murayama, as modified, discloses the semiconductor module according to claim 1, wherein the pair of second protruding portions each have an inclined surface inclined to be lower with respect to the side wall of the case part as getting away from an end side of the side wall of the case part (fig. 8 36b1 inclined to be lower with respect to 32c as it moves away from 32c, lines 230-232+238-242). For claim 6, “second protruding portions” are interpreted to be a plurality of fig. 7 36b. Regarding claim 8, Murayama, as modified, discloses the semiconductor module according to claim 6, wherein the first protruding portion has a shape in which a dimension along the one of the pair of long sides of the base part is longer than a dimension along one of the pair of short sides of the base part. def. along (preposition) – in a line next to something long (Cambridge Dictionary def. B1) See annotated fig. 1C + Fig. 1C first protruding portion schematic. Symmetric cylindrical region depicted. Dimension along long side (angled line left to right) longer than dimension along short side (perfectly horizontal line into page) Regarding claim 9, Murayama, as modified, discloses the semiconductor module according to claim 5, wherein the 36b portions each have an inclined surface inclined to be lower with respect to the side wall of the case part as getting away from an end side of the side wall of the case part (fig. 8 36b1 inclined to be lower with respect to 32c as it moves away from 32c, lines 230-232+238-242). Murayama, as modified, does not disclose wherein the 36a portions each have an inclined surface inclined to be lower with respect to the side wall of the case part as getting away from an end side of the side wall of the case part. It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incline the analogous 36a protrusion surface in the same manner as the 36b1 surface. One of ordinary skill in the art would make this modification to reduce the manufacturing cost + time by making 36a more similar to 36b. Additional inclined surfaces would also make it easier to attach the case to the base and require less force applied to the fragile components of the device. Allowable Subject Matter Claim 7, 10, 12-15 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 7, 12-15: Prior art of record does not disclose second protruding portion clearance being greater than a first protruding portion clearance. Applicant argued in 10/6/25 interview (dated 10/8/25) and 10/8/25 Remarks that “a clearance” between the first protruding portion and the inner periphery of the through-hole inherently requires a non-zero spacing between first protruding portion and inner periphery of through-hole. Examiner agrees. Claim 10: Depends from claim 7 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Ehrlich whose telephone number is (703)756-5716. The examiner can normally be reached M-F 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached on (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /A.E./Examiner, Art Unit 2828 /MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828
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Prosecution Timeline

Oct 26, 2022
Application Filed
Dec 10, 2024
Non-Final Rejection — §103
Mar 26, 2025
Response Filed
Apr 01, 2025
Final Rejection — §103
Aug 04, 2025
Request for Continued Examination
Aug 05, 2025
Response after Non-Final Action
Oct 06, 2025
Examiner Interview Summary
Oct 06, 2025
Applicant Interview (Telephonic)
Oct 21, 2025
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
64%
Grant Probability
99%
With Interview (+57.1%)
3y 4m
Median Time to Grant
High
PTA Risk
Based on 33 resolved cases by this examiner. Grant probability derived from career allow rate.

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