DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7, 10-12, 15, 17 and 18 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wang et al. (US 2020/0083309) hereinafter “Wang”.
Regarding claim 1, Fig. 6B of Wang teaches an electronic device capable of allowing a light to pass through, comprising: a substrate (Item 110); a silicon semiconductor (Item 21; Paragraph 0072) disposed on the substrate (Item 110); a first conductive layer (Item 130c) disposed on the silicon semiconductor (Item 21); an oxide semiconductor (Item 31; Paragraph 0074) disposed on the substrate (Item 110); a second conductive layer (Item 32) disposed on the oxide semiconductor (Item 31), wherein the first conductive layer (Item 130c) comprises a first opening (defined as the space between Items 130c and 22) and the second conductive layer (Item 32) comprises a second opening (defined as the space between Items 32 and TE11), through which the first opening and the second opening the light is allowed to pass; and an opaque structure layer (Item 120) disposed on the substrate (Item 110) and having a third opening (defined as the space between Items TE22 and 120), wherein the third opening is at least partially overlapped with the first opening in a direction vertical to the substrate (Item 110), wherein the third opening is closer to the substrate (Item 110) than the first opening, the first opening is closer to the substrate than the second opening, a width of the third opening is smaller than a width of the first opening, the width of the first opening is smaller than a width of the second opening, and the first opening exposes a portion of the opaque structure layer around the third opening in a top view in the direction vertical to the substrate (Item 110).
Regarding claim 2, Fig. 6B of Wang further teaches where the second opening is at least partially overlapped with the first opening in the direction vertical to the substrate (Item 110).
Regarding claim 3, Fig. 6B of Wang further teaches where the third opening is at least partially overlapped with the first opening and the second opening.
Regarding claim 7, Fig. 6B of Wang further teaches where the silicon semiconductor (Item 21) is disposed on the opaque structure layer (Item 120).
Regarding claim 10, Fig. 6B of Wang further teaches a third conductive layer (Item TE12) disposed on the silicon semiconductor (Item 21), where the third conductive layer (Item TE12) comprises a fourth opening (defined as the space between TE12 and Item 34), and the first opening, the third opening and the fourth opening are at least partially overlapped with each other.
Regarding claim 11, Fig. 6B of Wang further teaches where the third conductive layer (Item TE12) is a single-layered structure.
Regarding claim 12, Fig. 6B of Wang further teaches a third conductive layer (Item 34) disposed on the oxide semiconductor (Item 31), where the third conductive layer (Item 34) comprises a fourth opening (defined as the space between 34 and Item 23), and the first opening, the third opening and the fourth opening are at least partially overlapped with each other.
Regarding claim 15, Fig. 6B of Wang further teaches where the first conductive layer (Item 130c) is a single layered structure.
Regarding claim 17, Fig. 6B of Wang further teaches where the first conductive layer (Item 130c) comprises a first gate electrode which is overlapped with the silicon semiconductor (Item 21).
Regarding claim 18, Fig. 6B of Wang further teaches where the second conductive layer (Item 32) comprises a second gate electrode which is overlapped with the oxide semiconductor (Item 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0083309) hereinafter “Wang” in view of Lee et al. (US 2022/0140041) hereinafter “Lee”.
Regarding claim 13, Wang teaches all of the elements of the claimed invention as stated above except where the third conductive layer is a multi-layered structure.
Lee teaches where a source and drain electrode are multi-layered structure (Paragraph 0144).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the third conductive layer be a multi-layered structure because this is a known to produce a source and drain electrode which has good conductivity (Lee Paragraph 0144).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0083309) hereinafter “Wang” in view of Chung et al. (US 2021/0408182) hereinafter “Chung”.
Regarding claim 16, Wang teaches all of the elements of the claimed invention as stated above except where the second conductive layer is a multi-layered structure.
Chung teaches where a gate electrode is multi-layered structure (Paragraph 0137).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the second conductive layer be a multi-layered structure because this is a known to produce a gate electrode (Chung Paragraph 0137).
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2020/0083309) hereinafter “Wang” in view of SO (US 2022/0209068) hereinafter “So”.
Regarding claim 19, Wang teaches an electronic module comprising: the electronic device as claimed in claim 1 (For brevity the entirety of the rejection of claim 1 will not be repeated here; See the rejection of claim 1 above);
Wang does not teach a sensor disposed underneath the electronic device and configured to receive the light.
So teaches a sensor (Item 200) disposed underneath an electronic device and configured to receive light (Paragraph 0038).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have a sensor disposed underneath the electronic device and configured to receive the light because this allows for a camera to be integrated with the electronic device (So Paragraph 0043).
Regarding claim 20, Wang does not teach where the sensor is a fingerprint sensor or an image sensor.
So teaches a sensor (Item 200), where the sensor is an image sensor (Paragraph 0043).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the sensor be an image sensor because this allows for a camera to be integrated with the electronic device (So Paragraph 0043).
Allowable Subject Matter
Claims 4, 6 and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 4, the prior art of record fails to teach, suggest or motivate one having ordinary skill in the art to have the first opening be a pinhole.
Regarding claim 6, the prior art of record fails to teach, suggest or motivate one having ordinary skill in the art to have the third opening is a pinhole.
Regarding claim 8, the prior art of record fails to teach, suggest or motivate one having ordinary skill in the art to have the opaque structure layer is disposed between the silicon semiconductor and the oxide semiconductor.
Response to Arguments
Applicant’s arguments, see Applicant’s REMARKS/ARGUMENTS, filed 02/12/2026, with respect to the rejection(s) of claim(s) 1 under 35 USC 103(a) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wang.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC K ASHBAHIAN whose telephone number is (571)270-5187. The examiner can normally be reached 8-5:30 PM.
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/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891
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