Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to
determine the presence of all possible minor errors. Applicant's cooperation is
requested in correcting any errors of which applicant may become aware in the
specification.
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The entire reference is considered to provide disclosure relating to the claimed invention. The claims & only the claims form the metes & bounds of the invention. Office personnel are to give the claims their broadest reasonable interpretation in light of the supporting disclosure. Unclaimed limitations appearing in the specification are not read into the claim. Prior art was referenced using terminology familiar to one of ordinary skill in the art. Such an approach is broad in concept and can be either explicit or implicit in meaning. Examiner's Notes are provided with the cited references to assist the applicant to better understand how the examiner interprets the applied prior art. Such comments are entirely consistent with the intent & spirit of compact prosecution.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5, 7, 8, 15-16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kiffe et al (US 2018/0365361 A1), hereinafter Kiffe, in view of Kale et al (US 2022/0358349 A1), hereinafter Kale.
Claim 1. An electrical system simulation method comprising:
Kiffe discloses obtaining a model of an electrical system comprising a plurality of subcircuits; assigning each of the plurality of subcircuits to a processing core from among a plurality of processing cores employed for simulation of the model;
Kiffe [0025] “Embodiments of the invention provide computer-implemented methods for simulation of electrical circuits with circuit components by at least one computing unit, [correspond to model of an electrical system] whereby the electrical circuit is mathematically described by an overall state space representation, with the overall circuit being separated into two subcircuits in a separation step that consists of the separation of branch circuits, whereby each subcircuit is mathematically described by a substate space representation, whereby the substate space representations are coupled with each through coupling variables of the separated branch circuits and each subcircuit is calculated by numerically solving the coupled substate space representations on the at least one computing unit. [correspond to assigning each of the plurality of subcircuits to a processing core]”
Kiffe discloses executing a simulation of behaviors of the model,
Kiffe [0027] “A computing unit with which the simulation is performed can be part of a controller or an HIL simulator, which each comprise an I/O interface. By means of the I/O interface, electrical signals can be imported or exported, with the electrical signals being low-voltage analog or digital communication engineering signals. In the case of electronic power applications, the I/O interface can also be used to transfer considerable electrical power, for example to control electric motors. This means that selected, calculated output values of the electrical circuit are emitted as electrical signals by means of the I/O interface in such a way that they influence a technical-physical process. [correspond to behavior of the electrical model] Additionally or alternatively, process values of the technical-physical process are recorded and imported in the form of electrical signals by means of the I/O interface and made available to the computing unit. The simulation therefore has a direct influence on the physical world.”
Kiffe discloses sending a message, from a first processing core assigned to a first subcircuit to a second processing core assigned to a second subcircuit
Kiffe [0027] “A computing unit with which the simulation is performed can be part of a controller or an HIL simulator, which each comprise an I/O interface. By means of the I/O interface, electrical signals can be imported or exported, with the electrical signals being low-voltage analog or digital communication engineering signals. [correspond to message] In the case of electronic power applications, the I/O interface can also be used to transfer considerable electrical power, for example to control electric motors. This means that selected, calculated output values of the electrical circuit are emitted as electrical signals by means of the I/O interface in such a way that they influence a technical-physical process. Additionally or alternatively, process values of the technical-physical process are recorded and imported in the form of electrical signals by means of the I/O interface and made available to the computing unit. The simulation therefore has a direct influence on the physical world.”
Kiffe discloses the message comprising one or more boundary conditions at an interface between the first subcircuit and the second subcircuit in the model.
Kiffe [0027] “A computing unit with which the simulation is performed can be part of a controller or an HIL simulator, which each comprise an I/O interface. By means of the I/O interface, electrical signals can be imported or exported, with the electrical signals being low-voltage analog or digital communication engineering signals. In the case of electronic power applications, the I/O interface can also be used to transfer considerable electrical power, for example to control electric motors. This means that selected, calculated output values of the electrical circuit are emitted as electrical signals by means of the I/O interface in such a way that they influence a technical-physical process. Additionally or alternatively, process values of the technical-physical process are recorded and imported in the form of electrical signals by means of the I/O interface and made available to the computing unit. The simulation therefore has a direct influence on the physical world.”
In light of applicant’s specification [0043] and [0066], examiner interpret “boundary condition at an interface” as “current and voltage between subcircuits” or “electrical signal between circuits”.
Kiffe does not appear to explicitly disclose wherein the simulation of each subcircuit is executed by the respective processing core assigned to the subcircuit;
However, Kale discloses wherein the simulation of each subcircuit is executed by the respective processing core assigned to the subcircuit;
Kale: [0034] “The control circuitry 106 can also include assigning circuitry 108. In some embodiments, the assigning circuitry 108 can comprise an ASIC configured to assign DLA cores to one or more subsets of DLA cores as described herein. In some embodiments, the assigning circuitry 108 can represent functionality of the control circuitry 106 that is not embodied in separate discrete circuitry. The control circuitry 106 and/or the assigning circuitry 108 can be configured to assign execution of a DLA model to one or more DLA cores of a DLA chip (represented by the memory array 110). The control circuitry 106 and/or the assigning circuitry 108 can be configured to assign execution of a first DLA model to a first subset of DLA cores and execution of a second DLA model to a second subset of DLA cores. The control circuitry 106 and/or the assigning circuitry 108 can be configured to assign a quantity of DLA cores to a subset based on processing requirements of a DLA model to be executed by the executed by the subset of DLA cores. The control circuitry 106 and/or the assigning circuitry 108 can be configured to receive user-defined subsets of DLA cores and/or user-defined quantities of DLA cores.”
Kiffe and Kale are analogous art because they are from the “same field of endeavor” modeling analysis.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Kiffe and Kale before him or her, to modify thethe method of Kiffe to include the assigning core feature of Kale because this combination utilizing the computational resource efficiently.
The suggestion/motivation for doing so would have been Kale: [0017] “Aspects of the present disclosure address the above and other deficiencies. For instance, execution of various DLA models can be assigned to subsets of DLA cores of a DLA chip. The quantity of DLA cores assigned to execute a DLA model can be based on the computational capability and/or processing requirements of the DLA model. Some embodiments of the present disclosure provide post-manufacturing flexibility not available in previous approaches. For example, the quantity of DLA cores of a DLA chip assigned to a subset and/or the quantity of subsets can be modified in response to modification of workloads and/or DLA models. Subsets of DLA cores can be configured on-demand (“on-the-fly”) at any time. An advantage of some embodiments described herein is an ability for on-demand workload aware compute deployment, utilization, and/or management. Computational capability of a DLA chip can be available on-demand and is scalable to satisfy changing requirements of deep-learning edge applications.”
Therefore, it would have been obvious to combine Kiffe and Kale to obtain the invention as specified in the instant claim(s).
Regarding Claim 15, the same ground of rejection is made as discussed above for substantially similar rationale.
In addition, Claim 15 recites “A system comprising: at least one processor; and a data store coupled to the at least one processor having instructions stored thereon which, …”.
Kiffe discloses A system comprising: at least one processor; and a data store coupled to the at least one processor having instructions stored thereon which, on [0007] The computing units may be several processor cores, but also several processors of a multiprocessor system, which is quite frequently the case in larger HIL simulators. It is also possible that a computing unit or several computing units, respectively, is/are realized on the basis of one (or more) FPGA (field programmable gate arrays), which has speed benefits but also creates difficulties with regard to certain numerical operations such as divisions.
Regarding Claim 20, the same ground of rejection is made as discussed above for substantially similar rationale.
In addition, Claim 20 recites “A non-transitory computer readable storage medium storing instructions that, when executed by at least one processor, cause the at least one processor to perform operations comprising: …”.
Kiffe discloses one or more non-transitory computer-readable media storing program instructions and processor on [0007] The computing units may be several processor cores, but also several processors of a multiprocessor system, which is quite frequently the case in larger HIL simulators. It is also possible that a computing unit or several computing units, respectively, is/are realized on the basis of one (or more) FPGA (field programmable gate arrays), which has speed benefits but also creates difficulties with regard to certain numerical operations such as divisions.
Claim 2 and 16
Kiffe discloses evaluating one or more electrical components in the model of the electrical system;
Kiffe [0028] “… Methods according to embodiments of the invention are based on substate space representations, which are coupled with each other by a coupling equation system to exchange the calculated coupling variables. In the subsequent evaluation step, at least one stability parameter is calculated for the simulation on the basis of the coupling equation system. Thus, an evaluation of the separation of the overall circuit into subcircuits is performed on the basis of systems theory. This evaluation may be of a traditional systems theory nature in the form of the determination of eigenvalues of the substate space representation obtained due to the separation, which are coupled with one another by means of the coupling equation. It may, however, be numerical considerations that are based on this mathematical representation when certain numerical methods for solving the equation system obtained from the separation of the overall circuit are considered. In addition, certain delay effects may be included in the coupling equation system, which go hand in hand with the numerical solution of the subsystems and the exchange of the couple variables. Ultimately, however, a theoretical stability consideration is performed in any case without a simulation on the basis of separated subcircuits being necessary.”
Kiffe discloses based on the evaluation of the one or more electrical components in the model of the electrical system, partitioning the model into the plurality of subcircuits
Kiffe [0030] “If the separation of the overall circuit is not rejected, however, i.e., if a successful selection is made, the simulation of the electrical circuit is performed by calculating the substate representations that were previously evaluated numerically and in accordance with systems theory on the at least one computing unit. In contrast with methods known from prior art, a reliable selection of a certain separation of the overall circuit into subcircuits is performed here on the basis of systems theory and/or numerical consideration, so that the simulation of the functionality of the overall circuit on the basis of the subcircuits is reliable as well, and a basic stability requirement or even a requirement regarding the precision of the calculation can be guaranteed from the start. …”
Claims 5 and 19
Kale discloses wherein executing the simulation of electric grid behaviors of the model comprises: executing the simulation of the first subcircuit on by the first processing core according to a first set of simulation parameters; and executing the simulation of the second subcircuit on the second processing core according to a second, different set of simulation parameters.
Kale: [0067] “In some embodiments, the instructions 692 include instructions to implement functionality corresponding to the host 102 and/or the memory device 104. The instructions 692 can be executed to cause the machine to assign a first quantity of a plurality of DLA cores of a physical DLA chip to a first virtual DLA chip based on a first processing requirement of a first DLA model and assign a second quantity of the plurality of DLA cores of the physical DLA chip to a second virtual DLA chip based on a second processing requirement of a second DLA model. The instructions 692 can be executed to cause the machine to execute the first DLA model using the first virtual DLA chip and execute the second DLA model using the second virtual DLA chip. The instructions 692 can be executed to cause the machine to assign a greater quantity of the plurality of DLA cores to the first virtual DLA chip than to the second virtual DLA chip in response to the first processing requirement being greater than the second processing requirement. The instructions 692 can be executed to cause the machine to assign a lesser quantity of the plurality of DLA cores to the first virtual DLA chip than to the second virtual DLA chip in response to the second processing requirement being greater than the first processing requirement.”
Claim 7. The method of claim 1, Kiffe discloses wherein the one or more boundary conditions of the first subcircuit include simulation output, generated by the first processing core, for electrical conditions at the interface.
Kiffe [0027] “A computing unit with which the simulation is performed can be part of a controller or an HIL simulator, which each comprise an I/O interface. By means of the I/O interface, electrical signals can be imported or exported, with the electrical signals being low-voltage analog or digital communication engineering signals. In the case of electronic power applications, the I/O interface can also be used to transfer considerable electrical power, for example to control electric motors. This means that selected, calculated output values of the electrical circuit are emitted as electrical signals by means of the I/O interface in such a way that they influence a technical-physical process. Additionally or alternatively, process values of the technical-physical process are recorded and imported in the form of electrical signals by means of the I/O interface and made available to the computing unit. The simulation therefore has a direct influence on the physical world.”
Claim 8. The method of claim 7, Kiffe discloses wherein the electrical conditions include one or more of: a current value at the interface, a voltage value at the interface, a simulation time step at which the current and voltage values were simulated, and a propagation delay between the first subcircuit and the second subcircuit.
Kiffe [0027] “A computing unit with which the simulation is performed can be part of a controller or an HIL simulator, which each comprise an I/O interface. By means of the I/O interface, electrical signals can be imported or exported, with the electrical signals being low-voltage analog or digital communication engineering signals. In the case of electronic power applications, the I/O interface can also be used to transfer considerable electrical power, for example to control electric motors. This means that selected, calculated output values of the electrical circuit are emitted as electrical signals by means of the I/O interface in such a way that they influence a technical-physical process. Additionally or alternatively, process values of the technical-physical process are recorded and imported in the form of electrical signals by means of the I/O interface and made available to the computing unit. The simulation therefore has a direct influence on the physical world.”
Allowable Subject Matter
Claims 3, 4, 6, 9-14 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Kiffe et al (US 2018/0365361 A1) teaches a method for simulation of an electrical circuit with circuit components by at least one computing unit includes mapping a coupling of the substate representations in a coupling equation system for exchange of calculated coupling variables between the subcircuits. The method also includes calculating, in an evaluation step, at least one stability parameter on a basis of the coupling equation system, and deciding, in a selection step and depending on the at least one calculated stability parameter, whether the current separation of the electrical circuit into subcircuits will be used as the basis of the simulation. The method further includes performing, after a successful selection, the simulation of the electrical circuit by calculating the substate space representations on the at least one computing unit.
Kale et al (US 2022/0358349 A1) teaches the feature of assigning model to different processing cores [0034].
Khalilinia et al (NPL: Fast Frequency-Domain Decomposition for Ambient Oscillation Monitoring, 2015) teaches analysis feature of suing different time windows.
These references taken either alone or in combination with the prior art of record fail to disclose limitations, including:
Claim 3 and 17
determining one or more propagation delays between the plurality of subcircuits; and wherein partitioning the model into the plurality of subcircuits is further based on the one or more propagation delays between the plurality of subcircuits.
Claim 6. The method of claim 5, wherein the first set of simulation parameters comprise a first simulation time step size and the second set of simulation parameters comprise a second, different simulation time step size.
Claim 9. The method of claim 1, wherein executing a simulation of the behaviors of the model comprises: completing a simulation of the first subcircuit up until a simulation time step tn, wherein the message comprises boundary conditions at the interface between the first subcircuit and the second subcircuit at simulation time step tn; and in response to receiving the message, executing, by the second processing core, simulation of electric grid behaviors of the model in the second subcircuit for simulation time step t1i.
Claim 10. The method of claim 1, wherein each subcircuit of the plurality of subcircuits has a default time step size, the method further comprising:
identifying a transient behavior in the first subcircuit at a simulation time step tn;
reducing, by the first processor, a time step size of the first subcircuit to less than the default time step size; and continuing to execute simulation of the first subcircuit with the reduced time step size and the second subcircuit with the default time step size for simulation time steps greater than simulation time step tn.
Claim 14. The method of claim 1, wherein executing a simulation of the behaviors of the model comprises: completing a simulation of the first subcircuit up until a simulation time step to-1, wherein the message comprises boundary conditions at the interface at the simulation time step to-1;in response to receiving the message comprising the simulation time step tn-i, estimating, by the second processing core, values for the boundary conditions at the interface at a simulation time step to in the first subcircuit; and continuing to execute, using the estimated values, simulation the first subcircuit for simulation time steps greater that tn.
in combination with the remaining elements and features of the claimed invention.
Conclusion
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/CHUEN-MEEI GAN/Primary Examiner, Art Unit 2189