DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s election with traverse of the restriction requirement set forth on 04/07/26 in the reply on 07/06/26 is acknowledged. Applicant asserts that the three groups are related because Group I recites a DPD circuit, Group II recites arithmetic blocks, and Group III recites a Hermitian matrix (remarks p. 8). In support, Applicant asserts that because Groups I and II are both classified under G06F7/57 they overlap (remarks p. 9). Further claim 7 recites M matrix memories configured so that the M elements can be read in parallel in a single clock cycle – the identical functional outcome achieved by the Hermitian matrix memory of Group III. (remarks p. 9)
Examiner respectfully disagrees. While both groups II and III may be related in that they reference matrices, the specific claim limitations with respect to those matrices are different. Group II requires no Hermitian matrix, hence the groups to not overlap in scope.
Applicant further asserts that all three groups are capable of use together in a unified system as in figure 4 (remarks p 9).
Examiner respectfully disagrees. Applicant has provided no argument how the claims of each group are reflected in figure 4 and how they are usable together.
Applicant further asserts Examiner has failed to provide any explanation as to how the three groups have a materially different design, mode of operation, function or effect (remarks p. 9)
Examiner respectfully disagrees. Group I function is as a digital pre-distortion circuit. Group II function is an arithmetic block. Group III function is as a clocked Hermitian matrix memory. These are each a different function.
The requirement is still deemed proper and is therefore made FINAL.
Supplemental Reply
The supplemental reply filed on 07/09/26 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, and 5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites that the instruction decode block is configured to decode instructions specifying one or more of followed by three options modified by the modifier “or”. It is unclear whether the apparatus must be “configured to” perform inclusive of only one of the options, or is configurable to perform between one and three of the options. For purposes of examination, Examiner interprets as the apparatus may be configured to perform only one of the options.
Claim 5 recites “wherein different pairs of the vector memories are configured to store real parts and imaginary parts of different complex vectors”. It is unclear whether the different pairs each store only one of the real part or the imaginary part, or both store real and imaginary parts but different vector values or other. For purposes of examination, Examiner interprets as the different pairs of vector memories each store different vector values that may be both real and imaginary parts.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over US 20180115332 A1 Kishibe (hereinafter “Kishibe”) in view of US 20150023451 A1 Muhammad (hereinafter “Muhammad”).
Regarding claim 1, Kishibe teaches the following:
an output terminal adapted to couple to an input of a power amplifier (fig 1 input to device 9);
a feedback terminal adapted to couple to an output of the power amplifier (fig 1 from output of 9 to input of 11);
a data terminal adapted to receive a data stream (input to 2, 3, and 21);
a digital pre-distortion (DPD) circuit including:
a capture circuit including a first input coupled to the data terminal, a second input coupled to the feedback terminal, and an output (fig 1 delayer 21, delay detector 23, with first input coupled to the data terminal, second input coupled to feedback terminal 11 through 13, 12, and 11, and output to 20)
a DPD estimator including an input coupled to the output termina of the capture circuit, and an output (fig 1 22), the DPD estimator including:
a vector arithmetic processing unit (APU) (fig 1 22, fig 2 22, fig 3), including:
multiple vector memories (fig 3 42a, 42b [0064]);
multiple vector arithmetic blocks, including multiple vector addition blocks and multiple vector multiplication blocks (fig 3 52, 53 54, 56, [0063], [0065-0066]); and
the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories ([0057], [0059], [0063-0064], [0066]); and
a DPD corrector including a first input coupled to the data terminal, a second input coupled to the output of the DPD estimator, and an output coupled to the output terminal (fig 1 2, [0059]).
Kishibe discloses a controller including a CPU, RAM and ROM including programs to control the apparatus. Kishibe does not, however, explicitly disclose an instruction memory configured to store multiple instructions, wherein the instruction memory is coupled to the APU, an instruction decode block to cause the APU to perform the complex domain vector arithmetic in response to instructions. However, in the same field of endeavor Muhammad discloses an apparatus similar to Kishibe for perform predistortion in power amplifiers (abstract, fig 1). Muhammad further discloses instructions stored in a memory, which are retrieved, decoded and executed by a processor, wherein the instructions are derived from arithmetic (algorithmic) constructions to perform the predistortion disclosed ([0062]). It would have been obvious to one of ordinary skill in the art before the effective filing date to use the instruction memory storing instructions as in Muhammed to decode those instructions as in Muhammad to cause the APU of Kishibe to perform complex domain vector arithmetic on vector stored in the vector memories of Kishibe in response to the instructions as in Muhammad. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141.III.(A).
Regarding claim 2, in addition to the teachings addressed in the claim 1 analysis, Kishibe teaches the following:
wherein the instruction decode block is configured to decode instructions specifying one or more of: multiplication of a complex vector stored in the vector memories by a complex matrix stored in a memory external to the vector APU (LUT for memory external to the vector APU, [0059], vector for 1 dimensional matrix, with instruction decode as in the claim 1 mapping), a dot product of two complex vectors stored in the vector memories, a complex vector stored in the external memory plus a scalar stored in a register memory of the vector APU multiplied by a complex vector stored in the vector memories, or a complex vector stored in the vector memories plus a scalar stored in a register memory of the vector APU multiplied by a complex vector stored in the vector memories.
Regarding claim 3, in addition to the teachings addressed in the claim 1 analysis, Kishibe teaches the following:
further including a matrix memory external to the vector APU and configured to store a complex matrix (LUT for memory external to the vector APU, [0059], vector for 1 dimensional matrix);
wherein the instruction decode block is configured to decode an instruction that specifies reading of the complex matrix from the matrix memory, and multiplication of the complex matrix by a complex vector stored in the vector memories ([0059] with the instruction decode limitations as in the claim 1 mapping).
Regarding claim 5, in addition to the teachings addressed in the claim 1 analysis, Kishibe teaches the following:
wherein different pairs of the vector memories are configured to store real parts and imaginary parts of different complex vectors (fig 3, [0064], [0057], 42a, 42b different pairs storing different parts, real and imaginary of complex vectors Sd(t) and Sd*(t) r(t)).
Claim 4 is rejected under 35 USC 103 under as being unpatentable over Kishibe in view of Muhammad in view of US 20220197640 A1 Azadet et al., (hereinafter “Azadet”).
Regarding claim 4, in addition to the teachings addressed in the claim 1 analysis, Kishibe in view of Muhammad teach the claim 1 limitations. Kishibe in view of Muhammad teach passing instructions to the instruction decode block as in the claim 1 analysis. Both Kishibe and Muhammad are silent with respect to a sequencer. However, in the same field of endeavor, Azadet discloses an apparatus for calculating digital pre-distortion coefficients for use with radio frequency transmitter chains (abstract). Azadet further discloses a sequencer which selects instructions from memory for execution ([0039]). It would have been obvious to one of ordinary skill in the art before the effective filing date to use Azadet’s sequencer in conjunction with the instruction and decode block of Kishibe in view of Muhammad to select instruction s from the instruction memory in order to pass the instructions to the instruction decode block for execution. It is obvious to use a known technique to improve similar devices in the same way. See MPEP 2141.III.(A).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached on 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
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/EMILY E LAROCQUE/Examiner, Art Unit 2182
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