DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 7-9, filed 11/6/25, with respect to the rejection(s) of claim(s) 12-20 under 35 U.S.C. 102(a)(1) as anticipated by Ishizaka (US 2015/0063801 A1), have been fully considered and are unpersuasive.
The claimed terms “layer” and “coplanar” are broad in the art, so as to refer to a commonly bounded space. For example, the cladding 3 of Figure 3 in Ishizaka bounds a region of space considered to be a “layer” or “plane” so as to define a common layer or plane for optical input, optical output, and floating gate waveguide. The same is consistent with the ordinary meaning of the claims, as the claims fail to specifically define the boundaries of the claimed layer or plane. For these reasons, the rejection is maintained. This Action is FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ishizaka (US 2015/0063801 A1).
Re. Claim 12, Ishizaka discloses a nonvolatile memory for a photonic circuit ([0019]-[0020]), the nonvolatile memory comprising:
a layer comprising:
an optical input 12/13 (Fig. 3; [0031]);
an optical output 9/10 (Fig. 3; [0031]);
a floating gate waveguide 5/11 (Figs. 1-3; [0031], [0034]);
a control gate 6/7 (Figs. 1-3; [0031]);
a source gate 14 (Figs. 1-3; [0031]);
a first isolation coupler optically coupling the optical input 12/13 to the floating gate waveguide 5/11, the first isolation coupler conductively decoupling the floating gate waveguide 5/11 from the optical input 12/13 (Fig. 2; [0033]); and
a second isolation coupler optically coupling the floating gate waveguide 12/13 to the optical output 9/10, the second isolation coupler conductively decoupling the floating gate waveguide 5/11 from the optical input 12/13 (Fig. 2; [0033]);
wherein the floating gate waveguide 5/11 is configured to accumulate and retain electrical charge supplied by the source gate 14 in response to a voltage applied to the control gate 6/7 (Fig. 2; [0034]-[0035]).
Re. Claim 13, Ishizaka discloses the floating gate waveguide 5/11 is a portion of an interferometer or a resonator (Figs. 3-4; [0030]-[0031], [0042]).
Re. Claim 14, Ishizaka discloses accumulated charge in the floating gate waveguide influences a behavior of the interferometer or the resonator ([0039]), [0045]).
Re. Claim 15, Ishizaka discloses the first isolation coupler comprises a gap (Fig. 2; [0034]).
Re. Claim 16, Ishizaka discloses the second isolation coupler comprises a tapered gap (Figs. 3-4).
Re. Claim 17, Ishizaka discloses the floating gate waveguide 5/11 is formed from a semiconductor ([0031]).
Re. Claim 18, Ishizaka discloses nonvolatile memory for a photonic circuit ([0019]-[0020]), the nonvolatile memory comprising:
a floating gate waveguide 5/11 (Figs. 1-3; [0031], [0034]);
a control gate 6/7 (Figs. 1-3; [0031]);
a source gate 14 (Figs. 1-3; [0031]);
a first isolation coupler conductively isolating the floating gate waveguide 5/11 from the control gate 6/7 and the source gate 14 (Fig. 2; [0033]); and
a second isolation coupler conductively isolating the floating gate waveguide 5/11 from the control gate 6/7 and the source gate 14 (Fig. 2; [0033]);
wherein the floating gate waveguide 5/11 is configured to accumulate and retain electrical charge supplied by the source gate 14 in response to a voltage applied to the control gate 6/7 (Fig. 2; [0034]-[0035]).
Re. Claim 19, Ishizaka discloses the floating gate waveguide 5/11 is formed from a semiconductor material ([0031]).
Re. Claim 20, Ishizaka discloses the floating gate waveguide 5/11 is optically coupled to a photonic circuit ([0020]).
Re. Claim 21, Ishizaka discloses the optical input 12/13, optical output 9/10, and floating gate waveguide 5/11 are coplanar with one another (Fig. 3). For example, all elements are contained within the plane defined by layer 3.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RHONDA S PEACE/Primary Examiner, Art Unit 2874 12/15/25