Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see page 8-9, filed 05/11/2026, with respect to the rejection(s) of claim(s) 1-3, 5, 7-8, 10-11, 13-16 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of IM (KR20220054078).
Allowable Subject Matter
Claims 17-18 and 20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Claim 17, for which Claims 18 and 20 depends, teaches limitations: “an impedance transformer embedded in the second PCB and configured to match an output of the power amplifier; and a die shield on the power amplifier configured to limit electromagnetic coupling between the power amplifier and the impedance transformer” that is not taught in the prior art of record and in further search.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981).
It must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Claim(s) 1, 5, and 7 and is/are rejected under 35 U.S.C. 103 as being unpatentable over NII (US6335669) in view of FURUTANI (WO2022071006) and in further view of IM (KR20220054078).
Regarding Claim 1. (Original) NII teaches, in Fig. 3-8, a device, comprising: a first printed circuit board (PCB) (101), including a first cavity (4) in a first surface of the first PCB (see Fig. 3-8); a power amplifier (19) mounted in the first cavity; and a second PCB (102) mounted to the first surface and mounted over the first cavity (see Fig. 3-8), but does not disclose a first mold including a molding material at the first surface of the first PCB, wherein the first mold encloses the second PCB and electrical components mounted to the first surface of the first PCB and the second PCB and a second mold including the molding material at a second surface of the first PCB, wherein the second mold encloses electrical components mounted to the second surface of the first PCB.
FURUTANI discloses, in Fig. 1B/C, a first mold (72) including a molding material at the first surface of the first PCB (30), wherein the first mold encloses the second PCB (assume 20, see also Nii reference) and electrical components (60, see also Nii reference, also obvious to have components mounted to surfaces in PCB) mounted to the first surface of the first PCB and the second PCB.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by NII with the mold as disclosed by FURUTANI in order to protect the electrical components by sealing as it is known in the art (FURUTANI, translation page 4 paragraph 5-8, translation page 9 paragraph 3) .
IM teaches, in Fig. 1-3, a second mold (126) including the molding material at a second surface (110b) of the first PCB (110) (see Fig.2 and 3), wherein the second mold encloses electrical components (123- duplication of parts) mounted to the second surface of the first PCB.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by NII and FURUTANI with the second mold as disclosed by IM in order to fix a signal terminal processing problem (IM, Background Art) .
Regarding Claim 5. (Original) Nii, FURUTANI, and IM teaches the device of claim 1, further comprising: an electrical joint (Nii, 118,119,5) located on a second surface of the first PCB (see Nii, Fig. 3-8) and at a location on the second surface opposite the power amplifier (Nii, see Fig. 3-8); and a via (Nii, 8 below) electrically connecting an amplified output from the power amplifier to the electrical joint (Nii, see Fig. 3-8).
Regarding Claim 7. (Original) Nii, FURUTANI, and IM teaches the device of claim 1, wherein the first PCB is comprised of a plurality of insulating layers (Nii, See Fig. 3-8), and a depth of the first cavity includes a thickness of at least one of the plurality of insulating layers (Nii, see Fig. 3-8).
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US6633005) in view of FURUTANI (WO2022071006) in further view of IM (KR20220054078).
Regarding Claim 1. (Original) Wang teaches, in Fig. 4,5, and 7, a device, comprising: a first printed circuit board (PCB) (18a, 18b, 18c), including a first cavity (22) in a first surface of the first PCB (see Fig. 4 ,5 ,7); a power amplifier (24) mounted in the first cavity; and a second PCB (18d) mounted to the first surface and mounted over the first cavity (see Fig. 4,5, 7), but does not disclose a first mold including a molding material at the first surface of the first PCB, wherein the first mold encloses the second PCB and electrical components mounted to the first surface of the first PCB and the second PCB and a second mold including the molding material at a second surface of the first PCB, wherein the second mold encloses electrical components mounted to the second surface of the first PCB.
FURUTANI discloses, in Fig. 1B/C, a first mold (72) including a molding material at the first surface of the first PCB (30), wherein the first mold encloses the second PCB (assume 20, see also Nii reference) and electrical components (60, see also Nii reference, also obvious to have components mounted to surfaces in PCB) mounted to the first surface of the first PCB and the second PCB.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by NII with the mold as disclosed by FURUTANI in order to protect the electrical components by sealing as it is known in the art (FURUTANI, translation page 4 paragraph 5-8, translation page 9 paragraph 3).
IM teaches, in Fig. 1-3, a second mold (126) including the molding material at a second surface (110b) of the first PCB (110) (see Fig.2 and 3), wherein the second mold encloses electrical components (123- duplication of parts) mounted to the second surface of the first PCB.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Wang and FURUTANI with the second mold as disclosed by IM in order to fix a a signal terminal processing problem (IM, Background Art) .
Regarding Claim 2. Wang, FURUTANI and IM teaches the device of claim 1, wherein the power amplifier is configured to amplify radio frequency signals (RF amplifier, implicit) and the device further comprises a first circuit (Wang, 34a, 38) mounted to the second PCB wherein the first circuit is electrically connected to the power amplifier (used for output matching so there should be a connection)
Regarding Claim 3. Wang, FURUTANI and IM teaches the device of claim 2, wherein the first circuit includes at least one of: a bias circuit mounted to the second PCB and electrically connected to the power amplifier; or a single-ended output matching circuit mounted to the second PCB and electrically connected to the power amplifier (Wang, column 8 lines 35-42).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nii, FURUTANI, and IM in view of Ida (US7119004).
Regarding Claim 8. (Original) Nii, FURUTANI, and IM teaches the device of claim 1, wherein the power amplifier is mounted in the first cavity (Nii,4) at a joint between a first surface (Nii, bottom surface) of the power amplifier and a surface in the first cavity (Nii, see Fig. 3-8), but does not teach the device further comprises: an electromagnetic coupling shield coupled to a second surface of the power amplifier opposite the first surface of the power amplifier.
Ida teaches, in Fig. 10, an electromagnetic coupling shield (4) coupled to a second surface of the power amplifier (2) opposite the first surface (bottom surface) of the power amplifier.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Nii, FURUTANI, and IM with the shield as disclosed by Ida in order to protect the power amplifier from external electrical noise as it is known in the art.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nii, FURUTANI, and IM in view of Wang (US6633005).
Regarding Claim 10. Nii, FURUTANI, and IM teaches the device of claim 1, but does not teach further comprising: an electromagnetic interference (EMI) shield enclosing the first mold, a side surface of the first PCB.
WANG teaches, in Fig. 4, an electromagnetic interference (EMI) shield (46) enclosing the first mold (see FURATANI), a side surface of the first PCB (18a-18c) (see Fig. 4).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Nii, FURUTANI, and IM with the shield as disclosed by WANG in order to provide additional RF grounding and EMI shielding (Wang, column 7 lines 38-42).
Claim(s) 11, 13, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nii, FURUTANI, and IM in view of KAJIWARA (JP2018085375).
Regarding Claim 11 (Original) Nii, FURUTANI, and IM teaches the device of claim 1, wherein the second PCB is mounted at a joint between the first surface of the first PCB and a second surface of the second PCB (NII, see Fig. 3-8), but does not teach the device further comprises: a solder resist layer attached to the second surface of the second PCB and coupled to a first surface of the second PCB opposite the second surface of the second PCB.
Kajiwara teaches, in Fig. 2 and 11, a solder resist layer (43) attached to the second surface of the second PCB (40) and coupled to a first surface of the second PCB opposite the second surface of the second PCB (see Fig. 2, 11).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Nii, FURUTANI, and IM with the solder resist layer as disclosed by Kajiwara in order to act as a barrier to the circuit board and provide a barrier to excess solder as it is known in the art.
Regarding Claim 13. Nii, FURUTANI, and IM teaches the device of claim 1, and does not teach a solder ball joint between a second surface of the second PCB and the first surface of the first PCB; and a solder resist layer around the solder ball joint.
Kajiwara teaches, in Fig. 2 and 11, a solder ball joint (38) between a second surface (bottom surface) of the second PCB (40) and the first surface (top surface) of the first PCB (10); and a solder resist layer (43,25) around the solder ball joint (Fig. 2, 11).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device disclosed by Nii, FURUTANI, and IM with the solder ball and solder resist as disclosed by Kajiwara in order to connect electrically the second PCB to the first PCB for the purposes of low loss signal transmission as it is known in the art.
Regarding Claim 14. (Original) Nii, FURUTANI, and IM teaches the device of claim 1,but does not teach a joint between a second surface of the second PCB and the first surface of the first PCB, wherein the joint has a non-circular shape.
Kajiwara teaches a joint (38) between a second surface (bottom surface) of the second PCB (40) and the first surface (top surface) of the first PCB (10), wherein the joint has a non-circular shape (cylindrical, see Fig. 2, 11).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device disclosed by Nii, FURUTANI, and IM with the non-circular joint as disclosed by Kajiwara in order to make a better proper connection to rectangular electrical pad as it is known in the art.
It has also been held that changing the shape of an object is routine to one of ordinary skill in the art if persuasive evidence is absent that the particular configuration of the claimed object is significant. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nii, FURUTANI, and IM in view of Nishimura (US7217993).
Regarding Claim 15. Nii, FURUTANI, and IM teaches the device of claim 1, the first PCB includes a second surface (NII, bottom surface) opposite the first surface (NII, see Fig. 3-8), but does not teach the device further comprises: a solder ball grid array.
Nishimura teaches, in Fig. 4, a solder ball grid array (16).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Nii, FURUTANI, and IM with solder ball grid array as disclosed by Nishimura for the purpose of connecting with an external circuit (Nishimura, column 3 lines 50-55).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US6633005) in view of Fukuoka (US7149496) in view of FURUTANI (WO2022071006) in further view of IM (KR20220054078).
Regarding Claim 16. Wang teaches, in Fig. 4-5 and 7, an device, comprising: a first printed circuit board (PCB) (18a,18b, 18c), including a plurality of insulating layers (36); a cavity (22) in a first surface of the first PCB (see Fig. 4-5 and 7), the cavity having a depth from the first surface greater than a thickness of one of the plurality of insulating layers (see Fig. 4-5, and 7); a power amplifier (24) mounted in the cavity, wherein the power amplifier is configured to amplify radio frequency signals (column 4 lines 18-22), a second PCB (18d) mounted to the first surface (top surface) and mounted over the cavity (see Fig. 4); but does not teach a power amplifier mounted at a first electrical joint on a cavity surface; a second electrical joint on a PCB second surface of the first PCB at a location on the PCB second surface opposite the first electrical joint; a via through one or more of the plurality of insulating layers from the first electrical joint to the second electrical joint and providing an electrical connection path between an amplified output of the power amplifier to the second electrical joint; a first mold including a molding material at the first surface of the first PCB, wherein the first mold encloses the second PCB and electrical components mounted to the first surface of the first PCB and the second PCB and a second mold including the molding material at a second surface of the first PCB, wherein the second mold encloses electrical components mounted to the second surface of the first PCB.
Fukuoka teaches, in Fig. 12, a power amplifier (24) mounted at a first electrical joint (the joint below AMP-IC112) on a cavity surface (see Fig. 12); a second electrical joint (SLPG{5,6}) on a PCB second surface (see Fig. 12) of the first PCB at a location on the PCB second surface opposite the first electrical joint (see Fig. 12); a via (V1,V2) through one or more of the plurality of insulating layers (11,12,13,14) from the first electrical joint to the second electrical joint and providing an electrical connection path between an amplified output of the power amplifier to the second electrical joint (see Fig .12).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Wang with the electrical joint as disclosed by Fukuoka in order to provide a high-frequency module reduced both in size and loss and increased in isolation in its entirety (column 2 lines 55-57).
FURUTANI teaches, in Fig. 1B/C, a first mold (72) including a molding material at the first surface of the first PCB (see Fig. 1B/C), wherein the first mold encloses the second PCB (see above references) and electrical components mounted to the first surface of the first PCB and the second PCB (see Fig. 1B/C).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Wang and Fukuoka with the mold as disclosed by FURUTANI in order to protect the electrical components by sealing as it is known in the art (FURUTANI, translation page 4 paragraph 5-8, translation page 9 paragraph 3).
IM teaches, in Fig. 1-3, a second mold (126) including the molding material at a second surface (110b) of the first PCB (110) (see Fig.2 and 3), wherein the second mold encloses electrical components (123- duplication of parts) mounted to the second surface of the first PCB.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device as disclosed by Wang, Fukuoka and FURUTANI with the second mold as disclosed by IM in order to fix a a signal terminal processing problem (IM, Background Art) .
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUHAMMED AZAM whose telephone number is (571)270-0593. The examiner can normally be reached Mon-Fri 11:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TIMOTHY DOLE can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MA/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
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