DETAILED ACTION
1. The communication is in response to the application received 11/01/2022, wherein claims 1-25 are pending and are examined as follows.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
3. The disclosure is objected to because of the following informalities: it is recommended that references to the chroma format expressed as, for e.g. ‘444’, be changed to read 4:4:4. The same applies to the other formats shown. See for e.g. ¶0162 of the filed specification. This is mostly for clarity but also seems to be the common way that chroma formats are specified in the literature. Appropriate correction is required.
Claim Objections
4. Claim 2 is objected to because of the following informalities: the phrase “of the encode” in the limitation “comprising determining encoder statistics of the encode of the downscaled image data” (emphasis added) seems as though it should be removed to read “comprising determining encoder statistics of the downscaled image data”. Please check. Appropriate correction is required.
5. Claim 8 is objected to because of the following informalities: the claim recites “a single 444 format” (emphasis added). It is recommended that this be changed to read “4:4:4 format”, which is believed to be the common way for indicating chroma formats in the literature. Appropriate correction is required.
6. Claim 10 is objected to for similar reasons as claim 8: the claim recites “420”. Please update to read “4:2:0 format”. Appropriate correction is required.
7. Claim 12 is objected to because of the following informalities: the claim recites “downscaling of 4x4 to 1 pixel or 2x2 to 1 pixel.” (emphasis added). For clarity, it is recommended that this be changed to “downscaling of a block of 4x4 pixels to 1 pixel or a block of 2x2 pixels to 1 pixel” or something equivalent. Appropriate correction is required.
8. Claim 13 is objected to for similar reasons as claim 12, where it is recommended the limitation “the downscaling circuitry performs 8x8 to 1 pixel downscaling” be changed to read for e.g. “the downscaling circuitry performs 8x8 to 1 pixel downscaling of a pixel block” or something equivalent. Please check. Appropriate correction is required.
9. Claim 13 is further objected to for similar reasons as claim 8: the claim recites “444” and “420”. It is recommended that these be changed to read “4:4:4” and “4:2:0”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
10. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 14-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 19, claims 1 and 19 recite the limitation “without retrieving the downscaled image data from off-chip memory”, however, it is not clear how the downscaled image data can be retrieved from off-chip memory when the claim only stores the downscaled image data in on-chip memory. In other words, the claim does not appear to show said downscaled image data was ever stored in the off-chip memory in the first place such that it can be later retrieved as suggested in the claim. For the purpose of examination, the examiner interprets the aforementioned limitation to mean rather than placing the downscaled image from an off-chip memory into local memory, the downscaled image is placed directly into local memory within the chip itself, i.e. is on-chip.
Regarding claims 2-18 and 20-25, these depend on claims 1 and 19 and therefore include all of their features. Thus, these dependent claims are also rejected under 35 U.S.C. 112(b).
Regarding claim 14, claim 14 further recites “wherein the transmission circuitry is arranged to operate by using cache line operations to move image data without the use of a cache.” (emphasis added), however, it is not clear from the claim or the specification, how there can be cache line operations without the use of a cache. For the purposes of examination, the examiner interprets the aforementioned limitation to mean using cache line operations to move image data from an external storage buffer that is not cache.
Regarding claims 15-18, these depend on claim 14 above and therefore include all of its features. Thus, claims 15-18 are also rejected under 35 U.S.C. 112(b) for the same reasons previously presented.
Claim Rejections - 35 USC § 102
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 7-8, 11, 19, and 23-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. US 2024/0080462 A1 (with reference to priority document Provisional application No. 63/404,106), hereinafter referred to as Park, where Park employs techniques for performing low-resolution motion estimation searches which may improve the accuracy of techniques utilized to encode the source data (e.g. ¶0008). Please see below for details.
Regarding claim 1, Given the broadest reasonable interpretation (BRI) of the following limitation, Park teaches and/or suggests “A method of video coding comprising [See video encoder system 38 in fig. 7]: downscaling image data of a sequence of video frames [Fig. 7 discloses scaler block 65 that can receive and downscale image data to generate low resolution image data (e.g. ¶0105)] on on-chip dedicated-function downscaling circuitry [Scalar block 65 is located in video encoder system 38 which may be packaged as a system-on-chip SoC (¶0070); hence, said scaler block 65 can be understood as being on-chip]; storing downscaled image data from the downscaling circuitry in at least one on-chip buffer [See for e.g. ¶0012, ¶0049, and ¶0051. Low-resolution image data may be stored in ‘memory’ for use by the main encoding pipeline, where a memory and buffer are taken to be analogous terms. Said memory may be found in controller 40 (controller memory 44 - ¶0130). Since controller 40 may be implemented in video encoder system 38 (¶0071-¶0072), which in turn may be packaged as a SoC (¶0070), said memory is therefore construed as being on-chip. Please refer to figs. 7 and 15] without retrieving the downscaled image data from off-chip memory [Since the foregoing components can be packaged as a SoC, this suggests there is no need for having to retrieve the downscaled image data from off-chip memory.]; and providing the downscaled image data to an encoder.” [For e.g., fig. 7 illustrates that downscaled image data can be accessed via DMA and provided to the main encoding pipeline. Similarly low-resolution data can be accessed from memory 172 (¶0142) and used for low resolution motion estimation (e.g. fig. 15)]
Regarding claim 2, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “comprising determining encoder statistics of the encode of the downscaled image data, and encoding a full resolution version of the image data with encoder settings set depending on the encoder statistics.” [See for e.g. ¶0013, ¶0016, and ¶0053, where information (e.g. statistics) determined by the low resolution pipeline can be used the main encoding pipeline, for example, to determine motion weight (e.g. lambda) tuning information in rate-distortion calculations, frame-rate conversion, image stabilization, etc. A histogram statistic may also be determined to find a best motion vector. Thus, said information facilitates the motion estimation process in the main encoding pipeline]
Regarding claim 3, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein downscaled image data from the at least one buffer [See for e.g. ¶0012, ¶0049, and ¶0051. Low-resolution image data may be stored in memory for use by the main encoding pipeline] is provided to at least one processor performing the encoding of an encoder [Please refer to the hardware illustrated in figs. 7 and 15] directly without placing the downscaled image data into another memory.” [Park does not appear to place the low-resolution data (via scaler block 65) into another memory other than the memory disclosed in claim 1]
Regarding claim 7, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein the downscaling circuitry receives a predetermined scaling factor.” [Park discloses downscaling (via scaler block 65) by a factor of for e.g. ‘four’ in both horizontal and vertical directions (e.g. ¶0154). Said factor is therefore understood to be a predetermined factor for said downscaling operation]
Regarding claim 8, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein the downscaling comprises simultaneously downsampling a subsampling color scheme from a single 444 format to a format with a lower number of color variations. [¶0077, for example, describes using a 4:4:4 sampling format for chroma blocks, however, it also shows a 4:2:2 or a 4:2:0 sampling format may be used, which are half the resolution and quarter of the resolution, respectively, of the coding unit (i.e. down-sampled)]
Regarding claim 11, claim 11 is rejected under the same art and evidentiary limitations as determined for the method of Claim 1.
Regarding claim 19, claim 19 is rejected under the same art and evidentiary limitations as determined for the method of Claims 1 and 2. As to the hardware, see figs. 7 and 15 of Park.
Regarding claim 23, Park teaches and/or suggests all the limitations of claim 19, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein the encoder settings comprise at last one quantization parameter (QP) or quantization step value to control a bitrate to stream the video sequence.” [Park discloses encoding parameters such as for e.g. the quantization coefficient). See ¶0074. Park also discusses a quantization parameter in ¶0090.]
Regarding claim 24, Park teaches and/or suggests all the limitations of claim 19, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein the encoder settings relate to intra or inter- prediction data determined on the downscaled image data and to be used to encode a full resolution version of the downscaled image data.” [Park describes syntax elements to indicate a prediction mode (e.g. inter-prediction or intra-prediction). See ¶0101]
Regarding claim 25, Park teaches and/or suggests all the limitations of claim 19, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein the encoder settings relate to inter-prediction data motion vectors.” [See for e.g. ¶0010-¶0011 of Park with respect to a motion estimation block of a video encoding system that may determine a motion vector of a reference sample for a determined one or more candidate inter prediction modes]
Claim Rejections - 35 USC § 103
12. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 4 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Yoo US 2019/0311751 A1, hereinafter referred to as Yoo.
Regarding claim 4, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 4. Yoo on the other hand from the same or similar field of endeavor teaches and/or suggests “wherein the at least one buffer is a latch-based buffer.” [See for e.g. ¶0002 and ¶0005 with respect to a memory device for a SoC that can store data through a shared latch and a plurality of latches connected to said shared latch] Given Yoo’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the memory device of Yoo above that may include a blocking circuit for blocking data output with respect to a memory cell array in a section in which the memory cell array may not store data, thereby preventing unnecessary power consumption and improving the performance (¶0037).
Claim 5 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Nachimuthu et al. US 10,795,595 B2, hereinafter referred to as Nachimuthu.
Regarding claim 5, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein the at least one buffer is a type of random-access memory (RAM).” [Park shows external memory 172 (fig. 15) may be a part of controller memory 44 or local memory 21 (¶0130), the latter of which can include RAM (¶0058). Although including RAM for controller memory would be within the level of skill in the art, this is not clear from Park’s teachings. Please refer to Nachimuthu below for corresponding support] Since Park does not explicitly show that controller memory can comprise RAM, the work of Nachimuthu from the same or similar field of endeavor is relied on to disclose this feature. [Controller memory 1236 may be embodied as dynamic access memory (DRAM). See col. 11 lines 40-45. Further, col. 16 lines 5-55 also discloses controller memory comprising a random access volatile memory] Given Nachimuthu’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the teachings of Nachimuthu above that centralizes management of firmware images in a lifecycle management server which may improve management efficiency , especially for data centers and other enterprises with large numbers of computing devices (e.g. col. 10 lines 17-21).
Claim 6 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Hu et al. US 2008/0013844 A1, hereinafter referred to as Hu.
Regarding claim 6, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park further teaches and/or suggests “wherein the at least one buffer holds downscaled image data of brightness or color channel or both of up to one or more 32 x 32 pixel blocks of 8 bits per pixel.” [See for e.g. ¶0049 and ¶0105, where low-resolution image data is derived via downscaled image data (scaler block 65) of a 32x32 coding unit. Although having 8 bits per pixel is not explicit, this is within the level of skill in the art. Please see Hu below for support] Regarding using “8 bits per pixel” for the pixels of a pixel block, the work of Hu from the same or similar field of is relied on to explicitly teach this feature. [See for e.g. ¶0071 where each pixel in a 4x4 block has 8-bits] Given Hu’s method for block coding of an image, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the teachings of Hu above that combines coding in transform and spatial domains so as to adapt to applications requiring parallel computation and fixed length coding (¶0024).
Claim 9 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Li et al. US 2010/0104163 A1, hereinafter referred to as Li.
Regarding claim 9, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park however does not appear to teach and/or suggest “wherein the downscaling comprises converting initial image value bit depth of the image data to a lower bit depth in the downscaled image data.” Li on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest the aforementioned features [See for e.g. abstract, ¶0032, and ¶0042 with reference to fig. 2, where a down-sampled image undergoes bit depth reduction to facilitate subsequent processing steps employed for analyzing chest radiographic images] Given Li’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the image processing techniques of Li above that allows for proper orientation detection of thoracic and other x-ray images that does not require training and fine-tuning and that executes quickly and accurately, and that can operate automatically without the need for continual human supervision. (¶0007).
Claim 10 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Minoo et al. US 2017/0085879 A1, hereinafter referred to as Minoo.
Regarding claim 10, Park teaches and/or suggests all the limitations of claim 1, and is analyzed as previously discussed with respect to that claim. Park however does not appear to teach and/or suggest “wherein the downscaling circuitry is arranged to downsample subsample color schemes to 420 and bit depth of single pixel chroma or luminance values to 8 bit.” Minoo on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest the aforementioned features [See claim 10 of Minoo, where color data can be quantized to a given bit depth (e.g. 8 bits - ¶0023) and downsampled to a 4:2:0 format] Given Minoo’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the method of Minoo above that facilitates the conversion of high dynamic range (HDR) video data into standard dynamic range (SDR) video data for encoding purposes such that the HDR data can be recovered at the decoder (¶0008).
Claim 12 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Casefalvay et al. US 2023/0118937 A1, hereinafter referred to as Casefalvay.
Regarding claim 12, Park teaches and/or suggests all the limitations of claim 11, and is analyzed as previously discussed with respect to that claim. Park however does not appear to teach and/or suggest “wherein the downscaling circuitry is arranged to implement downscaling of 4x4 to 1 pixel or 2x2 to 1 pixel.” Csefalvay on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest the aforementioned features [Recognizing the ‘or’ condition above, see for e.g. ¶0202 with respect to averaging (construed as a downscaling operation) a 2x2 pixel block to produce 1 pixel. Although not explicitly shown, any NxN pixel array can be similarly averaged to produce 1 pixel. Such averaging schemes are within the level of skill in the art (e.g. ¶0031 of Garcia et al. US 2023/0260205 A1)] Given Csefalvay’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the processing techniques of Csefalvay above for improving the quality of denoising, and to implement it more efficiently, in order to better support path-tracing - in particular, to allow path-tracing to be performed at higher framerates and/or at better quality on devices with limited computational resources and power, such as mobile devices. (¶0005).
Claim 13 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Tripathi et al. US 2013/0222413 A1, hereinafter referred to as Tripathi.
Regarding claim 13, Park teaches and/or suggests all the limitations of claim 11, and is analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 13. Tripathi on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the downscaling circuitry performs 8x8 to 1 pixel downscaling to simultaneously downsample 444 color subsampling scheme format to 420 color subsampling scheme format.” [See for e.g. ¶0042 with respect to performing horizontal and vertical downsampling of chroma pixel components to go from a 4:4:4 format to a 4:2:0 structure. Please refer to the downsampling schemes shown in fig. 3 (e.g. ¶0050-¶0051)] Given Tripathi’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the teachings of Tripathi above for performing buffer-free chroma downsampling (abstract) that avoids having to rely on large amounts of silicon area for buffers which can consume additional power. Thus, the cost of graphics hardware and battery life of mobile devices can be better controlled (e.g. ¶0009).
Claims 14-17 are rejected under 35 U.S.C. 103 as being obvious over Park, in view of Tamura et al. US 2011/0216983 A1, hereinafter referred to as Tamura.
Regarding claim 14, Park teaches and/or suggests all the limitations of claim 11, and is analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 14. Tamura on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the transmission circuitry is arranged to operate by using cache line operations [Tamura does not refer to ‘cache line’, however the term ‘cache block’ (image data of 8x8 pixels) is used (e.g. ¶0062-¶0064), which is believed to be an analogous term in the art (e.g. see ¶0027 of Schuttenberg et al. US 2020/0241839 A1). Also refer to fig. 5 of Tamura] to move image data without the use of a cache. [In light of the 112 rejection above, the foregoing limitation is understood to mean moving image data from an external buffer, i.e. without the use of a cache. As such, cache block controller 121 can retrieve non-corrected image data from an external frame buffer 150 (fig. 5)] Given Tamura’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the teachings of Tamura above to facilitate the transfer of image data such that it is possible to shorten the time of reading and storing a necessary image block during pixel interpolation and to enhance the processing rate of a trapezoidal distortion correcting process (e.g. ¶0010).
Regarding claim 15, Park and Tamura teach and/or suggest all the limitations of claim 14, and are analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 15. Tamura on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein cache lines requests are used to obtain full resolution versions of the image data to be downscaled.” [Per for e.g. fig. 5, a cache block controller controls acquisition of a non-corrected image that includes 1920x1200 pixels, here construed to be full-resolution. Although the term “downscaled” is not used, Tamura shows the non-corrected image can be divided into smaller 240x150 cache blocks which is construed to mean ‘downscaled’] The motivation for combining Park and Tamura has been discussed in connection with claim 14, above.
Regarding claim 16, Park and Tamura teach and/or suggest all the limitations of claim 15, and are analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 16. Tamura on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein a number of cache line requests are upscaled to factor an amount of the downscaling.” [Although Tamura does not explicitly refer to upscaling, Tamura does teach pixel interpolation (fig. 5) which can be understood as a form of upscaling the data] The motivation for combining Park and Tamura has been discussed in connection with claim 14, above.
Regarding claim 17, Park and Tamura teach and/or suggest all the limitations of claim 14, and are analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 17. Tamura on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein cache lines are used to collect downscaled image data from the at least one buffer.” [Since a cache line can be considered analogous to a cache block, please see fig. 5 of Tamura regarding the movement of divided image data] The motivation for combining Park and Tamura has been discussed in connection with claim 14, above.
Claim 18 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Symes et al. US 2018/0270499 A1, hereinafter referred to as Symes.
Regarding claim 18, Park and Tamura teach and/or suggest all the limitations of claim 14, and are analyzed as previously discussed with respect to that claim. Park and Tamura however do not appear to address the features of claim 18. Symes on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein cache lines are used to transmit the downscaled image data to the encoder.” [Please refer to figs. 2 and 3. Although cache lines are not directly referenced, fig. 3 does illustrate the use of cache in the VPU with further downscaling capability (13). Output stream 4 of said VPU is further shown in the SoC of fig. 2 where said output stream can be sent to a decoder/display 3] Given Symes’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the video data processing system of Symes above that in response to a monitored memory bandwidth being greater than a threshold, encoding circuitry can be controlled to encode image data via a modified process to restrict memory bandwidth usage (e.g. abstract).
Claim 20 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Boyce et al. US 5,614,957, hereinafter referred to as Boyce.
Regarding claim 20, Park teaches and/or suggests all the limitations of claim 19, and is analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 20. Boyce on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the downscaling circuitry is arranged to remove data from the downscaled image data before encoding, wherein the removed data is at least one of: one or more least significant bits in image data values, redundant chroma data, and alpha channel data, and packer unit arranged to replace removed data with zeros to accompany the downscaled image data to form blocks of data with sizes expected by the encoder. [See col. 11 lines 1-51. Bit padding circuits replace least significant bits (LSBs) with zeros of what appears to be downsampled video frames in frame memory 118 for subsequent output to the motion compensation circuit 130. Please refer to for e.g. fig. 2A] Although Boyce’s teachings above pertain to video decoding, they are deemed relevant, since analogous processing of the video frames is performed. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the teachings of Boyce above to facilitate reducing frame buffer memory requirements in order to maintain MPEG compatibility (e.g. col. 11 lines 34-37).
Claim 21 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Kim et al. US 2020/0175647 A1, hereinafter referred to as Kim.
Regarding claim 21, Park teaches and/or suggests all the limitations of claim 19, and is analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 21. Kim on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the downscaling circuitry operates at least one of: a bilinear downscaling algorithm, nearest neighbor downscaling algorithm nearest to an average pixel value, and a fixed pixel location downscaling algorithm within individual downscaling blocks.” [Recognizing the limitation “at least one of”, see for e.g. ¶0032 with respect to downscalers that can have high downscaling quality (e.g. bilinear downscaling)]
Given Kim’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the image processing methods of Kim above that allow for high quality images to be downscaled with a small scale factor so as to save bandwidth and power to transmit and memory to store which can amount to as much as a 40% savings on both bandwidth and power (e.g. ¶0038).
Claim 22 is rejected under 35 U.S.C. 103 as being obvious over Park, in view of Sugimoto et al. US 2022/0360788 A1, hereinafter referred to as Sugimoto.
Regarding claim 22, Park teaches and/or suggests all the limitations of claim 19, and is analyzed as previously discussed with respect to that claim. Park however does not appear to address the features of claim 22. Sugimoto on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the encoder settings used to encode the downscaled image data are based on a downscaled frame size relative to a size of the video frames.” [See ¶0059 regarding an initialization parameter for a given size of a downsampled image] Given Sugimoto’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Park’s approach for low-resolution motion estimation searches, to add the image encoding method of Sugimoto above that makes it possible to reduce a code amount while maintaining image context (e.g. ¶0016).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional references in PTO 892.
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/RICHARD A HANSELL JR./Primary Examiner, Art Unit 2486