CTFR 17/978,290 CTFR 92033 DETAILED ACTION This Office Action is in response to the Amendment filed on 04/13/2026. In the filed response, Claims 1-2 and 4-25 have been amended, where Claims 1, 11, and 19 are independent claims. Claim 3 has been canceled and new Claim 26 has been added. Accordingly, Claims 1-2 and 4-26 have been examined and are pending. This Action is made FINAL. Response to Arguments 1. Applicant’s arguments, see pgs. 8-9, filed 04/13/2026, with respect to the prior art rejections of the instant claims under 35 U.S.C. 102 and 103 have been fully considered and are persuasive. Therefore, these rejections have been withdrawn. However, upon further consideration, a new ground of rejection is made in view of Kudana et al. US 2016/0198166 A1, Haskell et al. US 8,031,777 B2, and Lin US 20150262328 A1, hereinafter referred to as Kudana, Haskell, and Lin, respectively. Please see examiner’s responses below. 2. Although Park’s teachings were previously found to be relevant, they do not appear to address the newly amended features of for e.g. claim 1. However, updated searches yielded the work of Kudana, Haskell, and Lin, which are currently relied on to address these features given their broadest reasonable interpretation (BRI). Both Kudana and Haskell teach multi-pass video encoding (see abstracts), while Lin describes both a fetch unit and a down-scaler (e.g. figs. 2-3). Kudana further generates statistics from a first encoding pass of down-sampled video data at lower resolution which is subsequently used for a second encoding pass at full resolution (e.g. fig. 1). Although Kudana does not explicitly recite the terms “bypass path” and “bypass switch” as now claimed, Kudana’s multi-pass encoding scheme reasonably suggests these features for the following reason. The first encoding pass includes down-sampling/sub-sampling the video data (e.g. ¶0023), while the second encoding pass is performed at full-resolution, i.e. is not down-sampled (e.g. ¶0030). This suggests the presence of a “bypass path” that allows the second encoding pass to bypass the down-sampling/sub-sampling circuit in the video processing system of fig. 15. This also suggests the presence of a switch or a means for alternating between the two paths during the encoding process. As to Haskell, Haskell is brought in to address “wherein the second encoding pass is performed according to the quantization parameter and generates one or more further encoded frames, and the quantization parameter is to control a bitrate to stream the one or more further encoded frames .” (emphasis added). This is shown in for e.g. col. 3 lines 7-11 with respect to the quantization parameter (qp) that can be used to adjust the bit rate when performing multi-pass video encoding. Lastly, regarding the “fetch circuit” , the work of Lin is relied on for support, although receiving/retrieving video data for encoding in both Kudana and Haskell can be reasonably construed as “fetching” said data. The relationship between retrieving image data of a source video and a source fetch unit appears to be found in ¶0041-¶0042 of the filed specification. Nonetheless, please refer to Lin’s hardware arrangement in figs. 2-3, where Lin employs a tile/linear fetch 310 that can fetch video data 302. Moreover, the video data is down-scaled via down-scaler 300. Although Lin’s fetch 310 is included in down-scaler 300 as opposed to down-scaler 300 being included in fetch 310, as claimed, the examiner respectfully submits that a mere rearrangement of elements without modification of the operation of the device involves only routine skill in the art. In re Japiske , 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not appear to modify the operation of the device because it is still capable of down-sampling fetched video data that can be subsequently coded. Thus, Lin’s teachings for modifying a down-scaling filter allow for more efficient down-scaling to be performed so as to help conserve memory bandwidth, memory access, and bus bandwidth (e.g. ¶0029). Also noteworthy is the work of Tripathi et al. US 2013/0222413 A1, which describe a pipeline 10 (fig. 1) that may be implemented as a SoC (¶0032). It also includes circuitry for fetching, scaling, and down-sampling source video data (e.g. ¶0035-¶0037). Thus for these reasons, which are further elaborated on below, the examiner respectfully submits Kudana, Haskell, and Lin, either alone or in combination, reasonably teach and/or suggest the disclosed claimed features, as amended, given their BRI. 3. Applicant’s amendments to the specification in response to the specification objections are acknowledged. Thus, the objections are withdrawn. 4. Applicant’s amendments in response to the claim objections are acknowledged. Thus, the objections are withdrawn. 5. Applicant’s amendments in response to the rejections under 35 U.S.C. 112(b) are acknowledged. Thus, the rejections are withdrawn. 6. The Examiner is available to discuss the matters of this office action to help move the Instant Application forward. Please refer to the conclusion to this office action regarding scheduling interviews. 7. Accordingly, Claims 1-2 and 4-26 have been examined and are pending. Claim Objections 07-29-01 AIA 8. Claim 19 is objected to because of the following informalities: the claim recites “and a bypass path for a second encoding pass” (line 3), however, its function is not entirely clear. For e.g. claim 1 defines the bypass path as “bypass path within the fetch circuit that bypasses the on- chip dedicated-function downscaling circuitry ” (emphasis added). It is recommended that this also be defined in claim 19 for clarity . Appropriate correction is required. Claim 19 is further objected to because of the following informalities: the claim further recites “and the path includes dedicated-function downscaling circuitry…”. It is recommended for clarity that this read as “and the path includes on-chip dedicated-function downscaling circuitry…” (emphasis added) as found in claim 1. Claim 19 is further objected to because of the following informalities: the claim further recites “encode for the second encoding pass according to…”. It is recommended that this read as “encode for the second encoding pass via the bypass path according to…” or something equivalent, to more clearly show the second encoding pass is along the bypass path. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1, 2, 7, 11, 19, 22-26 are rejected under 35 U.S.C. 103 as being obvious over Kudana et al. US 2016/0198166 A1, in view of Lin US 2015/0262328 A1, and in further view of Haskell et al. US 8,031,777 B2, hereinafter referred to as Kudana, Lin, and Haskell, respectively. Regarding claim 1 . (Currently Amended) Given the broadest reasonable interpretation (BRI) of the following limitations, Kudana teaches and/or suggests “A method of video coding comprising: downscaling, by on-chip dedicated-function downscaling circuitry in a fetch circuit, image data of a sequence of video frames [See for e.g. ¶0022-¶0023 regarding implementation of encoding method 100 via encoder circuit 1504 in video processing system 1502 which receives frames of input video 200 for downsampling. Although a “fetch circuit” is not explicitly disclosed, ‘receiving’ said frames for processing is construed to be analogous to ‘fetching’ given its BRI and would therefore require appropriate circuitry. Please see Lin below for more direct support regarding the “fetch circuit”] ; storing downscaled image data from the downscaling circuitry in at least one on-chip buffer in the fetch circuit [¶0022-¶0023 further describe memory 1506 (fig. 15) for storing video frame data, which includes downsampled video data (above) used in the initial (first) encoding pass] ; providing the downscaled image data from the fetch circuit to an encoder to perform a first encoding pass, wherein the first encoding pass generates one or more encoded frames [Se for e.g. [¶0022-¶0023 with reference to fig. 1, where method 100 shows a first pass to encode the downsampled frames of a first sub-GOP. Also please refer to the first pass in fig. 2] ; determining a quantization parameter based on the one or more encoded frames [Although Kudana does not teach determining a quantization parameter (QP), first pass encoding statistics are disclosed such as for e.g. motion data (e.g. ¶0029). Please see Haskell below regarding QP support] ; fetching, by the fetch circuit [Although a “fetch circuit” is not explicitly disclosed, Kudana’s image data is received (fig. 15). Please see Lin for support regarding the “fetch circuit”] , the image data of the sequence of video frames using a bypass path within the fetch circuit that bypasses the on-chip dedicated-function downscaling circuitry [Kudana’s method 100 further discloses performing a second pass encoding of full resolution frames based on the generated statistics of the first pass (fig. 1). Although a “bypass path” is not explicit, switching between downsampled video data and full-resolution video data suggests Kudana’s system includes an analogous path for performing multi-pass video encoding] ; and providing the fetched image data from the fetch circuit to the encoder to perform a second encoding pass [See for e.g. fig. 1] , wherein the second encoding pass is performed according to the quantization parameter and generates one or more further encoded frames [Kudana’s second encoding pass uses the generated statistics of the first encoding pass. See Haskell regarding QP support] , and the quantization parameter is to control a bitrate to stream the one or more further encoded frames.” [See Haskell regarding QP support] Although Kudana’s multi-pass video encoding (e.g. abstract) is deemed relevant to the aforementioned features as claimed, there is no explicit disclosure of a “on-chip dedicated-function downscaling circuitry in a fetch circuit”. Kudana does teach receiving frames of input video via the circuit shown in fig. 15 which can be construed as retrieving/fetching said data for downsampling and subsequent encoding in a first pass. However, to provide more direct support, the work of Lin from the same or similar field of endeavor is relied on to teach and/or suggest “on-chip dedicated-function downscaling circuitry in a fetch circuit” [See the hardware arrangement of Lin’s down-scaler 300 and tile/linear fetch 310 (e.g. figs. 1-2). Although fetch 310 is included in down-scaler 300, the arrangement shows that a fetch circuit and down-scaling circuitry are integrally connected to each other such that it still permits fetched video data to be down-sampled for subsequent coding operations at a lower resolution.] Although Lin’s fetch circuit is a part of the down-scaling circuitry, the arrangement is deemed relevant since video data that has been fetched can be down-sampled to a lower resolution for subsequent processing. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), to add the hardware arrangement of Lin for modifying a down-scaling filter that allows for more efficient down-scaling to be performed so as to help conserve memory bandwidth, memory access, and bus bandwidth (e.g. ¶0029). Although the combined teachings of Kudana and Lin are deemed relevant given the BRI of the disclosed features, they do not address the limitation related to the “quantization parameter.” However, Haskell from the same or similar field of endeavor is relied on to teach and/or suggest “determining a quantization parameter based on the one or more encoded frames” [See col. 3 lines 7-11 with respect to the quantization parameter (qp) that can be used to adjust the bit rate when performing multi-pass video encoding] and “wherein the second encoding pass is performed according to the quantization parameter and generates one or more further encoded frames [The encoding system (fig. 1) can perform intermediate passes or iterations via coding adjustments made by the controller implemented by the encoder engine that can for e.g. use the qp for adjusting bit rate (e.g. col. 2 lines 38-47 and col. 3 lines 7-11)] and the quantization parameter is to control a bitrate to stream the one or more further encoded frames.” [Same as above where the qp can be used for adjusting bit rate (e.g. col. 2 col. 3 lines 7-11)] Given Haskell’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract) and Lin’s hardware arrangement (fig. 3), to add Haskell’s multi-pass video encoding approach that allows for generating a complete coded data sequence more quickly while ensuring the sequence is highly compressed (col. 2 lines 59-61). Regarding claim 2 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Kudana further teaches and/or suggests “further comprising: determining encoder statistics of the one or more encoded frames [See first pass encoding statistics in for e.g. ¶0029] ; wherein the quantization parameter and encoder settings of the second encoding pass are set depending on the encoder statistics.” [A second encoding pass employs the statistics gathered during the first low-resolution (down-sampled) encoding process (e.g. ¶0033)] Although Kudana is deemed relevant given the BRI of the disclosed features, Kudana and Lin do not address the limitation related to the “quantization parameter.” However, Haskell from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the quantization parameter and encoder settings of the second encoding pass are set depending on the encoder statistics.” [See figs. 1-2 and associated text. Selected frames of a particular pass can be encoded according to selected encoding parameters which includes qp (col. 3 lines 23-65).] The motivation for combining Kudana, Lin, and Haskell has been discussed in connection with claim 1, above. Regarding claim 7 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Although Kudana does not appear to address the features of claim 7, Lin from the same or similar field of endeavor is found to teach and/or suggest “wherein the downscaling circuitry receives a predetermined scaling factor.” [See for e.g. ¶0086 of Lin. Said scale factor is understood to be a predetermined factor for said downscaling operation] The motivation for combining Kudana and Lin has been discussed in connection with claim 1, above. Regarding claim 11, claim 11 is rejected under the same art and evidentiary limitations as determined for the method of Claim 1. Regarding claim 19, claim 19 is rejected under the same art and evidentiary limitations as determined for the method of Claims 1 and 2. As to the hardware, please see fig. 15 of Kudana. Regarding claim 22 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 19, and are analyzed as previously discussed with respect to that claim. Kudana further teaches and/or suggests “wherein the downscaled image data has a frame size relative to a size of the image data of the sequence of video frames.” [See for e.g. fig. 5. Also please note fig. 8 of Lin] Regarding claim 23 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 19, and are analyzed as previously discussed with respect to that claim. Kudana and Lin however do not appear to address the features of claim 23. Haskell on the other hand from the same or similar field of endeavor teaches and/or suggests “wherein the quantization parameter controls a bitrate to stream one or more further encoded frames generated from the second encoding pass.” [See for e.g. fig. 2 with reference to the supporting text regarding quantization parameter qp. Also please note col. 3 lines 7-22 for controlling a bitrate] Regarding claim 24 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 19, and are analyzed as previously discussed with respect to that claim. Kudana further teaches and/or suggests “wherein encoder settings of the second encoding pass relate to intra or inter- prediction data determined on the one or more encoded frames generated from the fist encoding pass.” [See for e.g. ¶0030] Regarding claim 25 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 19, and are analyzed as previously discussed with respect to that claim. Kudana further teaches and/or suggests “wherein encoder settings of the second encoding pass relate to inter-prediction data motion vectors.” [See for e.g. ¶0034-¶0035 with respect to motion vectors of the second encoding pass] Regarding claim 26 , (New) Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 19, and are analyzed as previously discussed with respect to that claim. Kudana further teaches and/or suggests “wherein the fetch circuit further includes a bypass switch controllable to switch between the path for the first encoding pass and the bypass path for the second encoding pass.” [Although “bypass switch” is not explicit, Kudana’s multi-pass encoding scheme reasonably suggests this feature since the first encoding pass includes down-sampling/sub-sampling the video data (e.g. ¶0023), while the second encoding pass is performed at full-resolution, i.e. is not down-sampled (e.g. ¶0030). This suggests the scheme is capable of switching between two paths that allow the second encoding pass to bypass the down-sampling/sub-sampling circuit in the video processing system of fig. 15.] Claim 4 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Yoo US 2019/0311751 A1, hereinafter referred to as Yoo. Regarding claim 4 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell however do not appear to address the features of claim 4. Yoo on the other hand from the same or similar field of endeavor teaches and/or suggests “wherein the at least one on-chip buffer is a latch-based buffer.” [See for e.g. ¶0002 and ¶0005 with respect to a memory device for a SoC that can store data through a shared latch and a plurality of latches connected to said shared latch] Given Yoo’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract) to add the memory device of Yoo above that may include a blocking circuit for blocking data output with respect to a memory cell array in a section in which the memory cell array may not store data, thereby preventing unnecessary power consumption and improving the performance (¶0037). Claim 5 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Nachimuthu et al. US 10,795,595 B2, hereinafter referred to as Nachimuthu . Regarding claim 5 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell however do not appear to address the features of claim 4. Nachimuthu on the other hand from the same or similar field of endeavor teaches and/or suggests “wherein the at least one on-chip buffer is a type of random-access memory (RAM).” [Controller memory 1236 may be embodied as dynamic access memory (DRAM). See col. 11 lines 40-45. Further, col. 16 lines 5-55 also discloses controller memory comprising a random access volatile memory] Given Nachimuthu’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract) to add the teachings of Nachimuthu above that centralizes management of firmware images in a lifecycle management server which may improve management efficiency , especially for data centers and other enterprises with large numbers of computing devices (e.g. col. 10 lines 17-21). Claim 6 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in view of Hu et al. US 2008/0013844 A1, hereinafter referred to as Hu . Regarding claim 6 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Although Kudana does not appear to address the features of claim 6, Lin from the same or similar field of endeavor is found to teach and/or suggest “wherein the at least one buffer holds downscaled image data of brightness or color channel or both of up to one or more 32 x 32 pixel blocks of 8 bits per pixel.” [Lin discloses for e.g. a column buffer 330 that can be implemented as part of down-scaler 300 that can accumulate down-scaled values of the fetched video data (e.g. ¶0087). Said data may be luminance/chrominance values. Lin further discloses various block sizes in ¶0074. Although 32 by 32 is not mentioned, holding data of up to one or more 32x32 pixel blocks of 8 bits per pixel is deemed within the level of skill in the art. Hu is relied on below for support regarding 8 bits per pixel] Regarding using “8 bits per pixel” for the pixels of a pixel block, the work of Hu from the same or similar field of is relied on to explicitly teach this feature. [ See for e.g. ¶0071 where each pixel in a 4x4 block has 8-bits] Given Hu’s method for block coding of an image, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the teachings of Hu above that combines coding in transform and spatial domains so as to adapt to applications requiring parallel computation and fixed length coding (¶0024). Claim 8 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in view of Park et al. US 2024/0080462 A1, hereinafter referred to as Park . Regarding claim 8 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell do not appear to address the features of claim 8. Park on the other hand from the same or similar field of endeavor is found to teach and/or suggest “wherein the downscaling comprises simultaneously downsampling a subsampling color scheme from a single 4:4:4 format to a format with a lower number of color variations. [¶0077, for example, describes using a 4:4:4 sampling format for chroma blocks, however, it also shows a 4:2:2 or a 4:2:0 sampling format may be used, which are half the resolution and quarter of the resolution, respectively, of the coding unit (i.e. down-sampled)] Given Park’s teachings, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the coding methods of Park above for performing low-resolution motion estimation searches which may improve the accuracy of techniques utilized to encode the source data (e.g. ¶0008). Claim 9 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Li et al. US 2010/0104163 A1, hereinafter referred to as Li. Regarding claim 9 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell do not appear to address the features of claim 9. Li on the other hand from the same or similar field of endeavor is found to teach and/or suggest “wherein the downscaling comprises converting initial image value bit depth of the image data to a lower bit depth in the downscaled image data.” Li on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest the aforementioned features [See for e.g. abstract, ¶0032, and ¶0042 with reference to fig. 2, where a down-sampled image undergoes bit depth reduction to facilitate subsequent processing steps employed for analyzing chest radiographic images] Given Li’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the image processing techniques of Li above that allows for proper orientation detection of thoracic and other x-ray images that does not require training and fine-tuning and that executes quickly and accurately, and that can operate automatically without the need for continual human supervision. (¶0007). Claim 10 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Minoo et al. US 2017/0085879 A1, hereinafter referred to as Minoo . Regarding claim 10 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 1, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell do not appear to address the features of claim 10. Minoo on the other hand from the same or similar field of endeavor is found to teach and/or suggest “wherein the downscaling circuitry is arranged to downsample subsample color schemes to 420 and bit depth of single pixel chroma or luminance values to 8 bit.” Minoo on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest the aforementioned features [See claim 10 of Minoo, where color data can be quantized to a given bit depth (e.g. 8 bits - ¶0023) and downsampled to a 4:2:0 format] Given Minoo’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the method of Minoo above that facilitates the conversion of high dynamic range (HDR) video data into standard dynamic range (SDR) video data for encoding purposes such that the HDR data can be recovered at the decoder (¶0008). Claim 12 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Casefalvay et al. US 2023/0118937 A1, hereinafter referred to as Casefalvay . Regarding claim 12 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 11, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell do not appear to address the features of claim 12. Csefalvay on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the dedicated function downscaling circuitry is arranged to implement downscaling of a 4x4 pixel block to 1 pixel or a 2x2 pixel block to 1 pixel.” [Recognizing the ‘or’ condition above, see for e.g. ¶0202 with respect to averaging (construed as a downscaling operation) a 2x2 pixel block to produce 1 pixel. Although not explicitly shown, any NxN pixel array can be similarly averaged to produce 1 pixel. Such averaging schemes are within the level of skill in the art (e.g. ¶0031 of Garcia et al. US 2023/0260205 A1)] Given Csefalvay’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the processing techniques of Csefalvay above for improving the quality of denoising, and to implement it more efficiently, in order to better support path-tracing - in particular, to allow path-tracing to be performed at higher framerates and/or at better quality on devices with limited computational resources and power, such as mobile devices. (¶0005). Claim 13 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Tripathi et al. US 2013/0222413 A1, hereinafter referred to as Tripathi . Regarding claim 13 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 11, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell do not appear to address the features of claim 13. Tripathi on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the dedicated function downscaling circuitry performs an 8x8 pixel block to 1 pixel downscaling to simultaneously downsample a 4:4:4 color subsampling scheme format to a 4:2:0 color subsampling scheme format.” [See for e.g. ¶0042 with respect to performing horizontal and vertical downsampling of chroma pixel components to go from a 4:4:4 format to a 4:2:0 structure. Please refer to the downsampling schemes shown in fig. 3 (e.g. ¶0050-¶0051)] Given Tripathi’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the teachings of Tripathi above for performing buffer-free chroma downsampling (abstract) that avoids having to rely on large amounts of silicon area for buffers which can consume additional power. Thus, the cost of graphics hardware and battery life of mobile devices can be better controlled (e.g. ¶0009). Claims 14-15 and 17 are rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Tamura et al. US 2011/0216983 A1, hereinafter referred to as Tamura . Regarding claim 14 , Kudana, Lin, and Haskell teach and/or suggest all the limitations of claim 11, and are analyzed as previously discussed with respect to that claim. Kudana, Lin, and Haskell do not appear to address the features of claim 14. Tamura on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the transmission circuitry is arranged to operate by using cache line operations to move image data.” [Tamura does not refer to ‘cache line’, however the term ‘cache block’ (image data of 8x8 pixels) is used (e.g. ¶0062-¶0064), which is believed to be an analogous term in the art (e.g. see ¶0027 of Schuttenberg et al. US 2020/0241839 A1). Also refer to fig. 5 of Tamura] Given Tamura’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the teachings of Tamura above to facilitate the transfer of image data such that it is possible to shorten the time of reading and storing a necessary image block during pixel interpolation and to enhance the processing rate of a trapezoidal distortion correcting process (e.g. ¶0010). Regarding claim 15 , Kudana, Lin, Haskell, and Tamura teach and/or suggest all the limitations of claim 15, and are analyzed as previously discussed with respect to that claim. They do not appear however to address the features of claim 15. Tamura on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein cache line requests are used to obtain full resolution versions of the image data to be downscaled.” [Per for e.g. fig. 5, a cache block controller controls acquisition of a non-corrected image that includes 1920x1200 pixels, here construed to be full-resolution. Although the term “downscaled” is not used, Tamura shows the non-corrected image can be divided into smaller 240x150 cache blocks which is construed to mean ‘downscaled’] The motivation for combining Kudana, Lin, Haskell, and Tamura has been discussed in connection with claim 14, above. Regarding claim 17 , Kudana, Lin, Haskell, and Tamura teach and/or suggest all the limitations of claim 15, and are analyzed as previously discussed with respect to that claim. They do not appear however to address the features of claim 17. Tamura on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein cache lines are used to collect downscaled image data from the at least one on-chip buffer.” [Since a cache line can be considered analogous to a cache block, please see fig. 5 of Tamura regarding the movement of divided image data] The motivation for combining Kudana, Lin, Haskell, and Tamura has been discussed in connection with claim 14, above. Claim 21 is rejected under 35 U.S.C. 103 as being obvious over Kudana, in view of Lin, in further view of Haskell, and in further view of Kim et al. US 2020/0175647 A1, hereinafter referred to as Kim . Regarding claim 21 , Kudana, Lin, Haskell, and Tamura teach and/or suggest all the limitations of claim 19, and are analyzed as previously discussed with respect to that claim. They do not appear however to address the features of claim 21. Kim on the other hand from the same or similar field of endeavor is relied on to teach and/or suggest “wherein the dedicated-function downscaling circuitry operates using at least one of: a bilinear downscaling algorithm, nearest neighbor downscaling algorithm nearest to an average pixel value, and a fixed pixel location downscaling algorithm within individual downscaling blocks.” [Recognizing the limitation “at least one of”, see for e.g. ¶0032 with respect to downscalers that can have high downscaling quality (e.g. bilinear downscaling)] Given Kim’s teachings above, it would have therefore been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kudana’s multi-pass video encoding approach (abstract), Lin’s hardware arrangement (fig. 3), along with Haskell’s multi-pass video encoding scheme (e.g. abstract), to add the image processing methods of Kim above that allow for high quality images to be downscaled with a small scale factor so as to save bandwidth and power to transmit and memory to store which can amount to as much as a 40% savings on both bandwidth and power (e.g. ¶0038). Allowable Subject Matter 10. Claims 16, 18, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In light of the specification, the Examiner finds the claimed invention to be patentably distinct from the prior art of records. The prior art of record, taken individually or in combination fail to explicitly teach or render obvious within the context of the respective independent claims the limitations: 16. (Currently Amended) The system fetch circuit of claim 15 wherein a number of cache line requests are upscaled to factor in an amount of the downscaling. 18. (Currently Amended) The system fetch circuit of claim 14 wherein cache lines are used to transmit the downscaled image data to the encoder for the first encoding pass. 20. (Currently Amended) The video coding device of claim 19, wherein the dedicated-function downscaling circuitry is arranged to remove data from the downscaled image data, wherein the removed data is at least one of: one or more least significant bits in image data values, redundant chroma data, and alpha channel data, and the fetch circuit further includes a packer unit in the path arranged to replace removed data with zeros to accompany the downscaled image data to form blocks of data with sizes expected by the encoder. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD A HANSELL JR. whose telephone number is (571)270-0615. The examiner can normally be reached Mon - Fri 10 am- 7 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jamie Atala can be reached at 571-272-7384. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD A HANSELL JR./Primary Examiner, Art Unit 2486 Application/Control Number: 17/978,290 Page 2 Art Unit: 2486 Application/Control Number: 17/978,290 Page 3 Art Unit: 2486 Application/Control Number: 17/978,290 Page 4 Art Unit: 2486 Application/Control Number: 17/978,290 Page 5 Art Unit: 2486 Application/Control Number: 17/978,290 Page 6 Art Unit: 2486 Application/Control Number: 17/978,290 Page 7 Art Unit: 2486 Application/Control Number: 17/978,290 Page 8 Art Unit: 2486 Application/Control Number: 17/978,290 Page 9 Art Unit: 2486 Application/Control Number: 17/978,290 Page 10 Art Unit: 2486 Application/Control Number: 17/978,290 Page 11 Art Unit: 2486 Application/Control Number: 17/978,290 Page 12 Art Unit: 2486 Application/Control Number: 17/978,290 Page 13 Art Unit: 2486 Application/Control Number: 17/978,290 Page 14 Art Unit: 2486 Application/Control Number: 17/978,290 Page 15 Art Unit: 2486 Application/Control Number: 17/978,290 Page 16 Art Unit: 2486 Application/Control Number: 17/978,290 Page 17 Art Unit: 2486 Application/Control Number: 17/978,290 Page 18 Art Unit: 2486 Application/Control Number: 17/978,290 Page 19 Art Unit: 2486 Application/Control Number: 17/978,290 Page 20 Art Unit: 2486 Application/Control Number: 17/978,290 Page 21 Art Unit: 2486 Application/Control Number: 17/978,290 Page 22 Art Unit: 2486 Application/Control Number: 17/978,290 Page 23 Art Unit: 2486
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