DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments and amendments filed February 18, 2026 have been entered and considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6, 8, 14, 16-17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (KR 20190104277 A), in view of Son (KR 20110061435 A).
Regarding claim 1, Chang et al. teaches:
A display device comprising:
a first assembly electrode [2112, paragraph [0205], Fig. 21] and a second assembly electrode [2113, paragraph [0205], Fig. 21] spaced apart and disposed on a substrate [2110, paragraph [0205], Fig. 21];
a first insulating layer [2114, paragraph [0205], Fig. 21] disposed on the first assembly electrode [2112, Fig. 21] and the second assembly electrode [2113, Fig. 21];
an assembly barrier wall [2115, paragraph [0205], Fig. 21; 1315, paragraph [0165], Fig. 14] including a predetermined assembly hole [(no number designation), paragraph [0205, 0212], Fig. 21; 1311, paragraph [0163], Fig. 14] and disposed on the first insulating layer [2114, paragraph [0205], Fig. 21; 1314, paragraph [0164], Fig. 14]; (*Note equivalent numerical designations)
a semiconductor light emitting device [1850, paragraph [0194-0195], Fig. 19; becomes 2150* (no number designation in Fig. 21, hereby referred to as 2150*), Fig. 21] disposed in the predetermined assembly hole [(no number designation), paragraph [0205, 0212], Fig. 21], and including a first conductivity type semiconductor layer [2153, paragraph [0206], Fig. 21], a second conductivity type semiconductor layer [2155, paragraph [0206], Fig. 21], and an active layer [2154, paragraph [0206], Fig. 21] between the first conductivity type semiconductor layer [2153, Fig. 21] and the second conductivity type semiconductor layer [2155, Fig. 21];
a side electrode electrically [1851 “first conductive electrode”, paragraph [0194], Fig. 19a; 2151, paragraph [0204, 0206-0208], Fig. 21] connected to a first side surface of the semiconductor light emitting device [2150*, Fig. 21]; and
a second panel electrode [2140 “second wiring electrode”, paragraph [0207-0208], Fig. 21] electrically connected to the second conductivity type semiconductor layer [2155, Fig. 21],
wherein the side electrode [1851, Fig. 19a; 2151, Fig. 21] is electrically connected to a side surface of the first conductivity type semiconductor layer [1853, Fig. 19a; 2153, Fig. 21].
Chang et al. does not teach:
wherein a top most surface of the side electrode is positioned lower than the active layer.
Son teaches:
wherein a top most surface of the side electrode [180, paragraph [0006-0009], [00011-00013], Fig. 1-2, 8-9] is positioned lower than the active layer [140, paragraph [0006-00013], Fig. 1-2, 8-9].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Son into the teachings of Chang et al. to include wherein a top most surface of the side electrode is positioned lower than the active layer, for the purpose of improving light extraction efficiency, allowing current to flow uniformly and smoothly, luminous efficiency of the light emitting device can be improved and the operating voltage can be lowered, prevent the second conductive type semiconductor layer from being electrically shorted.
Regarding claim 3, Chang et al. and Son teach the display device according to claim 1.
Chang et al. further teaches:
further comprising a second insulating layer [2120, paragraph [0207], Fig. 21] disposed in the predetermined assembly hole [(no number designation), paragraph [0205, 0212], Fig. 21],
wherein the second insulating layer [2120, Fig. 21] is configured to fix the first side surface of the semiconductor light emitting device [2150*, Fig. 21].
Regarding claim 6, Chang et al. and Son teach the display device according to claim 1.
Chang et al. further teaches:
further comprising a first panel electrode [2130 “first wiring electrode”, paragraph [0207-0208], Fig. 21] electrically connected to the side electrode [2151 “first conductive electrode”, paragraph [0206-0208], Fig. 21].
Regarding claim 8, Chang et al. and Son teach the display device according to claim 1.
Chang et al. further teaches:
a first side electrode [2151 (Vertical portion), Fig. 21] contacting the semiconductor light emitting device [2150*, Fig. 21], and
a second side electrode [2151 (Horizontal portion), Fig. 21] extending from the first side electrode [2151 (Vertical portion), Fig. 21] and electrically connected to a first panel electrode [2130, Fig. 21].
Regarding claim 14, Chang et al. teaches:
A display device comprising:
a first assembly electrode [2112, paragraph [0205], Fig. 21] and a second assembly electrode [2113, paragraph [0205], Fig. 21] spaced apart and on a substrate [2110, paragraph [0205], Fig. 21];
a first insulating layer [2114, paragraph [0205], Fig. 21] on the first assembly electrode [2112, Fig. 21] and the second assembly electrode [2113, Fig. 21];
an assembly barrier wall [2115, paragraph [0205], Fig. 21; 1315, paragraph [0165], Fig. 14] on the first insulating layer and including a predetermined assembly hole [(no number designation), paragraph [0205, 0212], Fig. 21; 1311, paragraph [0163], Fig. 14]; (*Note equivalent numerical designations)
a semiconductor light emitting device [1850, paragraph [0194-0195], Fig. 19; becomes 2150* (no number designation in Fig. 21, hereby referred to as 2150*), Fig. 21] disposed in the predetermined assembly hole [(no number designation), paragraph [0205, 0212], Fig. 21];
a side electrode [1851 “first conductive electrode”, paragraph [0194], Fig. 19a; 2151, paragraph [0204, 0206-0208], Fig. 21] on a side surface of the semiconductor light emitting device [2150*, Fig. 21], and extending along the side surface of the semiconductor light emitting device [2150*, Fig. 21]; and
a panel electrode [2140 “second wiring electrode”, paragraph [0207-0208], Fig. 21] connected to an upper surface of the semiconductor light emitting device [2150*, Fig. 21],
wherein the semiconductor light emitting device [2150*, Fig. 21] comprises a first conductivity type semiconductor layer [2153, Fig. 21], a second conductivity type semiconductor layer [2155, Fig. 21] and an active layer [2154, Fig. 21] disposed between the first conductivity type semiconductor layer [2153, Fig. 21] and the second conductivity type semiconductor layer [2155, Fig. 21],
wherein the side electrode [1851, Fig. 19a; 2151, Fig. 21] is electrically connected to a side surface of the first conductivity type semiconductor layer [2153, Fig. 21];
Chang et al. does not teach:
wherein a top most surface of the side electrode is positioned lower than the active layer.
Son teaches:
wherein a top most surface of the side electrode [180, paragraph [0006-0009], [00011-00013], Fig. 1-2, 8-9] is positioned lower than the active layer [140, paragraph [0006-00013], Fig. 1-2, 8-9].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Son into the teachings of Chang et al. to include wherein a top most surface of the side electrode is positioned lower than the active layer, for the purpose of improving light extraction efficiency, allowing current to flow uniformly and smoothly, luminous efficiency of the light emitting device can be improved and the operating voltage can be lowered, prevent the second conductive type semiconductor layer from being electrically shorted.
Regarding claim 16, Chang et al. and Son teach the display device according to claim 14.
Chang et al. teaches in another embodiment of the same publication:
wherein the side electrode [1951, paragraph [0195], Fig. 19c-19d] encircles the semiconductor light emitting device [1950, paragraph [0195], Fig. 19c-19d].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of another embodiment of Chang et al. into the teachings of Chang et al. and Son to include wherein the side electrode encircles the semiconductor light emitting device, for the purpose of increasing the electrical contact area, improving electrical contact characteristics, and increasing the lighting rate.
Regarding claim 17, Chang et al. and Son teach the display device according to claim 14.
Chang et al. further teaches:
further comprising a second insulation layer [2120, paragraph [0207], Fig. 21] encircling the semiconductor light emitting device [2150*, Fig. 21] in the predetermined assembly hole [(no number designation), paragraph [0205, 0212], Fig. 21] and between the predetermined assembly hole [(no number designation), paragraph [0205, 0212], Fig. 21] and the assembly barrier wall [2115, Fig. 21].
Regarding claim 19, Chang et al. and Son teach the display device according to claim 14.
Chang et al. further teaches:
wherein the semiconductor light emitting device [2150*, Fig. 21] includes a passivation layer [2157, paragraph [0206-0207], Fig. 21], and
wherein the passivation layer [2157, Fig. 21] is coplanar with a portion of the side electrode [2151, Fig. 21] extending on the side surface.
Claims 4-5, 9-12, 20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (KR 20190104277 A), in view of Son (KR 20110061435 A) and Tomizawa et al. (US 10707378 B2).
Regarding claim 4, Chang et al. and Son teach the display device according to claim 3.
Chang et al. and Son do not teach:
further comprising a third insulating layer disposed on a second side surface of the semiconductor light emitting device and the side electrode.
Tomizawa et al. teaches:
further comprising a third insulating layer [18, Col. 3, Lines 34-36; Col. 14, Lines 1-3, Fig. 12] disposed on a second side surface of the semiconductor light emitting device [15, Col. 2, Lines 24-27; Col. 4, Lines 37-41, Fig. 12] and the side electrode [17a, Col. 3, Lines 34-36, Fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al. and Son to include further comprising a third insulating layer disposed on a second side surface of the semiconductor light emitting device and the side electrode, for the purpose of improving adhesion between features, preventing current leakage, and preventing electrical shorts improving reliability.
Regarding claim 5, Chang et al., Son and Tomizawa et al. teach the display device according to claim 4.
However, Chang et al. and Son do not teach:
further comprising a fourth insulating layer disposed on a third side surface of the semiconductor light emitting device and the third insulating layer.
Tomizawa et al. teaches:
further comprising a fourth insulating layer [72, Col. 13, Lines 3-7, Fig. 12] disposed on a third side surface of the semiconductor light emitting device [15, Fig. 12] and the third insulating layer [18, Fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al., Son and Tomizawa et al. to include further comprising a fourth insulating layer disposed on a third side surface of the semiconductor light emitting device and the third insulating layer, for the purpose of improving adhesion between features, preventing current leakage, and preventing electrical shorts improving reliability.
Regarding claim 9, Chang et al. and Son teach the display device according to claim 1.
Chang et al. further teaches:
wherein the second panel electrode [2140, Fig. 21] is disposed above the second conductivity type semiconductor layer [2155, Fig. 21],
Chang et al. and Son do not teach:
further comprising a first-second panel electrode to be connected to the side electrode and the first assembly electrode or to be connected to the side electrode and the second assembly electrode.
wherein the first-second panel electrode is disposed below the second conductivity type semiconductor layer, and the active layer.
Tomizawa et al. teaches:
further comprising a first-second panel electrode [17d, Col. 3, Lines 1-11, Fig. 12] to be connected to the side electrode [17a, Col. 3, Lines 1-11, Fig. 12] and the first assembly electrode [41, Col. 5, Lines 29-35; Col. 6, Lines 65-67, Fig. 12] or to be connected to the side electrode [17a, Fig. 12] and the second assembly electrode [43, Col. 5, Lines 29-35; Col. 6, Lines 65-67, Fig. 12].
wherein the first-second panel electrode [17d, Fig. 12] is disposed below the second conductivity type semiconductor layer [12, Fig. 12], and the active layer [13, Fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al. and Son to include further comprising a first-second panel electrode to be connected to the side electrode and the first assembly electrode, or to be connected to the side electrode and the second assembly electrode, wherein the first-second panel electrode is disposed below the second conductivity type semiconductor layer, and the active layer, for the purpose of improving electrical connection between features. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Regarding claim 10, Chang et al., Son and Tomizawa et al. teach the display device according to claim 9.
However, Chang et al. and Son do not teach:
wherein the assembly barrier wall comprises a contact hole exposing at least one of the first assembly electrode and the second assembly electrode.
Tomizawa et al. teaches:
wherein the assembly barrier wall [19, Col. 4, Lines 45-49; Col. 4, Lines 55-59, Fig. 7A, 12] comprises a contact hole [82, Col. 4, Lines 45-49; Col. 4, Lines 55-59, Fig. 7A, 12] exposing at least one of the first assembly electrode [41, Fig. 12] and the second assembly electrode [43, Fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al., Son and Tomizawa et al. to include wherein the assembly barrier wall comprises a contact hole exposing at least one of the first assembly electrode and the second assembly electrode, for the purpose of improving electrical connection between features.
Regarding claim 11, Chang et al., Son and Tomizawa et al. teach the display device according to claim 10.
Chang et al., Son and Tomizawa et al. disclose the above claimed subject matter.
However, Chang et al. and Son do not teach:
wherein the assembly barrier wall comprises the contact hole exposing the second assembly electrode, and
wherein the first-second panel electrode is disposed in the contact hole and is connected to the second assembly electrode.
Tomizawa et al. teaches:
wherein the assembly barrier wall [19, Fig. 12] comprises the contact hole [82, Fig. 7A, 12] exposing the second assembly electrode [43, Fig. 12], and
wherein the first-second panel electrode [17d, Fig. 12] is disposed in the contact hole [82, Fig. 7A, 12] and is connected to the second assembly electrode [43, Fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al., Son and Tomizawa et al. to include wherein the assembly barrier wall comprises the contact hole exposing the second assembly electrode, and wherein the first-second panel electrode is disposed in the contact hole and is connected to the second assembly electrode, for the purpose of improving electrical connection between features.
Regarding claim 12, Chang et al. and Son teach the display device according to claim 1.
Chang et al. and Son do not teach:
wherein the side electrode is disposed on an upper surface of the assembly barrier wall.
Tomizawa et al. teaches:
wherein the side electrode [17a, Fig. 12] is disposed on an upper surface of the assembly barrier wall [19, Fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al. and Son to include wherein the side electrode is disposed on an upper surface of the assembly barrier wall, for the purpose of improving electrical connections between features.
Regarding claim 20, Chang et al. and Son teach the display device according to claim 14.
Chang et al. and Son do not teach:
wherein one of the first assembly electrode and the second assembly electrode is electrically connected to the side electrode via a contact hole in the assembly barrier wall.
Tomizawa et al. teaches:
wherein one of the first assembly electrode [41, Fig. 12] and the second assembly electrode [43, Fig. 12] is electrically connected to the side electrode [17a, Fig. 12] via a contact hole [82, Fig. 7A, 12] in the assembly barrier wall [19, Fig. 7A, 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al. and Son to include wherein one of the first assembly electrode and the second assembly electrode is electrically connected to the side electrode via a contact hole in the assembly barrier wall, for the purpose of improving electrical connections between features.
Regarding claim 22, Chang et al. and Son teach the display device according to claim 14.
Chang et al. further teaches:
wherein the panel electrode [2140, Fig. 21] is disposed above the second conductivity type semiconductor layer [2155, Fig. 21],
Chang et al. and Son do not teach:
further comprising a first-second panel electrode to be connected to the side electrode and the first assembly electrode or to be connected to the side electrode and the second assembly electrode,
wherein the first-second panel electrode is disposed below the second conductivity type semiconductor layer, and the active layer.
Tomizawa et al. teaches:
further comprising a first-second panel electrode [17d, Col. 3, Lines 1-11, Fig. 12] to be connected to the side electrode [17a, Col. 3, Lines 1-11, Fig. 12] and the first assembly electrode [41, Col. 5, Lines 29-35; Col. 6, Lines 65-67, Fig. 12] or to be connected to the side electrode [17a, Fig. 12] and the second assembly electrode [43, Col. 5, Lines 29-35; Col. 6, Lines 65-67, Fig. 12],
wherein the first-second panel electrode [17d, Fig. 12] is disposed below the second conductivity type semiconductor layer [12, Fig. 12], and the active layer [13, Fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Tomizawa et al. into the teachings of Chang et al. and Son to include further comprising a first-second panel electrode to be connected to the side electrode and the first assembly electrode or to be connected to the side electrode and the second assembly electrode, wherein the first-second panel electrode is disposed below the second conductivity type semiconductor layer, and the active layer, for the purpose of improving electrical connection between features. See also, MPEP 2144.04(VI)(C) Rearrangement of Parts.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (KR 20190104277 A), in view of Son (KR 20110061435 A) as applied to claim 1 above, and further in view of Park et al. (KR 20190121274 A).
Regarding claim 7, Chang et al. and Son teach the display device according to claim 1.
Chang et al. and Son do not teach:
wherein the semiconductor light emitting device comprises an undoped semiconductor layer disposed under the first conductivity type semiconductor layer.
Park et al. teaches:
wherein the semiconductor light emitting device [1350, paragraph [0162], Fig. 13] comprises an undoped semiconductor layer [1351, paragraph [0162], Fig. 13] disposed under the first conductivity type semiconductor layer [1353, paragraph [0162], Fig. 13].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Park et al. into the teachings of Chang et al. and Son to include wherein the semiconductor light emitting device comprises an undoped semiconductor layer disposed under the first conductivity type semiconductor layer, for the purpose of protecting other features within the device and preventing electrical shorts.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (KR 20190104277 A), in view of Son (KR 20110061435 A) as applied to claim 1 above, and further in view of Hwang et al. (KR 20190105537 A).
Regarding claim 13, Chang et al. and Son teach the display device according to claim 1.
Chang et al. and Son do not teach:
wherein the first side surface of the semiconductor light emitting device is inclined.
Hwang et al. teaches:
wherein the first side surface of the semiconductor light emitting device [1850, paragraph [0193-0194], Fig. 17] is inclined.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hwang et al. into the teachings of Chang et al. and Son to include wherein the first side surface of the semiconductor light emitting device is inclined, for the purpose of forming a wider emission area, increasing luminance at the same current value, preventing short circuits, improving connection between features, uniformly forming subsequent features thereby minimizing reduction in luminous efficacy, and reducing size of device.
Claims 21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (KR 20190104277 A), in view of Son (KR 20110061435 A) and Tomizawa et al. (US 10707378 B2) as applied to claim 9 above, and further in view of Kim et al. (KR 20200026845 A).
Regarding claim 21, Chang et al., Son and Tomizawa et al. teach the display device according to claim 9.
Chang et al., Son and Tomizawa et al. do not teach:
wherein the first-second panel electrode is connected to both the first assembly electrode and the second assembly electrode.
Kim et al. teaches:
wherein the first-second panel electrode [1171, paragraph [0116-0118], [0147] Fig. 13a] is connected to both the first assembly electrode [1120(left), paragraph [0116-0118], [0147], Fig. 13a] and the second assembly electrode [1120(right), paragraph [0116-0118], [0147], Fig. 13a].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kim et al. into the teachings of Chang et al., Son and Tomizawa et al. to include wherein the first-second panel electrode is connected to both the first assembly electrode and the second assembly electrode, for the purpose of shielding electric field formed by the assembly electrode, to prevent self-assembly of the semiconductor light emitting device.
Regarding claim 23, Chang et al., Son and Tomizawa et al. teach the display device according to claim 22.
Chang et al., Son and Tomizawa et al. do not teach:
wherein the first-second panel electrode is connected to both the first assembly electrode and the second assembly electrode.
Kim et al. teaches:
wherein the first-second panel electrode [1171, paragraph [0116-0118], [0147] Fig. 13a] is connected to both the first assembly electrode [1120(left), paragraph [0116-0118], [0147], Fig. 13a] and the second assembly electrode [1120(right), paragraph [0116-0118], [0147], Fig. 13a].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Kim et al. into the teachings of Chang et al., Son and Tomizawa et al. to include wherein the first-second panel electrode is connected to both the first assembly electrode and the second assembly electrode, for the purpose of shielding electric field formed by the assembly electrode, to prevent self-assembly of the semiconductor light emitting device.
Response to Arguments
Applicant’s arguments with respect to independent claims 1 and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant argues on pages 1-5, Section: Rejections under 35 U.S.C. §§102 and 103, in remarks filed February 18, 2026 that the current prior art of record do not teach the amendments to independent claims 1 and 14. Examiner agrees with Applicant; However, after a new line of search and consideration of the prior art, the amended limitations of independent claims 1 and 14 can be overcome by primary reference Chang et al. (KR 20190104277 A), and newly cited source Son (KR 20110061435 A ).
Applicant argues on page 5, Section: Rejections under 35 U.S.C. §§102 and 103, in remarks filed February 18, 2026 that claims dependent on independent claims 1 and 14 should now be in condition for allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
Applicant argues on page 5, Section: New Claims, in remarks filed February 18, 2026 that newly added claims 21-23 should now be in condition or allowance. Examiner disagrees with Applicant for at least the reasons mentioned above.
In summary, the amended limitations of independent claims 1 and 14 can be overcome by primary reference Chang et al. (KR 20190104277 A) and newly cited source Son (KR 20110061435 A). All claims directly or indirectly dependent on independent claims 1 and 14 are also rejected for at least the reasons mentioned above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.M.H./Examiner, Art Unit 2815 03/05/2026
/MONICA D HARRISON/Primary Examiner, Art Unit 2815