Prosecution Insights
Last updated: August 16, 2026
Application No. 17/978,917

REINFORCEMENT LEARNING AND NONLINEAR PROGRAMMING BASED SYSTEM DESIGN

Final Rejection §112
Filed
Nov 01, 2022
Examiner
GEBRESILASSIE, KIBROM K
Art Unit
2189
Tech Center
2100 — Computer Architecture & Software
Assignee
PALO ALTO RESEARCH CENTER Incorporated
OA Round
2 (Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
518 granted / 715 resolved
+17.4% vs TC avg
Strong +25% interview lift
Without
With
+25.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
26 currently pending
Career history
737
Total Applications
across all art units

Statute-Specific Performance

§101
29.0%
-11.0% vs TC avg
§103
35.3%
-4.7% vs TC avg
§102
13.0%
-27.0% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 715 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This communication is responsive to amended application filed on 04/28/2026. Claims 1-20 are presented for examination. Response to Arguments Applicant’s arguments/amendments, see Remarks pgs. 8-11, filed 04/28/2026, with respect to claims 1, and 11 have been fully considered and are persuasive. The rejection of 35 USC 101 has been withdrawn. Applicant’s arguments/amendments, see Remarks pgs. 11-13, filed 04/28/2026, with respect to claims 1 and 11 have been fully considered and are persuasive. The rejection of 35 USC 103(a) has been withdrawn. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains (such as determining the intermediate parameters, the intermediate component parameters as per claims 1, 5, 6, 11, 15, 16, and 17) subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Allowable Subject Matter Claims 1-20 are allowable over prior art. The following is a statement of reasons for the indication of allowable subject matter: Matei et al (US Publication No. 2020/0210532) discloses Abstract, During operation, the system obtains a component library comprising a plurality of physical components, receives design requirements of the physical system, and constructs an initial system model based on physical components in the component library and the design requirements; [0003] One embodiment provides a method and a system for automated design of a physical system. During operation, the system obtains a component library comprising a plurality of physical components, receives design requirements of the physical system, and constructs an initial system model based on physical components in the component library and the design requirements; par [0048] FIG. 5 presents a flowchart illustrating an exemplary process for automated design, according to one embodiment. During operation, the automated design system receives requirements of the physical system (operation 502) and generates an initial system model (operation 504). In some embodiments, the initial system model (e.g., the initial topology) can be generated based on a library of physical components and the requirements of the physical system; [0028] Embodiments described herein solve the technical problem of automated design of physical systems. The automated design system can have a library of physical components (e.g., electrical or mechanical components) and the design process can start with constructing a sufficiently large system topology describing connections among the components. The system can then apply an optimization algorithm to eliminate redundant components in the system topology and learn the best parameters that can meet the design requirements. More specifically, the optimization algorithm can transform an initial multi-objective formulation of the optimization problem into a single objective, constrained nonlinear problem. The nonlinear, constrained optimization problem can be solved using a primal-dual approach. At each update of the dual optimization variables, a model reduction step can be executed to reduce the number of components and simplify the system model; [0050] The initial system topology and the system requirements can be sent into the optimization module, which can use various optimization approaches to optimize the topology (e.g., states of the switches) and parameters of the components. HUANG et al (G. Huang, J. Hu, Y. He, J. Liu, M. Ma, Z. Shen, J. Wu, Y. Xu, H. Zhang, K. Zhong, X. F. Ning, Y. Ma, H. Yang, B. Yu, H. Yang, Y. Wang, “Machine Learning for Electronic Design Automation: A Survey” pgs. 1-44, 2021) discloses pg. 4, 2.2 Machine Learning, ML-based solutions can be categorized according to their learning paradigms: supervised learning, unsupervised learning, active learning, and reinforcement learning. The difference between supervised and unsupervised learning is whether or not the input data is labeled. With supervised or unsupervised learning, ML models are trained on static data sets offline and then deployed for online inputs without refinement. With active learning, ML models subjectively choose samples from input space to obtain ground truth and refine themselves during the searching process. With reinforcement learning, ML models interact with the environment by taking actions and getting rewards, with the goal of maximizing the total reward. These paradigms all have been shown to be applied to the EDA problems … CNN models are composed of convolutional layers a and other basic blocks such as non-linear activation functions and down sample pooling functions; pg. 21, 6.3 Machine Learning for Device Sizing Automation, Based on this optimization model, Wang et al. [148] apply the reinforcement learning technique to deal with device sizing problems. Figure 12 illustrates the proposed reinforcement learning framework. At each environment step, the observations from the simulator are fed to the agent. A reward is calculated by the value network based on current performance. Then, the agent responds with an action to update the device sizes. Because the transistors are both affected by their local status (e.g., transconductance 𝑔𝑚, drain current 𝐼𝑑𝑠 , etc.) and the global status (DC operating points) of the circuit, the optimization of each transistor is not independent. To promote learning performance and efficiency, the authors use a multi-step environment, where the agent receives both the local status of the corresponding transistor and the global status. Although the device sizing problem is automated by the reinforcement learning approach, the training process depends heavily on efficient simulation tools. However, none of the cited prior art references of record fully anticipate or render obvious the independent claims in particular the limitation of: “performing the nonlinear optimization process determines based on the intermediate topology to determine intermediate parameters of the components in the topology based on the model and a loss function, wherein determining the intermediate parameters comprises simulating the model and computing the loss function using a Functional MockupUnit (FMU); and updating the intermediate topology using the RL process based on the intermediate component parameters” as recited in claims 1, and 11. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIBROM K GEBRESILASSIE whose telephone number is (571)272-8571. The examiner can normally be reached M-F 9:00 AM-5:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rehana Perveen can be reached at 571 272 3676. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. KIBROM K. GEBRESILASSIE Primary Examiner Art Unit 2189 /KIBROM K GEBRESILASSIE/ Primary Examiner, Art Unit 2189 05/20/2026
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Prosecution Timeline

Nov 01, 2022
Application Filed
Jan 28, 2026
Non-Final Rejection mailed — §112
Apr 16, 2026
Applicant Interview (Telephonic)
Apr 16, 2026
Examiner Interview Summary
Apr 28, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §112
Aug 04, 2026
Applicant Interview (Telephonic)
Aug 04, 2026
Examiner Interview Summary

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
98%
With Interview (+25.4%)
3y 7m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 715 resolved cases by this examiner. Grant probability derived from career allowance rate.

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