DETAILED ACTION
Claims 1-20 are presented for examination. This Office Action is made in response to the communications filed on November 1, 2022.
Claims 6 and 16 are rejected under 35 USC 112(b) as indefinite.
Claims 1-20 are rejected under 35 USC 101 as ineligible.
Claims 1-6 and 11-16 are rejected under 35 USC 102 as anticipated by Sorkhabi.
Claims 7-10 and 17-20 are rejected under 35 USC 103 as obvious over Sorkhabi in view of Settaluri.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “remote” in claims 6 and 16 is a relative term which renders the claim indefinite. The term “remote” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The claimed positional relationship between the electronic data sources and the workstation is indefinite. For purposes of examination, this will be interpreted to mean that the data is retrieved from as database.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed subject matter is directed to an abstract idea without significantly more.
As an initial matter, the subject matter of the claims, such as designing circuits using reinforcement learning, decision trees, convolutional models, neural networks, and physics-based models was a longstanding practice at the time of filing and well-understood, routine and conventional activity ala the following references of record: Lee et al.; Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.
Independent Claims
Claims 1 and 11
Claim 1 (Statutory Category – Process)
Claim 11 (Statutory Category – Machine)
Step 2A – Prong 1: Judicial Exception Recited?
Yes, the claims recite mental processes, which are abstract ideas.
Claim 11 recites:
[…]
[…] selects/ing a topology through use of a [processing] technique that takes, as input, the received design attribute(s); (Evaluation, Mental Process – Selection of a topology using processing techniques based on design attributes is an evaluation, a mental process that is practically performable in the mind or with the aid of pen and paper. This is evident from the Applicant’s paragraph [0003], which states, “engineers may consider a wide range of different architectures or topologies and the particular configuration of the circuitry may be determined based on desired operating parameters, such as certain input and output specifications.”)
determines/ing one or more design parameter values for one or more design parameters to be used along with the […] selected topology; and (Evaluation, Mental Process – Determining one or more design parameter values for one or more design parameters to be used with topologies is an evaluation, a mental process that is practically performable in the mind or with the aid of pen and paper. This is evident from the Applicant’s paragraph [0003], which states, “engineers may consider a wide range of different architectures or topologies and the particular configuration of the circuitry may be determined based on desired operating parameters, such as certain input and output specifications.”)
[…]
The specified steps of claim 11 are elements of an evaluation, a mental process, which can be performed in the mind of a person or with a pen, paper, or calculator. Being a mental process and a mathematical concept, the method and bolded steps are an abstract idea.
Regarding claim 1, claim 1 recites the method steps carried out by the system of claim 11, so claim 1 recites an abstract idea for at least the same reasons as claim 11.
Claims 1 and 11 recite an abstract idea.
Step 2A – Prong 2: Integrated into a Practical Solution?
No.
Claims 1 and 11 recite the following additional limitations:
An automated topology determination system, comprising one or more electronic processors and non-transitory, computer-readable memory that is accessible by the one or more electronic processors and that stores computer instructions; wherein, when the computer instructions are executed by the one or more electronic processors, the automated topology determination system:
[…]
automatically selects/ing […]
[…] through use of a machine learning (ML) technique […]
[…] automatically selected […]
The computer implementation is a recitation of a general-purpose computer and uses a machine learning technique that is not trained by the method with no specific configurations to execute the claimed method. The generic nature of the computing elements is evident from the following references of record: Lee et al.; Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.) As such, these features implement the recited abstract idea on a generic computer, and, under MPEP 2106.05(f), do not integrate the abstract idea into a practical application in Step 2A Prong Two.
receives/ing, at a workstation, one or more design attributes from a user;
provides/ing the automatically selected topology and determined design parameter value(s) to the user.
These steps are insignificant extra-solution activity similar to the MPEP 2106.05(g) examples: “e.g., a step of obtaining information about credit card transactions, which is recited as part of a claimed process of analyzing and manipulating the gathered information by a series of steps in order to detect whether the transactions were fraudulent.” “e.g., a printer that is used to output a report of fraudulent transactions, which is recited in a claim to a computer programmed to analyze and manipulate information about credit card transactions in order to detect whether the transactions were fraudulent.” “i. Performing clinical tests on individuals to obtain input for an equation,” “iv. Obtaining information about transactions using the Internet to verify credit card transactions” “vi. Determining the level of a biomarker in blood” “iii. Selecting information, based on types of information and availability of information in a power-grid environment, for collection, analysis and display,“ “ii. Printing or downloading generated menus,” Because these steps are insignificant extra-solution activity, under MPEP 2106.05(g), the steps fail to integrate the abstract idea into a practical application at Step 2A, Prong 2.
Further, the specification in the claims of context-specific elements related to lithography are merely tangentially recited, so they merely limit the claims to the particular field of lithography. Under MPEP 2106.05(h), these features fail to integrate the abstract idea into a practical application at Step 2A, Prong 2.
Claims 1 and 11 fail to recite any additional limitations that integrate the abstract idea into a practical application, so claim 11 is directed to the abstract idea.
Claims 1 and 11 are directed to the abstract idea.
Step 2B: Claim provides an Inventive Concept?
No.
Claims 1 and 11 recite the following additional limitations:
An automated topology determination system, comprising one or more electronic processors and non-transitory, computer-readable memory that is accessible by the one or more electronic processors and that stores computer instructions; wherein, when the computer instructions are executed by the one or more electronic processors, the automated topology determination system:
[…]
automatically selects […]
[…] through use of a machine learning (ML) technique […]
[…] automatically selected […]
The computer implementation is a recitation of a general-purpose computer and uses a machine learning technique that is not trained by the method with no specific configurations to execute the claimed method. Also, these features are well-understood, routine, and conventional (WURC) as shown in the following referencs of record: Lee et al.; Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al. As such, these features implement the recited abstract idea on a generic computer, and, under MPEP 2106.05(f), do not combine with the other elements of the claim to provide significantly more than the abstract idea that would confer an inventive concept at Step 2B.
receives/ing, at a workstation, one or more design attributes from a user;
provides/ing the automatically selected topology and determined design parameter value(s) to the user.
These steps are well-understood, routine, and conventional (WURC) activity similar to the MPEP 2106.05(d) examples: “i. Receiving or transmitting data over a network,” “iii. Electronic recordkeeping,” “iv. Storing and retrieving information in memory,” “iv. Presenting offers and gathering statistics,” “vi. Arranging a hierarchy of groups, sorting information, eliminating less restrictive pricing information and determining the price.”
Because these steps are WURC and insignificant extra-solution activity, under MPEP 2106.05(d) and 2106.05(g), they fail to combine with the other elements of the claim to provide significantly more than the abstract idea that would confer an inventive concept at Step 2B.
Further, the specification in the claims of context-specific elements related to lithography are merely tangentially recited, so they merely limit the claims to the particular field of lithography. Under MPEP 2106.05(h), these features fail to combine with the other elements of the claim to provide significantly more than the abstract idea that would confer an inventive concept at Step 2B.
Therefore, there are no additional limitations in claims 1 and 11 that furnish claims 1 and 11 with an inventive concept to ensure that claims 1 and 11, considered as their respective wholes, amount to significantly more than the abstract idea.
Claims 1 and 11 are ineligible.
Dependent Claims
Further, dependent claims 2-10 and 12-20 are ineligible for the following reasons.
Claims 2 and 12
wherein the step of automatically selecting a topology includes automatically selecting a plurality of topologies that includes the automatically selected topology. (This is a repetition of the “automatically selects/ing” steps of the respective independent claims and is an element of the abstract idea for at least the same reasons. This fails to provide any additional limitations to confer eligibility at Step 2A, Prong 2 and at Step 2B.
Accordingly, claims 2 and 12 fail to recite any additional limitations that confer eligibility.
Claims 2 and 12 are ineligible.
Claims 3 and 13
wherein each of the plurality of automatically selected topologies are presented at the workstation and to the user, and (This fails to confer eligibility for the same reasons as the provides/ing steps of the respective independent claims.)
wherein the workstation is configured to allow the user to choose one of the plurality of automatically selected topologies as the automatically selected topology.
First, it should be noted that this does not provide any positive recitation that affects the operation of the process or machine from which the claim depends. That is, the workstation does not conduct any steps of the method of claim 1 and is not an element of the claimed system of claim 11. This merely provides tangential context, which under MPEP 2106.05(h), merely limits the abstract idea to a particular technological field and fails to confer eligibility.
Further, this element is insignificant extra-solution activity similar to the MPEP 2106.05(g) examples: “iii. Presenting offers to potential customers and gathering statistics generated based on the testing about how potential customers responded to the offers; the statistics are then used to calculate an optimized price,” “iv. Obtaining information about transactions using the Internet to verify credit card transactions.” Because this feature is insignificant extra-solution activity, it fails to integrate the abstract idea into a practical application at Step 2A, Prong 2.
Further still, the feature is WURC activity similar to the MPEP 2106.05(d) examples: “i. Receiving or transmitting data over a network,” “iii. Electronic recordkeeping,” “iv. Storing and retrieving information in memory,” “v. Electronically scanning or extracting data from a physical document,” “i. Recording a customer’s order,” “iv. Presenting offers and gathering statistics,” “vi. Arranging a hierarchy of groups, sorting information, eliminating less restrictive pricing information and determining the price.” Because the feature is insignificant extra-solution activity and WURC, the feature fails to combine with the other elements of the claim to provide significantly more than the abstract idea that would confer an inventive concept.
Accordingly, claims 3 and 13 fail to recite any additional limitations that confer eligibility.
Claims 3 and 13 are ineligible.
Claims 4 and 14
wherein the step of determining one or more design parameter values for one or more design parameters is carried out for each of the plurality of automatically selected topologies. (This is a mere repetition of the determining step of the respective independent claim, so it is an element of the abstract idea for at least the same reasons as the selecting step of the respective independent claim.)
Accordingly, claims 4 and 14 fail to recite any additional limitations that confer eligibility.
Claims 4 and 14 are ineligible.
Claims 5 and 15
wherein the ML technique is a decision tree technique in which the received design attribute(s) are used as input into a decision tree.
The use of a decision tree is a generic computing operation recited at a high level (e.g., without any implementation details or specific configurations), so it fails to confer eligibility under MPEP 2106.05(f) for at least the same reasons as the other computer elements of the independent claims.
Also, the features of this method are WURC according to the teachings of the following references of record: Lee et al.; Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.
Accordingly, claims 5 and 15 fail to recite any additional limitations that confer eligibility.
Claims 5 and 15 are ineligible.
Claims 6 and 16
wherein the decision tree is trained with training data using decision tree learning, and (This is akin to stating that machine learning training is done using machine learning training data. This is a generic computing operation recited at a high level with no specific configuration, so, under MPEP 2106.05(f), it fails to confer eligibility.)
Also, the features of this method are WURC according to the teachings of the following references of record: Lee et al.; Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.
wherein the training data is obtained from one or more electronic data sources that are remote to the workstation. (This is insignificant extra-solution activity and WURC for the same reasons as the receives/ing and provide/ing steps of the respective independent claims, so it fails to confer eligibility for at least the same reasons as those steps in the respective independent claims.)
Accordingly, claims 6 and 16 fail to recite any additional limitations that confer eligibility.
Claims 6 and 16 are ineligible.
Claims 7 and 17
wherein the step of determining one or more design parameter values for one or more design parameters includes using a reinforcement learning (RL) technique. (The use of reinforcement learning is the use of a generic computing technique recited at a high level of generality without any specific configurations or modifications. Therefore, under MPEP 2106.05(f), this feature fails to confer eligibility.)
Also, the features of this method are WURC according to the teachings of the following references of record: Lee et al.; Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.
Accordingly, claims 7 and 17 fail to recite any additional limitations that confer eligibility.
Claims 7 and 17 are ineligible.
Claims 8 and 18
wherein the step of determining one or more design parameter values for one or more design parameters includes using the [processing] technique in combination with a simulation […]. ( Determining design parameters based on an acted out simulation of a scenario is a longstanding practice that is used in many contexts including staging a play (e.g., setting up a scale paper model of a stage and determining blocking for the actors). This is practically performable in the mind or with the aid of pen and paper, so it is an evaluation, a mental process, an element of the abstract idea. Because it is an element of the abstract idea, it does not recite an additional limitation that can confer eligibility.)
RL technique […] model […] (The generic recitation of a reinforcement learning technique and a model is a generic computing implementation recited at a high level without any specific implementation details. Therefore, under MPEP 2106.05(f), these generic computing features fail to confer eligibility.)
Also, the features of this method are WURC according to the teachings of the following references of record: Lee et al.; Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.
Accordingly, claims 8 and 18 fail to recite any additional limitations that confer eligibility.
Claims 8 and 18 are ineligible.
Claims 9 and 19
wherein the simulation model is a surrogate model that models a physics-based simulation.
Physics-based models are standard computing elements recited at a high level of generality without any particular limiting features. Therefore, under MPEP 2106.05(f), this feature fails to confer eligibility.
Also, using reinforcement learning with physics-based simulations is well-understood, routine, and conventional activity, as evidenced, under Berkheimer, by the following references of record: Lee et al. Abstract “In this work, we present a learning based approach to analog circuit design, where the goal is to optimize circuit performance subject to certain design constraints. […] Therefore, to better facilitate supporting the human designers, it is desirable to gain knowledge about the whole space of feasible solutions. In order to tackle these challenges, we take inspiration from model-based reinforcement learning and propose a method with two key properties. First, it learns a reward model, i.e., surrogate model of the performance approximated by neural networks, to reduce the required number of simulation. […] The results show that, compared to the model-free method applied with 20,000 circuit simulations to train the policy, DynaOpt achieves even much better performance by learning from scratch with only 500 simulations.”; These other references of record provide similar recitations: Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.
Accordingly, claims 9 and 19 fail to recite any additional limitations that confer eligibility.
Claims 9 and 19 are ineligible.
Claims 10 and 20
wherein the surrogate model is implemented at least in part by a neural network.
Surrogate simulations models implemented at least partially by neural networks are standard computing elements recited at a high level of generality without any particular limiting features. Therefore, under MPEP 2106.05(f), this feature fails to confer eligibility.
Also, surrogate simulations models implemented at least partially by neural networks are well-understood, routine, and conventional activity, as evidenced, under Berkheimer, by the following references of record: Lee et al. Settluri et al.; Sun et al.; Zhao et al.; Zhao et al.; Chentanez et al.; Freeman et al.; Lu et al.; Peng et al.; Sun et al.; Wang et al.; Zhao et al.
Accordingly, claims 10 and 20 fail to recite any additional limitations that confer eligibility.
Claims 10 and 20 are ineligible.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over NPL: “Automated topology synthesis of analog and RF integrated circuits: A survey” by Sorkhabi et al. (Sorkhabi).
Claims 1 and 11
Regarding claim 11, Sorkhabi teaches:
An automated topology determination system, comprising one or more electronic processors and non-transitory, computer-readable memory that is accessible by the one or more electronic processors and that stores computer instructions; wherein, when the computer instructions are executed by the one or more electronic processors, the automated topology determination system:
(Sorkhabi Page 128, Introduction “There has always been a perpetual inclination toward automation for the complex tasks that were conventionally done purely with human effort. That is because the concept of automation usually accompanies with higher speed, lower human endeavor, less errors, and higher productivity [1]. The design task of electronic systems and integrated circuits (ICs) has not been an exception. […] One aspect of the digital design, which has paved the way for the prosperous development of EDA methods in the digital domain, is that the specifications of the digital circuits can be easily defined by using either Boolean functions or behavioral description in a hardware description language (e.g., VHDL or Verilog). This step in the digital design flow is called design entry. In the case of behavioral level description, digital synthesis tools can convert the design entry to structural and subsequently to gate level descriptions. The validity of the design is checked through test platforms to ensure the satisfaction of the functional requirements specified by the system specifications as well as timing requirements.” – This study concerns the automated determination of topologies for analog and digital circuits using computing platforms with memory and a processor configured to execute routines. Page 132, Right Column, Fourth Paragraph “A novel low-voltage low-power amplifier was synthesized in [51] based on the strategy proposed in [46] to use a combination of abstract and physical features as the starting ideas in the synthesis procedure. To this end, a hierarchical graph-based knowledge structure at different abstraction levels including design features of low-voltage low-power OpAmps is utilized.” – One example circuit considered for design is an amplifier, which is a power converter.)
receiving, at a workstation, one or more design attributes from a user; (Sorkhabi Page 128, Right Column, Second Paragraph “In contrast, the first decision to make in the analog design flow is to provide an appropriate topology based on a set of functional specifications. In the case of larger or system-level designs, an additional decomposition step is to be taken to decompose the top-level structure into sub-circuits so that the overall combination satisfies the given functional specifications for the top-level structure. Behavioral simulations are performed to verify that the mapping from specifications to sub-circuits is correctly managed.” Page 130, Left Column, First Paragraph “The intensive-knowledge-based techniques embrace comprehensive circuit design knowledge, such as decision trees or trade-off database for design parameters obtained by a laborious human effort. These techniques often accompany the topology selection or the topology refinement methods.” – Users provide information to a computer for automated design analysis.)
automatically selecting a topology through use of a machine learning (ML) technique that takes, as input, the received design attribute(s); (Sorkhabi Page 134, Left Column, Second Paragraph “In ANTIGONE [35,66] an embryonic circuit is chosen based on a set of equations describing the functionality of the design. The performance of the design is calculated and fed into an evaluator, which determines the satisfaction level as a number between 0 and 1. A global satisfaction level is also defined to determine the best design in the population and execution termination of the algorithm. If the optimization continues, the designs with low satisfaction levels will be removed so that the population would be simplified. To improve the satisfaction level, a series of transformations can be applied both on the architecture and parameter values in the form of knowledge-based, equation-based or statistical transformations within a tree structure. This process continues until the desired results are achieved.” – A tree based-topology ML model is used to select/determine an initial topology for the converter.)
determining one or more design parameter values for one or more design parameters to be used along with the automatically selected topology; and (Sorkhabi Page 132, Left Column, First-Second Paragraphs “Topology refinement is aimed to modify an existing structure with alternative building blocks to improve the performance of the current topology. [..].] They believe that the black box methods are not an appropriate approach for analog circuit design; instead in every single synthesis step the trade-off among circuit parameters must be taken into consideration to guide the synthesis process towards the right and meaningful direction. In this review paper, this concept is treated as a complementary stream to topology selection. […] To this end, a feature clustering method, called ordered node cluster representation (ONCR), is utilized. A library of circuits with common functionality is provided and their equivalent uncoupled building block behavioral (UBBB) models, which are actually directed signal flow graphs (SFG), are extracted. Therefore, each circuit is represented by a set of nodes and two sets of symbolic expressions to identify the poles and the couplings between nodes. Then the nodes are matched based on similar AC behavior considering the poles and the outgoing couplings. A simulated-annealing-based scheme helps identify the classification curves through circuit nodes, which can offer the highest similarities. Clusters of the matched nodes from different circuits will be generated during this matching procedure.“ – Parameter values, such as AC behavior metrics, are determined and used to refine a selected/generated topology.)
providing the automatically selected topology and determined design parameter value(s) to the user. (Sorkhabi Page 129, Left Column, First Paragraph “As depicted in Fig. 2, three design levels including system-level synthesis, circuit-level synthesis, and layout-level synthesis, are enclosed when converting an innovative idea to an analog/RF IC chip or intellectual property block. The regular triangle indicates the implementation flow from idea to chip, while the inverse triangle (in gray shadow) exhibits the config uration space difference among distinct levels. Although commercial offerings have started to appear in some fields such as circuit-level sizing and layout-level synthesis [10], the research in these fields are still in progress to incorporate more advanced analog design concepts into the automation flow to elevate the quality of these tools. Recent developments comprise yield-aware [11] and parasitic-aware [12] design automation, which take the aging, yield, and secondary effects into account during the sizing and layout generation [13,14].” Page 132, Left Column, First Paragraph “Topology refinement is aimed to modify an existing structure with alternative building blocks to improve the performance of the current topology.” Page 133, Left Column, First Paragraph “Topology generation methods, as the name indicates, aim to generate a topology from scratch. Instead of selecting a definitive structure from a library, the algorithm creates new circuit topologies by connecting together the basic components and sub-circuits, often provided from a library of basic building blocks. Different strategies have been devised over the past two decades to tackle topology generation problem. Apart from the tools to combine the circuit components, the problem is encoded into four different schemes, namely graph-based, tree-based, string-based, and heuristic methods. The following sub-sections will discuss this topic in more detail.” Page 134, Right Column, Third Paragraph “The highly challenging nature of the topology synthesis problem and lack of definite solutions have urged the researchers to leverage the merits of different strategies by combining them together to overcome this puzzle. It is a bit difficult to specify exact boundaries among different topology synthesis strategies. The contributions in [76,77] are some examples in this respect.” See Also Fig. 2 (Shown below) –After the system generates/selects a topology, the topology is refined. Each stage of synthesis includes an output, as illustrated in Fig. 2, below.)
PNG
media_image1.png
798
1405
media_image1.png
Greyscale
Regarding claim 1, claim 1 is the method executed by the system of claim 11 and is rejected for at least the same reasons as claim 11.
Claims 2 and 12
Regarding claim 12, Sorkhabi teaches the features of claim 11 and further teaches:
wherein, when the computer instructions are executed by the one or more electronic processors, the automated topology determination system automatically selects a plurality of topologies that includes the automatically selected topology. (NOTE: The claim is sufficiently broad to encompass a repetition of steps, so it is taught by the reference in the same manner as the automated selection step in the independent claim. Also, Sorkhabi Page 133, 4.4.2 Tree-based topology generation method “Sripramong and Toumazou [21] proposed a tree-based bottom-up GP approach to generate topology structures. A design optimization method called current-flow analysis was utilized to correct the structures in each step. The circuits in the first generation are the result of an embryonic structure (varying from a single wire to a complete OpAmp) evolved with mutation operation, which is then sent through current flow analysis. A series of current flow lists is then created to describe the component connections based on the current flow in the circuit. Any correction rule, including altering component interconnects, removing isolated parts, and removing the parts without any effect on performance, is done within the current flow lists. The remaining circuits are then evaluated for fitness values.” – In this learning tree method, multiple circuits are evaluated with one eventually being selected.)
Regarding claim 2, claim 12 is the method executed by the system of claim 12 and is rejected for at least the same reasons as claim 12.
Claims 3 and 13
Regarding claim 13, Sorlhabi teaches the features of claim 12 and further teaches:
wherein each of the plurality of automatically selected topologies are presented at the workstation and to the user, and wherein the workstation is configured to allow the user to choose one of the plurality of automatically selected topologies as the automatically selected topology. (Sorkhabi Page 136 “However, there is no doubt that an automated analog/RF topology synthesis EDA method can well support the designers who are new into the analog/RF IC design area and provide insight about the overall design procedure for those who are not yet qualified professionals. Moreover, it is possible to gain impressive productivity by using a proven automated topology synthesis methodology provided that the design specifications and contexts are alike for an array of similar applications.“ – The current systems still require input from experts on design. Page 133, 4.4.2 Tree-based topology generation method “Sripramong and Toumazou [21] proposed a tree-based bottom-up GP approach to generate topology structures. A design optimization method called current-flow analysis was utilized to correct the structures in each step. The circuits in the first generation are the result of an embryonic structure (varying from a single wire to a complete OpAmp) evolved with mutation operation, which is then sent through current flow analysis. A series of current flow lists is then created to describe the component connections based on the current flow in the circuit. Any correction rule, including altering component interconnects, removing isolated parts, and removing the parts without any effect on performance, is done within the current flow lists. The remaining circuits are then evaluated for fitness values. Upon unsatisfactory results, an iterative process of producing new generations continues until some desired results are obtained. Despite incorporating some sort of design knowledge in this work, not all the runs could lead to desired outcomes as observed by the authors. In addition, some problems exist even for the successful runs where the proposed method for identifying transistor operating regions is not effective enough to discriminate between triode and saturation regions.” Page 131 “As mentioned earlier, the pioneer research work in the field of topology synthesis started to utilize the topology selection methods. In early attempts, desired topologies might be selected by users, and the behavioral models, which are in-depth analytic equations, can also be extracted by human designers.” – In this learning tree method, multiple circuits are evaluated with one eventually being selected. The process is iterative. See Also Fig. 2 (Shown below) –After the system generates/selects a topology, the topology is refined. Each stage of synthesis includes an output, as illustrated in Fig. 2, below.)
PNG
media_image1.png
798
1405
media_image1.png
Greyscale
Regarding claim 3, claim 13 is the method executed by the system of claim 13 and is rejected for at least the same reasons as claim 13.
Claim 4 and 14
Regarding claim 14, Sorlhabi teaches the features of claim 12 and further teaches:
wherein the step of determining one or more design parameter values for one or more design parameters is carried out for each of the plurality of automatically selected topologies. (NOTE: Because the operations of claim 12 are merely repetitions of steps, the reference teaches repeating each of the steps for each of the designs. Also, Sorkhabi Page 132, Left Column, First-Second Paragraph “Topology refinement is aimed to modify an existing structure with alternative building blocks to improve the performance of the current topology. Usually the authors, who are motivated to walk along this path, believe that the process of analog circuit design is more like a decision-making process rather than a generation procedure from scratch. They believe that the black box methods are not an appropriate approach for analog circuit design; instead in every single synthesis step the trade-off among circuit parameters must be taken into consideration to guide the synthesis process towards the right and meaningful direction. In this review paper, this concept is treated as a complementary stream to topology selection. We categorize the refinement process appearing in the literature into the following two branches. […] A library of circuits with common functionality is provided and their equivalent uncoupled building block behavioral (UBBB) models, which are actually directed signal flow graphs (SFG), are extracted. Therefore, each circuit is represented by a set of nodes and two sets of symbolic expressions to identify the poles and the couplings between nodes. Then the nodes are matched based on similar AC behavior considering the poles and the outgoing couplings. A simu lated-annealing-based scheme helps identify the classification curves through circuit nodes, which can offer the highest similarities. Clusters of the matched nodes from different circuits will be generated during this matching procedure.” – The different iteratively determined topologies are selected and different topology and refinement adjustments are made abased on the simulated annealing. Clusters of matched nodes are generated.)
Regarding claim 4, claim 14 is the method executed by the system of claim 14 and is rejected for at least the same reasons as claim 14.
Claims 5 and 15
Regarding claim 15, Sorkhabi teaches the features of claim 11 and further teaches:
wherein the ML technique is a decision tree technique in which the received design attribute(s) are used as input into a decision tree. (Sorkhabi Page 133, 4.4.2. Tree-based topology generation method “Sripramong and Toumazou [21] proposed a tree-based bottom-up GP approach to generate topology structures. A design optimization method called current-flow analysis was utilized to correct the structures in each step. The circuits in the first generation are the result of an embryonic structure (varying from a single wire to a complete OpAmp) evolved with mutation operation, which is then sent through current flow analysis. A series of current flow lists is then created to describe the component connections based on the current flow in the circuit. Any correction rule, including altering component interconnects, removing isolated parts, and removing the parts without any effect on performance, is done within the current flow lists. The remaining circuits are then evaluated for fitness values. Upon unsatisfactory results, an iterative process of producing new generations continues until some desired results are obtained.” – This teaches using decision trees based on the input elements to select/generate the topologies.)
Regarding claim 5, claim 15 is the method executed by the system of claim 15 and is rejected for at least the same reasons as claim 15.
Claims 6 and 16
Regarding claim 16, Sorkhabi teaches the features of claim 15 and further teaches:
wherein the decision tree is trained with training data using decision tree learning, and wherein the training data is obtained from one or more electronic data sources that are remote to the workstation. (Sorkhabi Page 130 “” Page 134, Left Column, Second Paragraph “In ANTIGONE [35,66] an embryonic circuit is chosen based on a set of equations describing the functionality of the design. The performance of the design is calculated and fed into an evaluator, which determines the satisfaction level as a number between 0 and 1. A global satisfaction level is also defined to determine the best design in the population and execution termination of the algorithm. If the optimization continues, the designs with low satisfaction levels will be removed so that the population would be simplified. To improve the satisfaction level, a series of transformations can be applied both on the architecture and parameter values in the form of knowledge-based, equation-based or statistical transformations within a tree structure. This process continues until the desired results are achieved. However, the proposed method seems quite computationally expensive and the repeated optimization-evaluation stages would even lengthen the process to reach the final result. Moreover, the reported experiments only cover data converters at the system level.” Page 131, Left Column– The decision tree is a decision tree trained by decision tree methods, and the data is obtained from a database.)
Regarding claim 6, claim 16 is the method executed by the system of claim 16 and is rejected for at least the same reasons as claim 16.
Claim Rejections - 35 USC § 103
Claim(s) 7-10 and 17-20 are rejected under 35 U.S.C.103 as being unpatentable over NPL: “Automated topology synthesis of analog and RF integrated circuits: A survey” by Sorkhabi et al. (Sorkhabi) in view of NPL: “AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs” by Settaluri et al. (Settaluri).
Claims 7 and 17
Regarding claim 17, Sorkhabi teaches the features of claim 11, but does not appear to explicitly teach, but Sorkhabi in view of Settaluri teaches:
wherein the step of determining one or more design parameter values for one or more design parameters includes using a reinforcement learning (RL) technique. (Settaluri Abstract “This work presents AutoCkt, a machine learning optimization framework trained using deep reinforcement learning that not only finds post-layout circuit parameters for a given target specification, but also gains knowledge about the entire design space through a sparse subsampling technique. – This uses a reinforcement learning technique to improve selected topologies based on specified parameters.)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claims to modify the automated circuit design of Sorkhabi by the AutoCkt methods of Settaluri because the person of ordinary skill in the art would be motivated by the stated aim in the art presented in Sorkhabi to expedite automation of circuit designs and the teaching of combining different methods to look to the AutoCkt method of Settluri, which provides circuit designs that meet specifications the vast majority of the time in significantly less time. (Sorkhabi Page 128, 1. Introduction “There has always been a perpetual inclination toward automation for the complex tasks that were conventionally done purely with human effort. That is because the concept of automation usually accompanies with higher speed, lower human endeavor, less errors, and higher productivity [1].” Page 134, Right Column, Third Paragraph “The highly challenging nature of the topology synthesis problem and lack of definite solutions have urged the researchers to leverage the merits of different strategies by combining them together to overcome this puzzle. It is a bit difficult to specify exact boundaries among different topology synthesis strategies. The contributions in [76,77] are some examples in this respect.”; Settaluri Abstract “This work presents AutoCkt, a machine learning optimization framework trained using deep reinforcement learning that not only finds post-layout circuit parameters for a given target specification, but also gains knowledge about the entire design space through a sparse subsampling technique.”
Regarding claim 7, claim 17 is the method executed by the system of claim 17 and is rejected for at least the same reasons as claim 17.
Claims 8 and 18
Regarding claim 18, Sorkhabi in view of Setttaluri teaches the features of claim 17 and further teaches:
wherein the step of determining one or more design parameter values for one or more design parameters includes using the RL technique in combination with a simulation model. (Settaluri Page 2 “Figure 1 shows the system level diagram for this algorithm: the two main blocks are the reinforcement learning agent and
simulation environment, discussed further below.” See Also Fig. 1. (Shown Below) – The RL technique is used in combination with a simulation model.)
PNG
media_image2.png
373
581
media_image2.png
Greyscale
Regarding claim 8, claim 18 is the method executed by the system of claim 18 and is rejected for at least the same reasons as claim 18.
Claims 9 and 19
Regarding claim 19, Sorkhabi in view of Setttaluri teaches the features of claim 18 and further teaches:
wherein the simulation model is a surrogate model that models a physics-based simulation. (Settaluri Page 3, B. Simulation Environment “In this work, we demonstrate results using a simulator that works on predictive technology models and Spectre, which run on schematic level simulations, as well as the Berkeley Analog Generator (BAG), which runs simulations in Cadence with layout parasitics automatically.” Page 5, Right Column, Second Paragraph “We demonstrate the usage of transfer learning to show that an RL agent trained by running inexpensive schematic simulations is able to transfer it’s knowledge to a different environment. This new environment, which then runs PEX simulations, is then used to deploy the agent. Figure 13 shows this idea. Note that no training is done once the environment has changed to post-layout extraction..” – The simulation model is a surrogate model that models a physics-based simulation.)
Regarding claim 9, claim 19 is the method executed by the system of claim 19 and is rejected for at least the same reasons as claim 19.
Claims 10 and 20
Regarding claim 20, Sorkhabi in view of Setttaluri teaches the features of claim 19 and further teaches:
wherein the surrogate model is implemented at least in part by a neural network. (Settaluri Page 2, A. The Reinforcement Learning Agent “At each environment step, the RL agent, which contains a neural network, observes the state of the environment and takes an action based on what it knows. The environment then returns a new state that is used to calculate the reward for taking that particular action.“ Page 5 “We demonstrate the usage of transfer learning to show that an RL agent trained by running inexpensive schematic simulations is able to transfer it’s knowledge to a different environment. This new environment, which then runs PEX simulations, is then used to deploy the agent. Figure 13 shows this idea.” See Also Figs. 2 and 13. (Shown Below)– The PEX simulations rely on the transferred knowledge of the RL agent, which uses a neural network.)
PNG
media_image3.png
304
607
media_image3.png
Greyscale
PNG
media_image4.png
235
618
media_image4.png
Greyscale
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
NPL: “Physics-based motion capture imitation with deep reinforcement learning” by Chenantez et al. (Teaches physics-based RL methods)
NPL: “Simplified Digital Logic Circuits using binary Decision Tree” by Fawareh et al. (Teaches physics-based RL methods)
NPL: “Speeding Up Reinforcement Learning with a New Physics Simulation Engine" by Freeman et al. (Teaches physics-based RL methods)
NPL: “Reinforcement Learning and Physics by Guerrero (Teaches physic-based RL methods)
NPL: “Analog Circuit Generator based on Deep Neural Network enhanced Combinatorial Optimization” by Hakhamaneshi et al. (Teaches generating circuit designs using ML)
NPL: “BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks” by Hakhamaneshi et al. (Teaches generating circuit designs using ML)
NPL: “AUTOMATED DESIGN OF BOTH THE TOPOLOGY AND SIZING OF ANALOG ELECTRICAL CIRCUITS USING GENETIC PROGRAMMING” by Koza et al. (Teaches an ML method for selection and optimization of circuit topologies)
NPL: “Machine Learning based Modeling of Power Electronic Converters.” By Krishnamoorthy et al. (Teaches ML modeling of power converters)
NPL: “Analog Circuit Design with Dyna-Style Reinforcement Learning” by Lee et al. (Teaches circuit design by RL)
NPL: “TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs” by Lu et al. (Teaches GNN method for designing ICs)
NPL: “Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks” by McConaghy et al. (Teaches generating circuit topologies using ML)
NPL: “DeepMimic: Example-Guided Deep Reinforcement Learning of Physics-Based Character Skills” by Peng et al. (Teaches using physics-based RL)
NPL: “Analog Circuit Topology Synthesis by Means of Evolutionary Computation” by Rojec et al. (Teaches using ML to design circuit topologies.
NPL: “GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning” by Wang et al. (Teaches using GNN and RL to design circuits)
NPL: “Circuit-GNN: Graph Neural Networks for Distributed Circuit Design” by Zhang et al. (Teaches using GNNS to design circuits)
NPL: “Deep Reinforcement Learning for Analog Circuit Sizing” by Zhao et al. (Teaches RL for analog circuit design)
NPL: “An Overview of Artificial Intelligence Applications for Power Electronics” by Zhao et al. (Teaches a series of ML methods for power electronics)
NPL: “Design of Multi-Output Switched-Capacitor Voltage Regulator via Machine Learning “ by Zhou et al. (Teaches design of a voltage regulator using ML)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY MICHAEL WHITE whose telephone number is (571) 272-7073. The examiner can normally be reached Mon-Fri 11:00-7:00 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ryan Pitaro can be reached at (571) 272-4071. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.M.W./Examiner, Art Unit 2188
/RYAN F PITARO/Supervisory Patent Examiner, Art Unit 2188