DETAILED ACTION
Response to Arguments
Applicant's arguments filed on 3/12/2026 have been fully considered but they are not persuasive. The examiner has thoroughly reviewed Applicant’s amendment and arguments but firmly believes that the cited references reasonably and properly meet the claimed limitation as rejected.
1). Applicant’s argument – The rejections are traversed because all of the rejections rely on Palmer and Samani, even if combinable, to satisfy certain features not taught or suggested by them. In particular, the Action relies on Palmer and Samani to satisfy claimed features directed to adjusting photodiodes in a receive path based on test signals (e.g., from a test stimulus circuit) injected into the receive path and adjusting the photo diodes based on an algorithmic logic circuitry analysis of the fedback test signals. For example, the application discusses this as follows:
Referring still to FIG. 3, a test stimulus 302 can include an amplitude modulated (AM) signal generated from a first in- phase/quadrature (IQ) digital-to-analog (DAC) pair 304, 306 input to a driver circuit/ s 308, 310 and a modulator block 312 .... (Application at 0024).
In aspects, by using the transmit laser 329 to generate the input stimulus and using the transmit laser 329 as the LO stimulus, the down-converted signal should be equal in frequency to the test stimulus that was input to the DACs 304, 306. This can minimize complexity in algorithm support as described later herein. (Application at 0025).
Referring again to FIG. 3 , the receiver circuitry takes feedbacks of the ADCs 374, 376, 378, 380, performing Fast-Fourier Transform (FFT) 382 of the feedback signals, and providing the ADCs 374, 376, 378, 380 to an adaptive filter 384. The adaptive filter 384 can comprise algorithmic logic circuitry that can execute one or more of a LMS algorithm, a Kalman filter, or a minimum mean-squared error (MMSE) algorithm. (Application at 0034).
Palmer does teach a transceiver with a loop back test capability for calibrating its receiver, and it does this with a laser source common to its Tx and Rx. However, nowhere does it indicate what type of test signal is to be injected, how it is injected and how its received version is analyzed, diagnosed and then used to adjust part of its Rx, let alone its photodiodes. Samani teaches calibrating differential photodiodes in an optical RX but exclusively to balance the photodiodes to minimize common mode distortions. For example, Samani states:
To optimize the CMRRSIG,LO parameter, the TIA 30 will provide an output (PIN,CM) 38 that indicates the electrical power of the AC common-mode input signal. The receiver control processor 36 will dynamically adjust MP (VAPDP) and MN (VAPDN) to achieve the lowest common-mode input power PIN,CM possible. (Samani at 0055).
This is all it does. It doesn't teach an approach with a flexible test stimulus capability and diagnostic analysis logic to more surgically calibrate different photo-diodes differently to achieve desired, optimal operations
Examiner’s response – In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “based on test signals (e.g., from a test stimulus circuit) injected into the receive path”, “a flexible test stimulus capability” and “diagnostic analysis logic”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The claims do not introduce a “test stimulus circuit”, “a flexible test stimulus capability” and “diagnostic analysis logic”, as well as “test signal”.
And, Applicant’s claims also do not clearly “indicate what type of test signal is to be injected, how it is injected and how its received version is analyzed, diagnosed and then used to adjust part of its Rx, let alone its photodiodes”.
Claim Objections
Claim 6 is objected to because of the following informalities: the phrase “The apparatus of claim 2” should be changed to “The apparatus of claim 1”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, and thus depending claims 3-11, recites the limitations “a variable voltage source that is coupled to at least one diode of the photo diodes to control the responsivity of the at least one diode”; it is not clear whether the “one diode” is a photo diode. Commonly, a diode is a two-terminal electronic component that conducts electric current primarily in one direction. But, from the phase “one diode of the photo diodes”, it seems the claimed “one diode” is a photo diode. Also, in claim 1, there are three terms are associated with photodiode(s): “a pair of photodiodes” (lines 8-9), “at least one diode” and “the photo diodes” (line 13). Are all these terms are used to indicate photodiode(s)? (Note: hereinafter, the claimed “diode” is interpreted as a photodiode).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-14 and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer et al (US 2020/0280373) in view of Samani et al (US 2022/0336691).
1). With regard to claim 1, Palmer et al discloses an apparatus (Figures 2-5 and 8 etc.) comprising:
optical circuitry (105 in Figure 3, or 303 in Figure 5) configured to provide an optical signal source ([0056] and [0066]) to be divided into a plurality of paths (one to EO 120, another to OE 130 in Figure 3, by the light source port (splitter) 115; or Figure splitter 351), a first path of the plurality of paths being input into an optical modulator (Figure 3, the TX circuit 120, [0056], “an optical modulator”. Figure 5, 320X and 320Y, “The dual optical Tx circuit 320 is embodied as an optical modulator circuit (OMC) formed of a first optical modulator 320X and a second optical modulator 320Y”), an output of the optical modulator being coupled to an input port of a first optical receiver (Figure 3: the output from the EO 120 is coupled to input port of a first optical receiver 130 via the loopback optical circuit (LOC) 40. Figure 5: the outputs from X-MOD 320X and Y-MOD 320Y are coupled to an input port of a first optical receiver 330) and, a second path (from 115 to 132; or from 351 to 330) of the plurality of paths being provided to a local oscillator port of the first optical receiver (Figure 3, the port 132; Figure 3, the two ports 333);
the first optical receiver comprising at least one coupler ([0054], “The optical Rx circuit 32 may include one or more photodetectors (PDs), and may also include one or more optical couplers and/or one or more optical mixers such as optical hybrids.”; Figure 5, the optical hybrids OH 330Y and 330X), an output of the coupler configured to provide input to at least one differentially configured pair of photodiodes ([0054], “The optical Rx circuit 32 may include one or more photodetectors (PDs)”; and Figure 5, PDs 336), the photodiodes currents output being operably coupled to an analog to digital converter (ADC) ([0051], “The data sink 36 performs digital signal processing on the electrical Rx signal or signals 35, after their conversion into the digital form by a suitable analog to digital converter (ADC, not shown), to extract transmitted data therefrom”. Figure 5, the output from the PD circuit 338 are sent “To processor 350”, and the processor 350 is a “digital signal processor”, [0080]; that is, an ADC is performed between the analog electrical circuitry 360 and the digital signal processor 350).
But, Palmer et al does not expressly disclose: feedback circuitry configured to provide outputs of the ADC to an algorithmic logic circuitry, the algorithmic logic circuitry being coupled to a variable voltage source that is coupled to at least one diode of the photo diodes to control the responsivity of the at least one diode.
However, Palmer et al discloses “module settings that are found during factory calibration under laboratory conditions may not match optimal settings in the field. The need for module calibration in the field further increases with the rise of new transceiver platforms that separate the digital electrical data processing unit from an analogue electro-optic conversion engine. For example CFP2-ACO hot-pluggable optical transceiver modules may be hosted in the field on printed circuit boards (PCB) that are sourced separately from the pluggables. Consequently, the digital host unit and the analogue pluggable optical transceiver are calibrated in their respective factory independently, and their optimal settings may not match. However calibration of conventional transceiver modules typically requires on-site technical personal and thus may be too costly to perform in the field” ([0004]) and “[t]he integrated optical loopback enables a flexible and precise in-field calibration of the transceiver, for example during an automatic start-up sequence of a transponder incorporating the transceiver, which results in an overall improvement of the transponder performance. The in-field transceiver calibration, as enabled by the integrated optical loopback, avoids the propagation of uncertainty of calibration data in traditional transceivers, in which digital and analog interfaces, although hosted on a same PCB, are calibrated separately at their respective manufacturing facilities” ([0049]), “the ability to identify contributions of the Tx and Rx signal path to the distortion would facilitate transceiver calibration and optimization” ([0083]), and “A transmission quality measure, such as for example the bit error ratio (BER), the Q-factor as a measure of the eye opening, the error vector magnitude (EVM), or any other suitable transmission quality measure, may be used to optimize the distortion parameter being measured” ([0088]). That is, the loopback mode is used to calibrate and optimize the transmitter/receiver. And the photodiode is one component in the optical receiver, and the each photodiode has a voltage source; that is, the voltage to the photodiode is one of the parameters needs to be “calibrated”/“optimized” or controlled. Therefore, for the control/calibration mechanism disclosed by Palmer et al it is obvious to one skilled in the art that the output from the digital signal processor (350 etc.) is used as a feedback to control the voltages of the photodiodes so that the receiver is “calibrated” and “optimized”.
Samani et al discloses a coherent optical receiver system (Figure 2 etc.), in which a feedback circuitry (Figure 2, from DSP 34 -> Receiver Control Processor 36 -> VAPDP/VAPDN 16/18) provide outputs of the ADC (32) to an algorithmic logic circuitry (DSP/Control Processor 34/36 in Figure 2; and Figure 5), the algorithmic logic circuitry ([0128]-[0129] etc. “in which each function or some combinations of certain of the functions are implemented as custom logic or circuitry” and “perform a set of operations, steps, methods, processes, algorithms, functions, techniques, etc. on digital and/or analog signals as described herein for the various embodiments”) being coupled to a variable voltage source (VAPDP 16 and VAPDN 18. [0065]-[0085]) that is coupled to at least one diode (Avalanche Photodiode, APD 12 or APD 14) of the photo diodes (Avalanche Photodiodes 12 and 14) to control the responsivity of the at least one diode (CMRR and sensitivity, [0035] and [0065]-[0085], Figures 5-6).
Samani et al discloses “the present disclosure relates to systems and methods for balancing a pair of Avalanche Photodiodes (APD) in a coherent receiver. … . Therefore, an APD balanced receiver (a pair of APD photodetectors) can enhance its sensitivity with a minimal power dissipation penalty. From another perspective, APD balanced receivers can achieve the same sensitivity as PIN balanced receivers with lower LO power, thus allowing more laser power to the transmitter to improve its output optical power” ([0035]), “To achieve optimum balanced photodetection, the setting of the bias voltages (or M) of a pair of APD must be controlled for optimum CMRR (DC and AC) and SNR performance” ([0036]), “The receiver control processor 36 will dynamically adjust the receiver's P-path 26 and N-path 28 transfer function difference by adjusting the TIA's common-mode AC response 42, AdjCM_AC_Response, to achieve the lowest common-mode output power POUT,CM possible” ([0059]), “This approach also improves interfering channel rejection in a colorless approach by optimizing the APD balanced receiver's CMRR. Without the CMRR optimization, an APD balanced receiver's CMRR can be very poor—process variation between a PIN-PD pair is already challenged to meet a typical CMRR spec of 20 dB because adding a difference in multiplication factor between an APD-PD pair with the same VAPD will lead to even poorer CMRR” ([0077]), and “Further implementing the gain control in balanced receivers (PD pair) in § 1.0-§ 1.4 can improve the noise performance of the APDs and minimize bandwidth variability and allow us to compensate any variations in the optical received power by adjusting the gain of each PD independently, achieving optimum balanced photodetection, i.e., optimized CMRR and SNR performance” ([0109]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Samani et al to the system/method of Palmer et al so that the common mode rejection ratio CMRR is optimized, and the sensitivity and performance of the corresponding photodiodes are enhanced.
2). With regard to claim 6, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 1 above. And the combination of Palmer et al and Samani et al further discloses wherein the optical receiver comprises a dual-polarization receiver (Palmer: Figure 5 is “a dual-polarization diversity coherent optical transceiver with an integrated optical loopback”).
3). With regard to claim 7, Palmer et al and Samani et al disclose all of the subject matter as applied to claims 1 and 6 above. And the combination of Palmer et al and Samani et al further discloses wherein a hybrid coupler (Palmer: Figure 5, OH 330X and 330Y) is configured to transform a local oscillator (LO) laser signal from 303/351) into an in-phase component and a quadrature component ([0073]) and wherein a hybrid coupler output is configured to generate an optical differential signal comprising at least the LO laser signal or a receiver input signal ([0076], “The phase diversity reception may be accomplished for example by embodying each of the OMs 330X, 330Y as a 90° hybrid, and differentially connecting the PDs 336 in the PD circuit 338 in pairs, as known in the art”).
4). With regard to claim 8, Palmer et al and Samani et al disclose all of the subject matter as applied to claims 1 and 6-7 above. And the combination of Palmer et al and Samani et al further discloses wherein the photodiodes are configured to generate a difference product of a frequency of the LO laser frequency minus input signal frequency ([0076], “The phase diversity reception may be accomplished for example by embodying each of the OMs 330X, 330Y as a 90° hybrid, and differentially connecting the PDs 336 in the PD circuit 338 in pairs, as known in the art”).
5). With regard to claim 9, Palmer et al and Samani et al disclose all of the subject matter as applied to claims 1 and 6-8 above. And the combination of Palmer et al and Samani et al further discloses the apparatus of claim 8, further comprising bias circuitry (Samani: VAPDP 16 and VAPDN 18) to generate tuning voltages as inputs for the photodiodes (Samani: [0065]-[0085], Figures 5-6).
6). With regard to claim 10, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 1 above. And the combination of Palmer et al and Samani et al further discloses the apparatus of claim 1, further comprising at least one optical switch (Palmer: Figure 3, switch 47; Figure 5, switches 342, 344 and 346), the at least one optical switch configured to switch signals from a transmission path of the apparatus to a receive path of the apparatus (Palmer: [0053]-[0058] and [0070]-[0072]).
7). With regard to claim 11, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 1 above. And the combination of Palmer et al and Samani et al further discloses wherein the apparatus is included in least one of a channel media, a fiber system (Palmer: “The optical Tx circuit 22 converts the one or more electrical Tx signals 25 into an output optical signal 21 that may be coupled into an optical fiber or otherwise transmitted to a destination over an optical communication link. The optical Rx circuit 32 receives an input optical signal 31, for example from a return optical fiber of the communication link”, [0051] and [0059]), a terrestrial free-space optics (FSO) system, a satellite-to-satellite FSO system or a combination thereof.
8). With regard to claim 12, Palmer et al discloses a method for calibrating an optical transceiver (Figures 2-5 and 8 etc.; [0004], [0049], [0083] and [0088], the loopback is used to calibrate and optimize the transmitter/receiver), the method comprising:
configuring optical switches (Figure 3, switch 47; Figure 5, switches 342, 344 and 346) to enable routing at least one output signal (Figure 3: the output from the EO 120 is coupled to input port of a first optical receiver 130 via the loopback optical circuit (LOC) 40. Figure 5: the outputs from X-MOD 320X and Y-MOD 320Y are coupled to an input port of a first optical receiver 330) of modulator circuitry (Figure 3, the TX circuit 120, [0056], “an optical modulator”. Figure 5, 320X and 320Y, “The dual optical Tx circuit 320 is embodied as an optical modulator circuit (OMC) formed of a first optical modulator 320X and a second optical modulator 320Y”) operably coupled to a first receive path (Figure 3: from 46 to 131. Figure 5 from 380 to 333) of a coherent optical transceiver (Figures 3,5 and 8; [0053]-[0058] and [0070]-[0072]);
configuring the input ([0050]-[0051] etc., the drive signals from data source 26 and amplifier 27; Figure 3: Tx El Signal; Figures 5 and 8, from data source 26) to at least one modulator to generate at least one first stimulus signal (the outputs from EO 120, or 320X and 320Y);
configuring a path from a first receiver analog-to-digital converter ([0051], “The data sink 36 performs digital signal processing on the electrical Rx signal or signals 35, after their conversion into the digital form by a suitable analog to digital converter (ADC, not shown), to extract transmitted data therefrom”. Figure 5, the output from the PD circuit 338 are sent “To processor 350”, and the processor 350 is a “digital signal processor”, [0080]; that is, an ADC is performed between the analog electrical circuitry 360 and the digital signal processor 350) to a control algorithm circuitry ([0053] and [0054] etc., the loopback mode is used to calibrate and optimize the transmitter/receiver, [0004], [0049], [0083] and [0088]. [0054], “The loopback controller 70 may be in communication with a digital signal processor 150, which may be an embodiment of processor 50 described above, and may be further configured to perform signal processing operations for transceiver testing when the optical transceiver is in the loopback mode of operation. Processor 150 may also communicate with the loopback controller 70 to switch between the loopback mode and a regular mode of transceiver operation.” That is, a path from ADC to a digital signal processor present, and control algorithm circuitry is associated with the digital signal processor).
But, Palmer et al does not expressly disclose: the method is for calibrating a common mode rejection ratio (CMRR) of the optical transceiver, and an adaptive algorithm circuitry is used, and adapting at least one bias setting of a photodiode associated with the first receive path in response to at least one first stimulus detected at the first receive path from an analog-to-digital converter to an adaptive algorithm circuitry; determining an optimum value of a photodiode associated with the first receiver through algorithm convergence; and determining whether to terminate or repeat the configuring and adapting operations based on whether all receive paths have been configured.
However, Palmer et al discloses “module settings that are found during factory calibration under laboratory conditions may not match optimal settings in the field. The need for module calibration in the field further increases with the rise of new transceiver platforms that separate the digital electrical data processing unit from an analogue electro-optic conversion engine. For example CFP2-ACO hot-pluggable optical transceiver modules may be hosted in the field on printed circuit boards (PCB) that are sourced separately from the pluggables. Consequently, the digital host unit and the analogue pluggable optical transceiver are calibrated in their respective factory independently, and their optimal settings may not match. However calibration of conventional transceiver modules typically requires on-site technical personal and thus may be too costly to perform in the field” ([0004]) and “[t]he integrated optical loopback enables a flexible and precise in-field calibration of the transceiver, for example during an automatic start-up sequence of a transponder incorporating the transceiver, which results in an overall improvement of the transponder performance. The in-field transceiver calibration, as enabled by the integrated optical loopback, avoids the propagation of uncertainty of calibration data in traditional transceivers, in which digital and analog interfaces, although hosted on a same PCB, are calibrated separately at their respective manufacturing facilities” ([0049]), “the ability to identify contributions of the Tx and Rx signal path to the distortion would facilitate transceiver calibration and optimization” ([0083]), “A transmission quality measure, such as for example the bit error ratio (BER), the Q-factor as a measure of the eye opening, the error vector magnitude (EVM), or any other suitable transmission quality measure, may be used to optimize the distortion parameter being measured”. That is, the loopback mode is used to calibrate and optimize the transmitter/receiver. And the photodiode is one component in the optical receiver; that is, “value of a photodiode” is one of the parameters needs to be “calibrated”/“optimized” or controlled. Therefore, for the control/calibration mechanism disclosed by Palmer et al it is obvious to one skilled in the art that the output from the digital signal processor (350 etc.) is used as a feedback to obtain an optimum value of a photodiode.
Samani et al discloses a coherent optical receiver system (Figure 2 etc.), in which a feedback circuitry (Figure 2, from DSP 34 -> Receiver Control Processor 36 -> VAPDP/VAPDN 16/18) provide outputs of the ADC (32) to an algorithmic logic circuitry (DSP/Control Processor 34/36; Figure 5), the algorithmic logic circuitry ([0128]-[0129] etc. “in which each function or some combinations of certain of the functions are implemented as custom logic or circuitry” and “perform a set of operations, steps, methods, processes, algorithms, functions, techniques, etc. on digital and/or analog signals as described herein for the various embodiments”) is coupled to a variable voltage source (VAPDP 16 and VAPDN 18. [0065]-[0085]).
And Samani et al teaches to adapt at least one bias setting (bias voltage, VAPD, [0065]-[0085]) of a photodiode associated (12 or 14) with the first receive path (from hybrid 24 ->26/28 - > photodiodes 12/14 -> TIA 30 -> ADC 32, as shown in Figure 2) in response to at least one first stimulus (Esig 20) detected at the first detect at the first receive path from an analog-to-digital converter (32) to an adaptive algorithm circuitry (DSP/Control Processor 34/36 in Figure 2; and Figures 5-6. [0128]-[0129] etc. “in which each function or some combinations of certain of the functions are implemented as custom logic or circuitry” and “perform a set of operations, steps, methods, processes, algorithms, functions, techniques, etc. on digital and/or analog signals as described herein for the various embodiments”; Figures 5-6 and [0065] describe a real-time control processes, the feedback is provided from DSP 34 to the control processor 36, and “If the output (POUT,CM) 40 meets a minimum threshold (step 59), the control process 50 returns to step 52, e.g., can continually run.” That is, a real-time controlling is performed, Samani’s control circuitry is an adaptive algorithm circuitry); determining an optimum value of a photodiode associated with the first receiver through algorithm convergence (e.g., Figure 5, the flowing: 53->55->56->58->59); and determining whether to terminate or repeat the configuring and adapting operations based on whether all receive paths have been configured (Figure 5 and Figure 6; [0065]-[0085]).
Samani et al discloses “the present disclosure relates to systems and methods for balancing a pair of Avalanche Photodiodes (APD) in a coherent receiver. … . Therefore, an APD balanced receiver (a pair of APD photodetectors) can enhance its sensitivity with a minimal power dissipation penalty. From another perspective, APD balanced receivers can achieve the same sensitivity as PIN balanced receivers with lower LO power, thus allowing more laser power to the transmitter to improve its output optical power” ([0035]), “To achieve optimum balanced photodetection, the setting of the bias voltages (or M) of a pair of APD must be controlled for optimum CMRR (DC and AC) and SNR performance” ([0036]), “The receiver control processor 36 will dynamically adjust the receiver's P-path 26 and N-path 28 transfer function difference by adjusting the TIA's common-mode AC response 42, AdjCM_AC_Response, to achieve the lowest common-mode output power POUT,CM possible” ([0059]), “This approach also improves interfering channel rejection in a colorless approach by optimizing the APD balanced receiver's CMRR. Without the CMRR optimization, an APD balanced receiver's CMRR can be very poor—process variation between a PIN-PD pair is already challenged to meet a typical CMRR spec of 20 dB because adding a difference in multiplication factor between an APD-PD pair with the same VAPD will lead to even poorer CMRR” ([0077]), and “Further implementing the gain control in balanced receivers (PD pair) in § 1.0-§ 1.4 can improve the noise performance of the APDs and minimize bandwidth variability and allow us to compensate any variations in the optical received power by adjusting the gain of each PD independently, achieving optimum balanced photodetection, i.e., optimized CMRR and SNR performance” ([0109]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Samani et al to the system/method of Palmer et al so that the common mode rejection ratio CMRR is optimized, and the sensitivity and performance of the receiver are enhanced.
9). With regard to claim 13, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 12 above. And the combination of Palmer et al and Samani et al further discloses wherein configuring the optical switches comprises configuring a subset of the optical switches to be calibrated and refraining from configuring optical switches that are not to be calibrated (Palmer: e.g., the subset switches 342 (top for X), 344 (for 341x) and 346 (for Y’) are used for X channe/path calibration (341x), and the subset switches 342 (second switch from the top for Y), 344 (for 341Y) and 346 (for X’) are used for Y path/channel calibration, [0070]).
10). With regard to claim 14, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 12 above. And the combination of Palmer et al and Samani et al further discloses wherein providing the input stimulus comprises providing inputs from a signal generator (Palmer: [0050]-[0051] etc., the data source 26 and amplifier 27 of Figure 2; Figure 3: Tx El Signal; Figures 5 and 8, from data source 26).
11). With regard to claim 16, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 12 above. And the combination of Palmer et al and Samani et al further discloses wherein the method is applied to at least one of a channel media, a fiber system (Palmer: “The optical Tx circuit 22 converts the one or more electrical Tx signals 25 into an output optical signal 21 that may be coupled into an optical fiber or otherwise transmitted to a destination over an optical communication link. The optical Rx circuit 32 receives an input optical signal 31, for example from a return optical fiber of the communication link”, [0051] and [0059]), a terrestrial free-space optics (FSO) system, a satellite-to-satellite FSO system or a combination thereof.
12). With regard to claim 17, Palmer et al discloses an integrated circuit (Abstract etc. “A photonic integrated circuit”) configured to perform operations comprising:
configuring optical switches (Figure 3, switch 47; Figure 5, switches 342, 344 and 346) to enable routing at least one output signal (Figure 3: the output from the EO 120 is coupled to input port of a first optical receiver 130 via the loopback optical circuit (LOC) 40. Figure 5: the outputs from X-MOD 320X and Y-MOD 320Y are coupled to an input port of a first optical receiver 330) of modulator circuitry (Figure 3, the TX circuit 120, [0056], “an optical modulator”. Figure 5, 320X and 320Y, “The dual optical Tx circuit 320 is embodied as an optical modulator circuit (OMC) formed of a first optical modulator 320X and a second optical modulator 320Y”) operably coupled to a first receive path (Figure 3: from 46 to 131. Figure 5 from 380 to 333) of a coherent optical transceiver (Figures 3,5 and 8; [0053]-[0058] and [0070]-[0072]);
configuring the input ([0050]-[0051] etc., the drive signals from data source 26 and amplifier 27; Figure 3: Tx El Signal; Figures 5 and 8, from data source 26) to at least one modulator to generate at least one first stimulus signal (the outputs from EO 120, or 320X and 320Y);
configuring a path from a first receiver analog-to-digital converter ([0051], “The data sink 36 performs digital signal processing on the electrical Rx signal or signals 35, after their conversion into the digital form by a suitable analog to digital converter (ADC, not shown), to extract transmitted data therefrom”. Figure 5, the output from the PD circuit 338 are sent “To processor 350”, and the processor 350 is a “digital signal processor”, [0080]; that is, an ADC is performed between the analog electrical circuitry 360 and the digital signal processor 350) to an adaptive algorithm circuitry ([0053] and [0054] etc., the loopback mode is used to calibrate and optimize the transmitter/receiver, [0004], [0049], [0083] and [0088]. [0054], “The loopback controller 70 may be in communication with a digital signal processor 150, which may be an embodiment of processor 50 described above, and may be further configured to perform signal processing operations for transceiver testing when the optical transceiver is in the loopback mode of operation. Processor 150 may also communicate with the loopback controller 70 to switch between the loopback mode and a regular mode of transceiver operation.” That is, a path from ADC to a digital signal processor present, and control algorithm circuitry is associated with the digital signal processor).
But, Palmer et al does not expressly disclose: an adaptive algorithm circuitry is used, and adapting at least one bias setting of a photodiode associated with the first receive path in response to at least one first stimulus detected at the first receiver analog-to-digital converter to an adaptive algorithm circuitry; determines an optimum value of a photodiode associated with the first receive path through algorithm convergence; and determining whether to terminate or repeat the configuring and adapting operations based on whether all receive paths have been configured.
However, Palmer et al discloses “module settings that are found during factory calibration under laboratory conditions may not match optimal settings in the field. The need for module calibration in the field further increases with the rise of new transceiver platforms that separate the digital electrical data processing unit from an analogue electro-optic conversion engine. For example CFP2-ACO hot-pluggable optical transceiver modules may be hosted in the field on printed circuit boards (PCB) that are sourced separately from the pluggables. Consequently, the digital host unit and the analogue pluggable optical transceiver are calibrated in their respective factory independently, and their optimal settings may not match. However calibration of conventional transceiver modules typically requires on-site technical personal and thus may be too costly to perform in the field” ([0004]) and “[t]he integrated optical loopback enables a flexible and precise in-field calibration of the transceiver, for example during an automatic start-up sequence of a transponder incorporating the transceiver, which results in an overall improvement of the transponder performance. The in-field transceiver calibration, as enabled by the integrated optical loopback, avoids the propagation of uncertainty of calibration data in traditional transceivers, in which digital and analog interfaces, although hosted on a same PCB, are calibrated separately at their respective manufacturing facilities” ([0049]), “the ability to identify contributions of the Tx and Rx signal path to the distortion would facilitate transceiver calibration and optimization” ([0083]), “A transmission quality measure, such as for example the bit error ratio (BER), the Q-factor as a measure of the eye opening, the error vector magnitude (EVM), or any other suitable transmission quality measure, may be used to optimize the distortion parameter being measured”. That is, the loopback mode is used to calibrate and optimize the transmitter/receiver. And the photodiode is one component in the optical receiver; that is, “value of a photodiode” is one of the parameters needs to be “calibrated”/“optimized” or controlled. Therefore, for the control/calibration mechanism disclosed by Palmer et al it is obvious to one skilled in the art that the output from the digital signal processor (350 etc.) is used as a feedback to obtain an optimum value of a photodiode.
Samani et al discloses a coherent optical receiver system (Figure 2 etc.), in which a feedback circuitry (Figure 2, from DSP 34 -> Receiver Control Processor 36 -> VAPDP/VAPDN 16/18) provide outputs of the ADC (32) to an algorithmic logic circuitry (DSP/Control Processor 34/36; Figure 5), the algorithmic logic circuitry ([0128]-[0129] etc. “in which each function or some combinations of certain of the functions are implemented as custom logic or circuitry” and “perform a set of operations, steps, methods, processes, algorithms, functions, techniques, etc. on digital and/or analog signals as described herein for the various embodiments”) is coupled to a variable voltage source (VAPDP 16 and VAPDN 18. [0065]-[0085]).
And Samani et al teaches to adapt at least one bias setting (bias voltage, VAPD, [0065]-[0085]) of a photodiode associated (12 or 14) with the first receive path (from hybrid 24 ->26/28 - > photodiodes 12/14 -> TIA 30 -> ADC 32, as shown in Figure 2) in response to at least one first stimulus (Esig 20) detected at the first receiver analog-to-digital converter (32) to an adaptive algorithm circuitry (DSP/Control Processor 34/36 in Figure 2; and Figures 5-6. [0128]-[0129] etc. “in which each function or some combinations of certain of the functions are implemented as custom logic or circuitry” and “perform a set of operations, steps, methods, processes, algorithms, functions, techniques, etc. on digital and/or analog signals as described herein for the various embodiments”; Figures 5-6 and [0065] describe a real-time control processes, the feedback is provided from DSP 34 to the control processor 36, and “If the output (POUT,CM) 40 meets a minimum threshold (step 59), the control process 50 returns to step 52, e.g., can continually run.” That is, a real-time controlling is performed, Samani’s control circuitry is an adaptive algorithm circuitry); determines an optimum value of a photodiode associated with the first receive path through algorithm convergence (e.g., Figure 5, the flowing: 53->55->56->58->59); and determining whether to terminate or repeat the configuring and adapting operations based on whether all receive paths have been configured (Figure 5 and Figure 6; [0065]-[0085]).
Samani et al discloses “the present disclosure relates to systems and methods for balancing a pair of Avalanche Photodiodes (APD) in a coherent receiver. … . Therefore, an APD balanced receiver (a pair of APD photodetectors) can enhance its sensitivity with a minimal power dissipation penalty. From another perspective, APD balanced receivers can achieve the same sensitivity as PIN balanced receivers with lower LO power, thus allowing more laser power to the transmitter to improve its output optical power” ([0035]), “To achieve optimum balanced photodetection, the setting of the bias voltages (or M) of a pair of APD must be controlled for optimum CMRR (DC and AC) and SNR performance” ([0036]), “The receiver control processor 36 will dynamically adjust the receiver's P-path 26 and N-path 28 transfer function difference by adjusting the TIA's common-mode AC response 42, AdjCM_AC_Response, to achieve the lowest common-mode output power POUT,CM possible” ([0059]), “This approach also improves interfering channel rejection in a colorless approach by optimizing the APD balanced receiver's CMRR. Without the CMRR optimization, an APD balanced receiver's CMRR can be very poor—process variation between a PIN-PD pair is already challenged to meet a typical CMRR spec of 20 dB because adding a difference in multiplication factor between an APD-PD pair with the same VAPD will lead to even poorer CMRR” ([0077]), and “Further implementing the gain control in balanced receivers (PD pair) in § 1.0-§ 1.4 can improve the noise performance of the APDs and minimize bandwidth variability and allow us to compensate any variations in the optical received power by adjusting the gain of each PD independently, achieving optimum balanced photodetection, i.e., optimized CMRR and SNR performance” ([0109]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Samani et al to the system/method of Palmer et al so that a common mode rejection ratio CMRR is optimized, and the sensitivity and performance of the receiver are enhanced.
13). With regard to claim 18, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 17 above. And the combination of Palmer et al and Samani et al further discloses wherein configuring the optical switches comprises configuring a subset of the optical switches to be calibrated and refraining from configuring optical switches that are not to be calibrated (Palmer: e.g., the subset switches 342 (top for X), 344 (for 341x) and 346 (for Y’) are used for X channe/path calibration (341x), and the subset switches 342 (second switch from the top for Y), 344 (for 341Y) and 346 (for X’) are used for Y path/channel calibration, [0070]).
14). With regard to claim 19, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 17 above. And the combination of Palmer et al and Samani et al further discloses wherein providing the input stimulus comprises providing inputs from one of a signal generator (Palmer: [0050]-[0051] etc., the data source 26 and amplifier 27 of Figure 2; Figure 3: Tx El Signal; Figures 5 and 8, from data source 26) and a look up table.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer et al and Samani et al as applied to claim 1 above, and further in view of Lowery et al (US 2014/0286642) and Zhu et al (MY 210251 A).
1). With regard to claim 3, Palmer et al and Samani et al disclose all of the subject matter as applied to claim 1 above. The combination of Palmer et al and Samani et al discloses that the algorithmic logic circuitry is an adaptive algorithm circuitry (Samani: Figures 5-6. [0128]-[0129] etc. “in which each function or some combinations of certain of the functions are implemented as custom logic or circuitry” and “perform a set of operations, steps, methods, processes, algorithms, functions, techniques, etc. on digital and/or analog signals as described herein for the various embodiments”; Figures 5-6 and [0065] describe a real-time control processes, the feedback is provided from DSP 34 to the control processor 36, and “If the output (POUT,CM) 40 meets a minimum threshold (step 59), the control process 50 returns to step 52, e.g., can continually run.” That is, a real-time controlling is performed, Samani’s control logic circuitry is an adaptive algorithm circuitry). But, Palmer et al and Samani et al do not expressly disclose wherein the algorithmic logic circuitry is configured to implement an adaptive filter algorithm.
However, an adaptive filter algorithm is well known in the art for controlling and optimization etc. E.g., Lowery et al discloses a coherent receiver (Figure 2 etc.), and the adaptive filter is used for improving received signal quality ([0017], [0052], [0083] and [0086] etc.; “The parameters of the filtering operation are advantageously adaptive, to enable on-line maximisation of compensated signal quality”) and receiver sensitivity ([0003]). Another prior art, Zhu et al, also discloses a feedback mechanism for a coherent receiver (Figures 4-5), and an adaptive filter algorithm is used for the feedback controlling (page 12 lines 28-32; “In the actual adjustment, the adjustment amount, that is, the adjustment step length dR, increases or decreases one for each adjustment. The dR can be a fixed value or a self-adaptive algorithm, that is, the step length is changed as the adjustment progresses. This step length-related algorithm is also a conventional algorithm”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply an adaptive filter algorithm as taught by Lowery et al and Zhu e al to the system/method of Palmer et al and Samani et al so that the CMRR and responsivity of the receiver can be controlled/adjusted in real-time, and the system can provide a robust performance in time-varying optical signals and/or environment.
2). With regard to claim 5, Palmer et al and Samani et al and Lowery et al and Zhu e al disclose all of the subject matter as applied to claims 1 and 3 above. And the combination of Palmer et al and Samani et al and Lowery et al and Zhu e al further discloses the apparatus of claim 3, further comprising Fast-Fourier Transform (FFT) circuitry configured to provided transformed outputs of the ADC to the algorithmic logic circuitry (Lowery: FFT is performed for the outputs of the ADCs 208/210, [0062] and [0069]. That is, the combination of Palmer et al and Samani et al and Lowery et al and Zhu e al further that a Fast-Fourier Transform (FFT) circuitry provides transformed outputs of the ADC to the algorithmic logic circuitry).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Palmer et al and Samani et al and Lowery et al and Zhu et al as applied to claims 1 and 3 above, and further in view of Kikuchi (US 2013/0108276).
Palmer et al and Samani et al and Lowery et al and Zhu et al disclose all of the subject matter as applied to claims 1-3 above. But, Palmer et al and Samani et al and Lowery et al and Zhu et al do not disclose wherein the adaptive filter algorithm comprises one of a least means squares (LMS) algorithm, a Kalman algorithm, or a minimum mean-squared error algorithm.
However, the LMS algorithm, a Kalman algorithm, and/or a minimum mean-squared error algorithm are just a few specific types of the adaptive filter algorithm. Another prior art, Kikuchi discloses to use an adaptive filter algorithm to improve the signal quality etc. ([0123], “the detection accuracy and receiving sensitivity can in this way be improved”), and as shown in Figure 13 etc., “Compensation algorithms and structures identical to the adaptive digital filter utilized in digital communication in the related art can also be utilized in this way in the adaptive equalizing circuit 342 and its adaptive compensation unit (compensation quantity calculation circuit 344). The compensation quantity calculation circuit 344 can for example calculate the correction quantity for the tap coefficient from the error signal by utilizing an algorithm such as the least mean squares (LMS) method. Methods such as decision feedback or blind equalization may be utilized as needed. Instead of minimizing the error signal, optimizing processes may be utilized that maximize the eye opening, or that minimize the clock frequency component. Signal degradation where these type of adaptive equalizing circuits can be used for compensation include polarization wave mode dispersion and wavelength dispersion, intersymbol interference (ISI) in transceivers and signal point position deviations, etc.” ([0125]).
It is commonly known that LMS has the advantage of simplicity, ease of implementation and robustness etc. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a least means squares (LMS) algorithm as commonly used and taught by Kikuchi to the system/method of Palmer et al and Samani et al and Lowery et al and Zhu e al so that the responsivity and CMRR can be conveniently controlled, and system can be more robust.
Claims 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Palmer et al and Samani et al as applied to claims 12 and 17 above, and further in view of Yoshida et al (US 2013/0136451) and Glaab et al (US 5,257,124) and Sugimoto et al (US 2021/0167863).
Palmer et al and Samani et al disclose all of the subject matter as applied to claims 12 and 17 above. But, Palmer et al and Samani et al do not expressly disclose where the algorithmic convergence solves for a minimization of the second harmonic in response to receiving a substantially one-hundred percent amplitude modulated tonally modulated signal.
Regarding the substantially one-hundred percent amplitude modulated tonally modulated signal, Palmer et al discloses that different modulation formats can be used for the signal transmission ([0004], [0070], [0090] and [0107]). Yoshida et al discloses an optical communication system with coherent receiver (Figures 1, 13 and 18 etc.), and a CSRZ (Carrier Suppressed Return to Zero) or CSRZ-QPSK can be used as the modulation format (Figures 15, 16 and 21 etc., [0103], [0111]-[0117] and [0123]); as shown in Figures 15-17 and 21-24, the CSRZ and CSRZ-QPSK signals are types of “substantially one-hundred percent amplitude modulated tonally modulated signal”. Since Palmer et al discloses that different types of modulations can be used for signal transmission, the CSRZ and CSRZ-QPSK modulation formats also can be used in the system of Palmer et al and Samani et al.
Regarding minimizing the second harmonic, Palmer et al and Samani et al use balanced photodetector to demodulate the received signals. It is a fundamental property or textbook knowledge that the balanced detection subtracts the photocurrents from two photodiodes and effectively cancels out common-mode noise and even-order harmonics including the second harmonic, while amplifying the desire differential signal. E.g., Glaab et al discloses that with the balanced photodiode (50 and 52 in Figure 3), “even order harmonics are cancelled and the power of the desired information is doubled for output to an RF output terminal 60” (column 4 lines 30-32), “This provides a 3 dB increase in the signal level of the RF signal to be recovered, while canceling the troublesome second order harmonic distortion components” (column 4 lines 63-66), and “A dual-detector balanced optical diode pair is advantageously used to simplify the recovery of an information signal while canceling even order harmonic distortions.” (column 5 lines 14-17). Another prior art, Sugimoto et al, discloses a coherent receiver (Figures 1, 6 and 9 etc., [0017]), and a feedback control ([0034]) is used to reduce the total harmonic distortion ([0041]-[0042], and Figures 4-5).
The purpose of the feedback control mechanism of Palmer et al and Samani et al is to enhance/optimize the CMRR (common-mode rejection ratio); since the CMRR is directly related to the second harmonic, when the second harmonic is minimized, the CMRR is increased/optimized. Therefore, it is obvious to one skilled in the art that the measurement of the second harmonic can be used as a criterion to judge whether a desired/optimum CMRR is reached, or whether a control processing is converged to a desired/optimum value.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to applying the teachings of Yoshida et al and Glaab et al and Sugimoto et al to the system/method of Palmer et al and Samani et al so that the feedback control algorithm can determine whether the photodiodes are balanced based on the power of the second harmonic, and while the second harmonic is maximally suppressed, the photodiodes are balanced, and the CMRR is enhanced.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
/LI LIU/Primary Examiner, Art Unit 2634 April 17, 2026
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