Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendments and Arguments
Applicant’s amendments and arguments filed on 08/18/2026 have been fully considered and are not found to place the application in a condition for allowance.
Amendments to claim 1 overcome the rejections under 35 USC § 112.
In view of the amendment citing: a sixth transistor comprises “a control electrode that receives a reference gate signal different from the first initialization gate signal”, further search and or consideration of the prior art was performed. Accordingly, a prior art of record, Tsuge, is found to teach such a limitation and Kim is no longer relied upon in the rejection of the claims. Therefore, the arguments provided in view of Kim are not found persuasive.
Accordingly, the amendments are not found to place the application in a condition for allowance and the arguments are not found persuasive.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1, 10 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuge, US 2014/0022288 A1, hereinafter “Tsuge.
Regarding claim 1, Tsuge teaches a pixel of a display apparatus (fig. 2, ¶ 37) comprising: a light emitting element (D20); a first transistor (Q20) that applies a driving current to the light emitting element; a second transistor (Q22) that receives a writing gate signal and transmits a data voltage using a data line (line 20); a first capacitor (C21) including: a first end electrically connected to a control electrode (Tp1) of the first transistor; and a second end electrically connected to an output electrode (Tp2) of the second transistor; and a second capacitor (C22) including: a first end electrically connected to the output electrode (Tp2) of the second transistor; and a second end electrically connected to an output electrode (Tp3) of the first transistor; a fourth transistor (Q23) that applies a first initialization voltage (Vint) to the second end of the second capacitor in response to a second initialization gate signal (CNT23, also see fig. 3), wherein the fourth transistor includes: an input electrode receiving the first initialization voltage from a first initialization voltage line connected to a first terminal, and an output electrode directly connected to a first electrode of the light emitting element (see fig. 2); a fifth transistor (Q24) that applies a second initialization voltage (Vref at Tp2, see fig. 4) to the second end of the first capacitor and the first end of the second capacitor in response to a first initialization gate signal (CNT24) different from the writing gate signal (CNT24 is different from CNT22); and a sixth transistor (Q21) comprising: a control electrode that receives a reference gate signal different from the first initialization gate signal (CNT21 different from CNT24); an input electrode that receives a reference voltage different from the first initialization voltage (Vref is different from Vint, ¶ 54); and an output electrode electrically connected to the control electrode of the first transistor (Q21 connection to Tp1), wherein the fifth transistor is different from the second transistor (see fig. 2), and wherein the fifth transistor includes: an input electrode receiving the second initialization voltage from a second initialization voltage line connected to a second terminal different from the first terminal, wherein the second initialization voltage line is different from the first initialization voltage line and the data line; and an output electrode directly connected to both of the second end of the first capacitor and the first end of the second capacitor (see configuration of Q24).
Regarding claim 10, Tsuge teaches the fourth transistor including: a control electrode that receives the second initialization gate signal (fig. 2, Q23 receiving signals from CNT23); and the fifth transistor including: a control electrode that receives the first initialization gate signal (CNT24); and the output electrode electrically connected to the output electrode of the second transistor (see fig. 2).
Regarding claim 24, Tsuge teaches the fourth transistor including the output electrode directly connected to the second end of the second capacitor (fig. 2, Q23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 10 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong, US 2017/0301289 A1, hereinafter “Jeong”, in view of Tsuge.
Regarding claim 1, Jeong teaches a pixel of a display apparatus (fig. 3A, ¶ 86) comprising: a light emitting element (fig. 3A, OLED, ¶ 87); a first transistor that applies a driving current to the light emitting element (fig. 3A, M0, ¶ 89); a second transistor (fig. 3A, M4, ¶ 94) that receives a writing gate signal (fig. 3B, Scan[n] signal during T3, ¶ 98-99) and transmits a data voltage using a data line (fig. 3A, Dm, ¶ 89); a first capacitor (CST1) including: a first end electrically connected to a control electrode of the first transistor; and a second end electrically connected to an output electrode of the second transistor (fig. 3A, CST1); and a second capacitor (CST2) including: a first end electrically connected to the output electrode of the second transistor; and a second end electrically connected to an output electrode of the first transistor (fig. 3A, CST2); a fourth transistor (fig. 3A, M1) that applies a first initialization voltage (Vinit) to the second end of the second capacitor (see the “s” node) in response to a second initialization gate signal (EM2), wherein the fourth transistor includes: an input electrode receiving a first initialization voltage from a first initialization voltage line connected to a first terminal (¶ 90, see connection to Vinit), and an output electrode directly connected to a first electrode of the light emitting element (see fig. 3A, M1).
Jeong does not specifically teach a fifth transistor that applies a second initialization voltage to the second end of the first capacitor and the first end of the second capacitor in response to a first initialization gate signal different from the writing gate signal, wherein the fifth transistor is different from the second transistor, and wherein the fifth transistor includes: an input electrode receiving the second initialization voltage from a second initialization voltage line connected to a second terminal different from the first terminal, wherein the second initialization voltage line is different from the first initialization voltage line and the data line; and an output electrode directly connected to both of the second end of the first capacitor and the first end of the second capacitor.
Jeong, however, teaches that the second transistor (fig. 3A, M4) applies a second initialization voltage (fig. 3B, Vinit, ¶ 99) to the second end of the first capacitor and the first end of the second capacitor (see fig. 3A, application of Vinit to node C) in response to a first initialization gate signal different from the writing gate signal (see fig. 3B, wherein two different pulses, or signals, provided on the SCAN[n] line have different amplitudes and timings), and wherein the second transistor includes: an input electrode receiving the second initialization voltage from a second initialization voltage line connected to a second terminal (Vinit is received from the DATA line which functions as a second terminal) different from the first terminal, wherein the second initialization voltage line is different from the first initialization voltage line (M4 receives the second initialization voltage from the DATA line which is a different terminal than the Vinit line to which the M1 transistor is connected, see ¶ 99-101); and an output electrode directly connected to both of the second end of the first capacitor and the first end of the second capacitor (fig. 3A, see connection of M4 to node C).
Jeong does not specifically teach that the fifth transistor is different from the second transistor, and the second initialization voltage line is different from the data line.
Note that the second transistor M4 of Jeong performs the functions of both the second transistor and the fifth transistor as claimed. Specifically, as taught by Jeong in fig. 3B, M4 performs the initialization functions of the fifth transistor during T1 and performs data writing functions of the second transistor during T3.
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Jeong in order to split the tasks performed by M4 between two separate transistors and configure the fifth transistor as claimed. Accordingly, the new transistor would receive the initialization voltage directly from a separate voltage line at an input and provide the initialization voltage directly to the C node during the first period as taught by Jeong, while being controlled by a separate line which provides the signal only during the time when the initialization voltage is to be provided (see fig. 3B for such clearly distinct periods when Vinit and Vdata are provided according to the operation of the SCAN line). One would have been motivated to make such a modification to reduce the number of switching operations for M4 thus reducing strain on this transistor, while simplifying the signal provided on the DATA line by providing the initialization signal through the new transistor, thus simplifying the driving of the circuit while achieving the same result of initializing and data writing.
Jeong does not specifically teach a sixth transistor comprising: a control electrode that receives a reference gate signal different from the first initialization gate signal; an input electrode that receives a reference voltage different from the first initialization voltage; and an output electrode electrically connected to the control electrode of the first transistor.
Tsuge teaches a sixth transistor (fig. 2, Q21) comprising: a control electrode that receives a reference gate signal (CNT21) different from the first initialization gate signal (CNT21 is different from CNT23); an input electrode that receives a reference voltage different from the first initialization voltage (Vref, which is different from Vinit; ¶ 54) and an output electrode electrically connected to the control electrode of the first transistor (connection to Tp1).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Jeong and Tsuge to provide such a sixth transistor. According to such a modification, during the initialization period of Jeong, the gate of the driving transistor is provided the Vref voltage instead of the ELVDD. One would have been motivated to make such a combination since according to Tsuge in ¶ 67, incorporation of such a Vref voltage prevents the OLED from inadvertently emitting light during the initialization period, thus achieving a higher quality display device.
Regarding claim 2, Jeong teaches a third transistor including: a control electrode that receives a compensation gate signal; an input electrode electrically connected to an input electrode of the first transistor; and an output electrode electrically connected to the control electrode of the first transistor (fig. 3A, M3, ¶ 92).
Regarding claim 3, Jeong teaches the fourth transistor (fig. 3A, M1) including: a control electrode that receives the second initialization gate signal (EM2).
Jeong does not specifically teach the fifth transistor including: a control electrode that receives the first initialization gate signal; and an output electrode electrically connected to the output electrode of the second transistor.
Jeong, however, teaches a transistor including: a control electrode that receives a first initialization gate signal; an input electrode that receives a second initialization voltage (fig. 3A, M4, per ¶ 99 performs the task of such a fifth transistor wherein the scan[n] signal line provides the first initialization gate signal and the input electrode receives an initialization voltage Vinit). In other words, Jeong teaches in ¶ 99 that M4 transistor performs the task of providing an initialization voltage to the node between the two capacitors in addition to providing the data voltage.
As such, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Jeong in order to split the tasks performed by M4 between two separate transistors and configure the fifth transistor as claimed. Accordingly, the new transistor would receive the initialization voltage at an input and provide the initialization voltage to the C node during the first period as taught by Jeong. One would have been motivated to make such a modification in order to reduce the number of switching for M4 thus reducing strain on this transistor while simplifying the signal provided on the DATA line by providing the initialization signal through the new transistor, thus simplifying the driving of the circuit.
Regarding claim 4, Jeong teaches a seventh transistor (fig. 3A, M2) including: a control electrode that receives an emission signal (EM1); an input electrode that receives a first power voltage (ELVDD); and an output electrode electrically connected to the input electrode of the first transistor (see fig. 3A).
Regarding claim 5, Jeong teaches that the first to fourth and seventh transistors are N-type transistors (¶ 95).
Jeong does not specifically teach the fifth and sixth transistors as stated above.
Tsuge teaches that all the transistors including the sixth transistor (Q21) and the fifth transistor (Q24) are N-type transistors (¶ 39).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Jeong and Tsuge to set all the transistors to be the same type. Both references teach that all transistors of the pixel circuit are of the same type, which would lead to simpler and cheaper manufacturing of such a pixel circuit, motivating one of ordinary skill to make such a combination.
Regarding claim 10, Jeong teaches the fourth transistor (fig. 3A, M1) including: a control electrode that receives the second initialization gate signal (EM2).
Jeong does not specifically teach the fifth transistor including: a control electrode that receives the first initialization gate signal; and the output electrode electrically connected to the output electrode of the second transistor.
Jeong, however, teaches in ¶ 99 that M4 transistor performs the task of providing an initialization voltage to the node between the two capacitors in addition to providing the data voltage (fig. 3A, M4, per ¶ 99 performs the task of such a fifth transistor wherein the scan[n] signal line provides the first initialization gate signal and the input electrode receives an initialization voltage Vinit).
As such, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to modify the teachings of Jeong in order to split the tasks performed by M4 between two separate transistors and configure the fifth transistor as claimed. Accordingly, the new transistor would receive the initialization voltage at an input and provide the initialization voltage to the C node during the first period as taught by Jeong. One would have been motivated to make such a modification in order to reduce the number of switching for M4 thus reducing strain on this transistor while simplifying the signal provided on the DATA line by providing a dedicated initialization signal to the new transistor, thus simplifying the driving of the circuit.
Regarding claim 24, Jeong teaches the fourth transistor including the output electrode directly connected to the second end of the second capacitor (see fig. 3A, M1).
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jeong and Tsuge, as applied above, further in view of Kang et al., US 2022/0139318 A1, hereinafter “Kang”.
Regarding claim 6, Jeong and Tsuge do not teach that the first transistor includes the control electrode, an input electrode, the output electrode, and a second control electrode, and the second control electrode of the first transistor is electrically connected to the output electrode of the first transistor.
Kang, however, clearly teaches that the first transistor includes the control electrode (N1), an input electrode (N3), the output electrode (N2), and a second control electrode (N4), and the second control electrode of the first transistor is electrically connected to the output electrode of the first transistor (fig. 2, ¶ 96).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Jeong, Tsuge and Kang. Jeong teaches the first transistor and Kang further teaches in ¶ 96 the connection of the backgate of such a transistor to its output electrode. One would have been motivated to make such a combination since Kang clearly teaches in ¶ 96 that such a connection improves “the device performance of the driving transistor DRT of each subpixel SP (for example, a sub-threshold swing value SS, etc.)”.
Regarding claim 7, Jeong and Tsuge do not teach that the first transistor includes the control electrode, an input electrode, the output electrode, and a second control electrode, and a bias voltage is applied to the second control electrode of the first transistor.
Kang, however, clearly teaches that the first transistor includes the control electrode (N1), an input electrode (N3), the output electrode (N2), and a second control electrode (N4), and a bias voltage is applied to the second control electrode of the first transistor (fig. 2, ¶ 96; note that N2 carries a voltage during the light emission period which is considered to be the bias voltage).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Jeong, Tsuge and Kang. Jeong teaches the first transistor and Kang further teaches in ¶ 96 the connection of the backgate of such a transistor to its output electrode. One would have been motivated to make such a combination since Kang clearly teaches in ¶ 96 that such a connection improves “the device performance of the driving transistor DRT of each subpixel SP (for example, a sub-threshold swing value SS, etc.)”.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jeong and Tsuge, as applied above, further in view of Jeon et al., US 2017/0337875 A1, hereinafter “Jeon”.
Regarding claim 8, Jeong and Tsuge do not teach that the first transistor includes the control electrode, an input electrode, the output electrode, and a second control electrode, and the pixel further comprises: an eighth transistor including: a control electrode that receives a compensation gate signal; an input electrode that receives a bias voltage; and an output electrode electrically connected to the second control electrode of the first transistor; and a third capacitor including: a first end electrically connected to the second control electrode of the first transistor; and a second end electrically connected to the output electrode of the first transistor.
Jeon, however, teaches that the first transistor includes the control electrode (fig. 2, N1 of DT), an input electrode (fig. 2, DT electrode connected to VDD), the output electrode (N3), and a second control electrode (N2), and the pixel further comprises: an eighth transistor (ST3) including: a control electrode that receives a compensation gate signal (scan2); an input electrode that receives a bias voltage (connection to ground which is the bias voltage); and an output electrode electrically connected to the second control electrode of the first transistor (ST3 connection to N2); and a third capacitor (C2) including: a first end electrically connected to the second control electrode of the first transistor; and a second end electrically connected to the output electrode of the first transistor (fig. 2, see connection of C2 to N2 and N3).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Jeong, Tsuge and Jeon. The references teach pixel circuits including driving transistors. Jeon further teaches the claimed configuration. One would have been motivated to make such a combination since Jeon teaches that such a configuration allows the threshold voltage of the driving transistor to be held constant at all times (see ¶ 70), thus forming an improved pixel circuit and providing a display device exhibiting better uniformity.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEPEHR AZARI/Primary Examiner, Art Unit 2621
