DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Action is non-final and is in response to the claims filed November 4th, 2022. Claims 1-20 are pending, of which claims 1-20 are currently rejected.
Claim Objections
Claims 10-19 are objected to because of the following informalities:
Claim 10 recites on line 4 “under the control” should be “under control”
Claims 11-19 are objected to based on their dependence on claim 10
Claim 11 recites on line 2 “under the control” should be “under control”
Claims 12-19 are objected to based on their dependence on claim 11
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-9, and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “a preset rule” on line 2. It is unclear if this mention of “a preset rule” is the same as the preset rule of claim 1 or some other preset rule. Appropriate correction is required. For examination purposes “a preset rule” as recited in claim 7 will be construed to be the same preset rule of claim 1.
Claim 7 recites the limitation “output buffer” on line 3. It is unclear if this output buffer is the same output buffer as the output buffer of claim 1. Appropriate correction is required. For examination purposes “output buffer” of claim 7 will be construed to be the same output buffer of claim 1.
Claim 7 recites the limitation “the K-th reading operation” on line 4. There is lack of antecedent basis for this limitation. Appropriate correction is required.
Because claim 8 depends on claim 7, claim 8 is also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 9 recites the limitation “a next row” on line 4. It is unclear if this “a next row” is the same as the next row as claimed in claim 1. Appropriate correction is required. For examination purposes “a next row” of claim 9 will be construed to be the same next row of claim 1.
Claim 18 recites the limitation “the input buffer” on line 3. It is unclear if this is the same input buffer as claim 10 or a specific input buffer for each corresponding accumulator. Appropriate correction is required. For examination purposes, “the input buffer” of claim 18 will be construed to be same input buffer as recited in claim 10.
Because claim 19 depends on claim 18, claim 19 is also rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite.
Claim 20 recites the limitation “the target matrix” on line 13. There is lack of antecedent basis for this limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites transposing of a matrix.
Below are the limitations of claim 1 that recite an abstract idea under mathematical concepts or mental steps:
A data processing method, for transposing a target matrix, comprising (mathematical concepts):
S12, shifting elements in the target row along a first direction to acquire a shifted target row according to a preset offset (mathematical concepts).
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
S11, reading a row of the target matrix as a target row;
and writing each element in the shifted target row into a corresponding buffer respectively;
S13, reading a next row of the target row from the target matrix as a new target row, if the next row of the target row is not the last row of the target matrix and there is an available storage space in the row buffers; wherein steps S12~S13 are performed repeatedly; and
S14, reading corresponding elements from each row buffer according to a preset rule, and writing the elements read from each row buffer into an output buffer as a row, wherein step S14 is repeated until all elements in all row buffers are written into the output buffer.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There are insignificant extra-solution activities that must be made of note as shown below:
S11, reading a row of the target matrix as a target row;
and writing each element in the shifted target row into a corresponding buffer respectively;
S13, reading a next row of the target row from the target matrix as a new target row
S14, reading corresponding elements from each row buffer according to a preset rule,
and writing the elements read from each row buffer into an output buffer as a row
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 1 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “reading a row of the target matrix as a target row”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson, David A., and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, edited by Peter J Ashenden, Elsevier Science & Technology, 2007, hereinafter “Patterson”: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing each element in the shifted target row”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “reading a next row of the target row from the target matrix as a new target row”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “reading corresponding elements from each row buffer according to a preset rule”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing the elements read from each row buffer into an output buffer as a row”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 1 is not eligible.
Regarding claim 2, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 2 that recite an abstract idea under mathematical concepts or mental steps:
The data processing method according to claim 1, wherein the step of shifting elements in the target row along a first direction according to a preset offset comprises (mathematical concepts):
dividing the target row into a plurality of subvectors, and cyclically shifting elements in each subvector along the first direction according to the preset offset, wherein the number of the subvectors is L and L is an integer greater than or equal to one (mathematical concepts).
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no further additional elements beyond those recited in claim 1.
Claim 2 is not eligible.
Regarding claim 3, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 3 that recite an abstract idea under mathematical concepts or mental steps:
The data processing method according to claim 2, wherein the step of cyclically shifting elements in each subvector along the first direction comprises: cyclically shifting the elements in each subvector to the right (mathematical concepts).
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no further additional elements beyond those recited in claim 2.
Claim 3 is not eligible.
Regarding claim 4, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 4 that recite an abstract idea under mathematical concepts or mental steps:
The data processing method according to claim 2, wherein L=ceil(A/B), wherein ceil is a ceiling function, A is the number of columns of the target matrix, B is the number of rows of the row buffers (mathematical concepts).
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no further additional elements beyond those recited in claim 2.
Claim 4 is not eligible.
Regarding claim 5, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 5 that recite an abstract idea under mathematical concepts or mental steps:
The data processing method according to claim 1, wherein the preset offset is set according to the row number of the target row in the target matrix (mathematical concepts).
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, there are no further additional elements beyond those recited in claim 1.
Claim 5 is not eligible.
Regarding claim 6, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 6 that recite an abstract idea under mathematical concepts or mental steps:
The data processing method according to claim 2, wherein the step of writing each element in the shifted target row into a corresponding row buffer respectively comprises (mathematical concepts).
All limitations as indicated describe “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
Sequentially writing each element of each subvector in the shifted target row into a corresponding row buffer respectively.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There are insignificant extra-solution activities that must be made of note as shown below:
Sequentially writing each element of each subvector in the shifted target row into a corresponding row buffer respectively.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 6 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “sequentially writing each element of each subvector”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 6 is not eligible.
Regarding claim 7, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 7 that recite an abstract idea under mathematical concepts or mental steps:
For the K-th reading operation, determining a reading sequence (mental steps)
Wherein K is an integer greater than or equal to one (mathematical concepts)
All limitations as indicated describe “mental steps” or “mathematical concepts”. Determination of a reading sequence can be practically done in the human mind or with the aid of pen and paper.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
Corresponding to each row buffer and storage positions of the elements to be read from each row buffer according to the preset rule,
Reading corresponding elements from each row buffer according to the reading sequence and the storage positions,
And writing the elements read from each row buffer into the output buffer as a row
Reading corresponding elements from each row buffer according to the reading sequence and the storage positions,
And writing the elements read from each row buffer into the output buffer as a row.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There are insignificant extra-solution activities that must be made of note as shown below:
to be read from each row buffer according to the preset rule,
Reading corresponding elements from each row buffer according to the reading sequence and the storage positions,
And writing the elements read from each row buffer into the output buffer as a row.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 7 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “reading corresponding elements from each row buffer according to the reading sequence and the storage positions”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing the elements read from each row buffer into the output buffer as a row”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 7 is not eligible.
Regarding claim 8, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 8 that recite an abstract idea under mathematical concepts or mental steps:
If K=1, determining the reading sequence S-i (mental steps)
And determining a storage position in the i-th row buffer wherein an element to be read is stored according to ceil (A/B) times Si, (mental steps)
wherein ceil is a ceiling function, A is the number of columns of the target matrix, B is the number of rows of row buffers (mathematical concepts); and
by cyclically shifting the reading sequence corresponding to each row buffer for the (K-1)-th reading operation to the right by one position (mathematical concepts);
by shifting ceil (A/B) positions to the left from a storage position of an element read for the (K-1)-the reading operation (mathematical concepts).
All limitations as indicated describe “mental steps” or “mathematical concepts”. Determination of a reading sequence and storage positions can be practically done in the human mind or with the aid of pen and paper.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
corresponding to each row buffer according to the row number i of each row buffer,
If K>1 acquiring the reading sequence corresponding to each row buffer for the K-th reading operation
for the i-th row buffer, acquiring the storage position where the element to be read is stored for the K-th reading operation
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There are insignificant extra-solution activities that must be made of note as shown below:
If K>1 acquiring the reading sequence corresponding to each row buffer for the K-th reading operation
for the i-th row buffer, acquiring the storage position where the element to be read is stored for the K-th reading operation
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 8 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “acquiring the reading sequence”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “acquiring the storage position”, this action describes mere data gathering that is recited at a high level of generality. Per MPEP 2106.05(d)(II), the courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iv. Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 8 is not eligible
Regarding claim 9, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea.
Below are the limitations of claim 9 that recite an abstract idea under mathematical concepts or mental steps:
Wherein if the number of columns of the target row is greater than the number of rows of the row buffers, (mathematical concepts)
All limitations as indicated describe “mental steps” or “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
S15, reading a next row of the target row from the target matrix as a new target row,
and writing each element in the next target row into a corresponding row buffer respectively,
Wherein step S15 is repeated until the new target row is the last row of the target matrix or there is no available storage space in the row buffers; and
S16, reading corresponding elements from each row buffer according to the preset rule,
writing the elements read from each row buffer into a corresponding row of the output buffer,
wherein step S16 is repeated until all elements in all row buffers are written into the output buffer.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There are insignificant extra-solution activities that must be made of note as shown below:
S15, reading a next row of the target row from the target matrix as a new target row,
and writing each element in the next target row into a corresponding row buffer respectively
S16, reading corresponding elements from each row buffer according to the preset rule,
writing the elements read from each row buffer into a corresponding row of the output buffer.
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 9 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “reading a next row of the target row from the target matrix as a new target row”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing each element in the next target row into a corresponding row buffer respectively”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “reading corresponding elements from each row buffer according to the preset rule”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing the elements read from each row buffer into a corresponding row of the output buffer”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 9 is not eligible.
Regarding claim 20, at Step 1, the claim is directed to a statutory category of invention (method).
At Step 2A, Prong 1, Examiner notes that the claim recites an abstract idea. Claim language recites dividing of an original matrix into submatrices, submatrices being diagonal or non-diagonal, and transposition of these submatrices.
Below are the limitations of claim 20 that recite an abstract idea under mathematical concepts or mental steps:
A data processing method, for transposing an original matrix, comprising (mathematical concepts):
Dividing the original matrix into a plurality of submatrices, wherein the submatrices comprise diagonal submatrices and non-diagonal submatrices (mathematical concepts);
Transposing each diagonal submatrix in the original matrix to acquire transposed diagonal submatrices (mathematical concepts),
Transposing each non-diagonal submatrix in the original matrix to acquire transposed non-diagonal submatrices (mathematical concepts),
Wherein the second positions are symmetrical to the original positions of the non-diagonal submatrices relative to a main diagonal of the original matrix (mathematical concepts);
Wherein two non-diagonal submatrices symmetrical to the main diagonal are transposed in parallel (mathematical concepts);
Wherein the step of transposing each submatrix in the original matrix comprises:
S12, shifting elements in the target row along a first direction to acquire a shifted target row according to a preset offset (mathematical concepts),
All limitations as indicated describe “mental steps” or “mathematical concepts”.
At Step 2A Prong 2, additional elements not reciting mathematical equations and mathematical calculations thereof include:
And writing the transposed diagonal submatrices into first positions of a target buffer,
Wherein the first positions correspond to original positions of the diagonal submatrices;
And writing the transposed non-diagonal submatrices into second positions of the target buffer,
S11 reading a row of the target matrix as a target row;
And writing each element in the shifted target row into a corresponding row buffer respectively;
S13, reading a next row the target row from the target matrix as a new target row,
If the next row of the target row is not the last row of the target matrix and there is an available storage space in the row buffers, wherein steps S12~S13 are performed repeatedly; and
S14, reading corresponding elements from each row buffer according to a preset rule,
And writing the elements read from each row buffer into an output buffer as a row, wherein step S14 is repeated until all elements in all row buffers are written into the output buffer.
These additional elements are recited at a high level of generality to merely generally link the abstract idea to a computer system, such that the claim merely recites “apply it” in a computer. Furthermore, the limitations merely generically recite circuits that flow from the functions performed. For these reasons, the additional elements, whether or alone or in combination, do not integrate the abstract idea into a practical application.
There are insignificant extra-solution activities that must be made of note as shown below:
And writing the transposed diagonal submatrices into first positions of a target buffer,
And writing the transposed non-diagonal submatrices into second positions of the target buffer,
S11 reading a row of the target matrix as a target row;
And writing each element in the shifted target row
S13, reading a next row the target row from the target matrix as a new target row,
And writing the elements read from each row buffer into an output buffer as a row
At Step 2B, the additional elements do not, either alone or in combination, amount to significantly more than the recited judicial exception. As stated in at Step 2A Prong 2, the claim does no more than generally link the abstract idea to a computer system. For these reasons, claim 9 does not amount to significantly more than the abstract idea.
In regards to the insignificant extra-solution activity found in this limitation “writing the transposed diagonal submatrices into first positions of a target buffer”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing the transposed non-diagonal submatrices into second positions of a target buffer”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “reading a row of the target matrix as a target row”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing each element in the shifted target row”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “reading a next row the target row from the target matrix as a new target row”, this action “reading” merely describes data inputting that is recited at a high level of generality. As is known in the art, inputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
In regards to the insignificant extra-solution activity found in this limitation “writing the elements read from each row buffer into an output buffer as a row”, this action “writing” merely describes data outputting that is recited at a high level of generality. As is known in the art, outputting of data is a basic function of underlying hardware in any computer (Patterson: Pg. 15 Section 1.3 Lines 2-4). This limitation therefore remains insignificant extra-solution activity even upon reconsideration. Thus, this limitation does not amount to significantly more.
Claim 20 is not eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by S. Ma et al. ("MT-DMA: A DMA Controller Supporting Efficient Matrix Transposition for Digital Signal Processing", 2018) (hereinafter “Ma”).
Regarding claim 1, Ma teaches:
A data processing method, for transposing a target matrix (Abstract - device used for matrix transposition), comprising:
S11, reading a row of the target matrix as a target row (Pg. 5810 Col. 2 Section III A and Pg. 5811 Col. 1 reading of a row of the target matrix; Pg. 5812 Col. 1 Steps 1 and 2 - writing row by row including target row until all rows are written in MBTB which are buffers Pg. 5811 Col. 2 Section C);
S12, shifting elements in the target row along a first direction to acquire a shifted target row according to a preset offset, and writing each element in the shifted target row into a corresponding row buffer respectively (Pg. 5812 Col. 1 Steps 1 and 2 row shift write strategy shifts rows in a direction i.e., first direction writing to MBTB which are the respective row buffers; shifting and offset further described in Pg. 5813 Col. 1 Section F Second paragraph);
S13, reading a next row of the target row from the target matrix as a new target row, if the next row of the target row is not the last row of the target matrix and there is an available storage space in the row buffers; wherein steps S12~S13 are performed repeatedly (row shift write strategy used for writing of rows into corresponding buffers (described in Step 2); Fig. 5; Pg. 5812 Col. 2 first paragraph once all rows are written, switch to reading is done, once all Columns are read from MBTB, transposition is complete); and
S14, reading corresponding elements from each row buffer according to a preset rule, and writing the elements read from each row buffer into an output buffer as a row, wherein step S14 is repeated until all elements in all row buffers are written into the output buffer (Pg. 5812 Col. 1 Step 2 and paragraph after, reading out column wise according to a reading scheme i.e., preset rule in order to read distributed elements from MBTBs, further described in Section D ping pong scheme, and after which the read elements are sent into a destination memory i.e., output buffer).
Regarding claim 7, Ma teaches reading out column wise according to a reading scheme i.e., preset rule in order to read distributed elements from MBTBs (Pg. 5812 Col. 1 Step 2 and paragraph after), further described in Section D as ping pong scheme, and after which the read elements are sent into a destination memory i.e., output buffer. Therefore, Ma teaches claim 7.
Regarding claim 9, Ma teaches a row shift write strategy used for writing of rows into corresponding buffers (described in Step 2) (Pg. 5812), once all rows are read, switch to writing (Fig. 5; Pg. 5812 Col. 2 first paragraph). Once all Columns are written from MBTB, transposition is complete (Pg. 5812 Col. 1 Step 2 and paragraph after), reading out column wise according to a reading scheme i.e., preset rule in order to read distributed elements from MBTBs, further described in Section D ping pong scheme, and after which the read elements are sent into a destination memory i.e., output buffer (Pg. 5813 Col. 1 Section F second paragraph 16 > 8 # of cols greater than # of rows).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Gunnam et al. (US 2011/0119553 A1) (hereinafter “Gunnam”).
Regarding claim 2, Ma teaches dividing into subvectors i.e., every two adjacent elements for locating to different MBTBs i.e., row buffers (preset offset being two and L being greater than one since there are 8 or 16 elements based on the example, having every two elements being allocated to various MBTBs for matrix transposition would yield 4 or more subvectors) (Pg. 5813 Col. 1 Section F second paragraph).
Ma does not explicitly teach cyclically shifting the subvectors.
However, Gunnam teaches cyclically shifting the subvectors (Gunnam: ¶ 0051 - 0052).
It would be obvious before the effective filing date of the claimed invention to combine the cyclic shifting as taught by Gunnam with the data processing method as taught by Ma because both teachings are directed towards matrix transposition. One with ordinary skill in the art would be motivated to combine the teachings because doing so could reduce sequential bit errors by having separate processing for each of the subwords i.e., subvectors (Gunnam: ¶ 0046).
Therefore, Ma in view of Gunnam teaches:
The data processing method according to claim 1, wherein the step of shifting elements in the target row along a first direction according to a preset offset comprises:
dividing the target row into a plurality of subvectors, and cyclically shifting elements in each subvector along the first direction according to the preset offset, wherein the number of the subvectors is L and L is an integer greater than or equal to one.
Regarding claim 3, Ma in view of Gunnam further teaches:
The data processing method according to claim 2, wherein the step of cyclically shifting elements in each subvector along the first direction comprises: cyclically shifting the elements in each subvector to the right (Gunnam: ¶ 0051 - 0052).
The motivation to combine with respect to claim 2 applies equally to claim 3.
Regarding claim 4, Ma in view of Gunnam further teaches:
The data processing method according to claim 2, wherein L= ceil (A/B), wherein ceil is a ceiling function, A is the number of columns of the target matrix, B is the number of rows of the row buffers (Ma: Pg. 5813 Col. 1 Section F third paragraph A=8 B=4, ceil(8/4) which would be 2, and since offset is 4, this would result in 2 subvectors being collected from the column, meeting the condition for L=2).
Regarding claim 6, Ma in view of Gunnam further teaches:
The data processing method according to claim 2, wherein the step of writing each element in the shifted target row into a corresponding row buffer respectively comprises:
sequentially writing each element of each subvector in the shifted target row into a corresponding row buffer respectively (Ma: Pg. 5813, section F, second paragraph, subvector i.e., two adjacent elements for locating to different banks i.e., row buffers (preset being two and L being 2).
Regarding claim 8, while Ma teaches the data processing method of claim 7, a reading sequence as well as the ceiling values (Pg. 5813 Col. 1 Section F second and third paragraph; Pg. 5812 Section D), Ma does not explicitly teach based on a reading sequence as well as dimension of input matrices determining a storage position of elements to be read and transposed.
However, Gunnam teaches cyclic right shifting of inputs in order to generate a transposition, as well as shifting of a reading sequence (the rows or columns being shifted), as well as acquiring a storage position of the final output by shifting (¶ 0051 - 0052).
The motivation to combine with respect to claim 2 applies equally to claim 8.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Redfern et al. (US 2018/0253402) (hereinafter “Redfern”).
While Ma teaches the data processing method of claim 1, Ma does not explicitly teach the preset offset being with respect to the row number.
However, Redfern teaches:
wherein the preset offset is set according to the row number of the target row in the target matrix (Redfern: ¶ 0027 preset offset is set according to the target row number).
It would be obvious before the effective filing date of the claimed invention to combine the row number offset as taught by Redfern with the data processing method as taught by Ma because both teachings are directed towards memory efficient matrix transposition. One with ordinary skill in the art would be motivated to combine the teachings because doing so would make matrix composition more oriented towards the row number data of each input data provided to the circuit (Redfern: ¶ 0027).
Claims 10 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ma.
Regarding claim 10, Ma teaches:
An acceleration unit (Pg. 5811 Fig. 4 with matrix transposition module being further shown in Pg 5811 Fig. 5), comprising:
an input buffer, for buffering a target matrix to be transposed (Fig. 4 FIFO as input buffer for receiving input i.e., target matrix);
shifting elements in the target row along a first direction under the control of a shift control signal, to acquire a shifted target row (Pg. 5812 steps 1 and 2 and paragraph after, row shift write strategy to take place);
at least two row buffers, for buffering elements in the shifted target row and for outputting elements read correspondingly from each row buffer (Fig. 5 MBTBs as row buffers);
writing the elements read correspondingly from each row buffer into an output buffer as a row (Pg. 5812 steps 1 and 2 and paragraph after writing elements of corresponding row buffers MBTBs into an output buffer); and
generating the shift control signal according to the size of the target matrix and the number of rows of the row buffers, shift the target row to acquire the shifted target row, write each element in the shifted target row into a corresponding row buffer, and outputting the elements read correspondingly from each row buffer (Pg. 5812 Steps 1 and 2 discusses row shift write strategy that would be dependent on size of input target, having shifted target rows written into MBTBs i.e., row buffers, and outputting elements from each row buffer into an output buffer).
Ma does not explicitly teach a shifter, combiner, or transposition controlling for controlling input from input buffer, shifting of shifter, or shifter writing to buffer and output to combiner.
However, Ma does teach the function of shifting (Pg. 5812 steps 1 and 2 and paragraph after, row shift write strategy to take place) and combining values for the final output to be read from MBTBs accordingly (Pg. 5812 steps 1 and 2 and paragraph after writing elements of corresponding row buffers MBTBs into an output buffer). It would be obvious to have a corresponding shifter and combiner in order to fulfill these functions.
Additionally, Ma teaches a Matrix Transposition Controller (Fig. 5) for controlling the reading out of MBTBs i.e., row buffers to be combined accordingly and write to the output buffer the transposed matrix (Pg. 5812 steps 1 and 2 and paragraph after writing elements of corresponding row buffers MBTBs into an output buffer) as well as a DMA controller for controlling the FIFO buffer i.e., input buffer to read in the target matrix for transposition and correspondingly shift values in rows (Pg. 5811 Col. 1).
Ma discloses the claimed invention except for the matrix transposition controller as claimed. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the DMA controller and Matrix Transposition Controller as disclosed in Ma to function as one controller since it has been held that forming in one piece an article, which has formerly been formed in two pieces and put together, involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). The term “integral” is sufficiently broad to embrace constructions united by such means as fastening and welding. In re Hotte, 177 USPQ 326, 328 (CCPA 1973).
Therefore, Ma teaches:
An acceleration unit, comprising:
an input buffer, for buffering a target matrix to be transposed;
a shifter, for receiving a target row of the target matrix, and for shifting elements in the target row along a first direction under the control of a shift control signal, to acquire a shifted target row;
at least two row buffers, for buffering elements in the shifted target row and for outputting elements read correspondingly from each row buffer;
a combiner, for writing the elements read correspondingly from each row buffer into an output buffer as a row; and
a transposition controller, for generating the shift control signal according to the size of the target matrix and the number of rows of the row buffers, for controlling the input buffer to read the first row of the target matrix and outputting the first row as the target row to the shifter, for controlling the shifter to shift the target row to acquire the shifted target row, for controlling the shifter to write each element in the shifted target row into a corresponding row buffer, and for outputting the elements read correspondingly from each row buffer to the combiner.
Claim 15 recites the apparatus for performing the method claimed in claim 7 and is therefore rejected for the same reasons therein.
Claim 16 recites the apparatus that performs the method recited in claim 8 and is therefore rejected for the same reasons.
Claims 11-12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Alexander et al. (7424036) (hereinafter “Alexander”).
Regarding claim 11, while Ma teaches the acceleration unit of claim 10 and the target row being divided into L subvectors, Ma does not explicitly teach an accumulator.
However, Alexander teaches accumulation buffers i.e., an accumulator to receive inputs and output sub frames i.e., subvectors at a time to the transposition computation downstream (Alexander: Fig. 11 and Fig. 12) a control signal for determining accumulation operators (Alexander: Col. 11 Lines 15-41).
It would be obvious before the effective filing date of the claimed invention to combine the accumulation as taught by Alexander with the acceleration unit as taught by Ma because both teachings are directed towards matrix transposition. One with ordinary skill in the art would be motivated to combine the teachings because doing so would decrease delays in processing (Alexander: Col. 10 Lines 30-40).
Claim 12 recites the apparatus for performing the method of claim 4 and is therefore rejected for the same reasons therein.
Regarding claim 17, Ma teaches the input buffer is a ping pong buffer (Pg. 5811 Col. 1 FIFO Buffer as input buffer; Pg. 5812 Col. 1 Section D ping pong scheme used to manage read and writes from MBTBs, FIFO interfaces with reads from MBTBs in ping pong scheme).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Alexander in view of Gunnam.
While Ma in view of Alexander teaches the acceleration unit of claim 11, Ma in view of Alexander does not explicitly teach cyclic shifting to the right according to a preset offset.
However, Gunnam teaches cyclic shifting to the right by a preset offset (Gunnam: ¶ 0051 – 0052).
The motivation to combine with respect to claim 2 applies equally claim 13.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ma in view of Alexander in view of Gunnam in view of Redfern.
While Ma in view of Alexander in view of Gunnam teaches the acceleration unit of claim 13, Ma in view of Alexander in view of Gunnam does not explicitly teach a preset offset based on the row number of the target row in the target matrix.
However, Redfern teaches a preset offset according to the row number (Redfern: ¶ 0027).
The motivation to combine with respect to claim 5 applies equally to claim 14.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ho (5644517) (hereinafter “Ho”) in view of Ma.
Ma teaches steps S11-14 as discussed with respect to claim 1. Ma does not explicitly teach dividing the target matrix into sub-matrices and transposing with respect to submatrices that are diagonal or non-diagonal, as well as positions of the output matrix being with respect to a diagonal in the original target matrix.
Ho teaches:
dividing the original matrix into a plurality of submatrices, wherein the submatrices comprise diagonal submatrices and non-diagonal submatrices (Ho: Fig. 4B dividing of matrix into submatrices, both diagonal and non-diagonal submatrices, further described in Col. 3 Lines 28-34);
transposing each diagonal submatrix in the original matrix to acquire transposed diagonal submatrices, and writing the transposed diagonal submatrices into first positions wherein the first positions correspond to original positions of the diagonal submatrices (Col. 5 Lines 31-56 transposing of diagonal and non-diagonal submatrices, on-diagonal submatrices remain in the original positions as shown in Fig. 4B);
transposing each non-diagonal submatrix in the original matrix to acquire transposed non-diagonal submatrices, and writing the transposed non-diagonal submatrices, wherein the second positions are symmetrical to the original positions of the non-diagonal submatrices relative to a main diagonal of the original matrix (Col. 5 Lines 31-56 transposing of diagonal and non-diagonal submatrices, off-diagonal submatrices reflect over diagonal line after transposition, further discussed in Col. 1 Lines 31-40 matrix transposition over diagonal results in this arrangement after transposition); wherein two non-diagonal submatrices symmetrical to the main diagonal are transposed in parallel (Col. 3 Lines 27-34 all off-diagonal submatrices transposed concurrently, including submatrices that are symmetrical to the main diagonal).
In combining Ma and Ho, the transposition matrices would take place with the use of MBTBs i.e., row buffers for memory efficient matrix transposition operations. With adapting to the scheme of Ho, diagonal submatrices would be transposed first followed by off-diagonal/non-diagonal submatrices, meaning diagonal submatrices elements would take first positions of row buffers, and off-diagonal submatrices would take second positions of row buffers.
It would be obvious before the effective filing date of the claimed invention to combine the diagonal and non-diagonal submatrices for matrix transposition as taught by Ho with the matrix transposition method as taught by Ma because both references are directed towards matrix transposition. One with ordinary skill in the art would be motivated to combine to the teachings because this would allow for concurrent execution of transposition and making transposition more efficient by making use of diagonal properties (Ho: Col. 5 Lines 31-45).
Allowable Subject Matter
Claims 18-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Applicant claims an acceleration unit, wherein the acceleration unit as in claim 10 comprises:
An input buffer, for buffering a target matrix to be transposed;
A shifter, for receiving a target row of the target matrix, and for shifting elements in the target row along a first direction under the control of a shift control signal, to acquire a shifted target row;
At least two row buffers, for buffering elements in the shifted target row and for outputting elements read correspondingly from each row buffer;
A combiner, for writing the elements read correspondingly from each row buffer into an output buffer as a row; and
A transposition controller, for generating the shift control signal according to the size of the target matrix and the number of rows of the row buffers, for controlling the input buffer to read the first row of the target matrix and outputting the first row as the target row to the shifter, for controlling the shifter to shift the target row to acquire the shifted target row, for controlling the shifter to write each element in the shifted target row into a corresponding row buffer, and for outputting the elements read correspondingly from each row buffer to the combiner.
Wherein claim 11 is dependent on claim 10, further comprising:
An accumulator, for buffering subvectors to be shifted in the target row under the control of an accumulation control signal, and for outputting one subvector to the shifter at a time in sequence, to enable the shifter to shift the subvectors; wherein the target row is divided into several subvectors, wherein the number of the subvectors is L and L is an integer greater than or equal to one;
Wherein the transposition controller also generates the accumulation control signal and outputs the accumulation control signal to the accumulator if the number of columns of the target matrix is greater than the number of rows of the target matrix.
Wherein claim 17 is dependent on claim 11, further comprising:
Wherein the input buffer is a ping pong buffer.
Wherein claim 18 is dependent on claim 17, further comprising:
A multiplexer, coupled between an output terminal of the ping pong buffer and the accumulator, for connecting the ping pong buffer to the input buffer of the accumulator under the control of a buffer selection signal;
Wherein the transposition controller also generates the buffer selection signal and outputs the buffer selection signal to the multiplexer.
Ma teaches the invention as claimed in the claim mappings above. Ma is silent as to a multiplexer for connecting the accumulator and the input buffers as well as a transposition controller for generating a buffer selection signal and outputting a buffer selection signal to the multiplexer.
Ho teaches the invention as claimed in the claim mappings above. Ho is silent as to a multiplexer for connecting the accumulator and the input buffers as well as a transposition controller for generating a buffer selection signal and outputting a buffer selection signal to the multiplexer.
Alexander teaches the invention as claimed in the claim mappings above. Ho is silent as to a multiplexer for connecting the accumulator and the input buffers as well as a transposition controller for generating a buffer selection signal and outputting a buffer selection signal to the multiplexer.
Claim 19 dependent on claim 18 is therefore also allowable.
Conclusion
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/M.D.R./Examiner, Art Unit 2151
/EMILY E LAROCQUE/Primary Examiner, Art Unit 2182
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