Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 8-11 is/are rejected under 35 U.S.C. 102a1/a2 as being anticipated by Lutchyn (US 2019/0013457).
Regarding claims 1 and 8; Lutchyn teaches a topological superconductor device and method of making thereof (abstract) comprising a superconducting wire having a first junction near a first end of the wire and a second junction near a second end of the wire (AI superconducting wire can be connected/disconnected from the topological layers indicates junctions at the end; para. 0032) a first side plunger gate in a first layer of the device operable to tune a first section of wire located between the first junction and a first end of the wire (fig. 7, #720; para. 0032-0034), a second side plunger gate in a first layer of the device operable to tune a second section of wire located between the second junction and a second end of the wire (fig. 7, #722; para. 0032-0034), a middle plunger formed int eh first layer of the device operable to tune a middle section of the wire between the first and second junction (fig. 7, #724; para. 0032-0034), a first cutter gate formed in the second layer operable to open/close the first junction (para. 0032), and a second cutter gate formed in the second layer operable to open/close the second junction, both cutter gates in a second layer different from the first layer (para. 0032).
Regarding claims 2-4, 9-11, Lutchyn teaches that the external electric field results from applying a gate voltage to one or more bottom gates coupled to the segments of the quantum device the applying the field creates a non-topological segment of the quantum device in a region of the quantum device having a dielectric layer (para. 0053). From this disclosure, the middle plunger gate is operable to tune its corresponding middle segment of the wire into the topological phase by tuning its gate voltage away from the gate voltage that creates a non-topological phase. In the same way, the first and second plunger gates are operable to tune the first and second segments to non-topological phases (trivial phases) by applying gate voltages to said first and second plunger gates that create a similar field as the one that tunes the middle segment into a trivial phase (even if it would require much larger gate voltages than tuning the middle section due to reduced lever arm of the first and second plunger gates compared to the middle plunger gate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 5-7, 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lutchyn (US 2019/0013457) in view of Poschl (“Nonlocal conductance spectroscopy of Andreev…”).
Lutchyn teaches a method and product as described above in claims 1 and 8 as described above, but fails to teach that the wire is patterned on a two dimensional electron gas (claims 5, 12, 15).
Poschl, however, teaches a aluminum nanowire superconductor device (abstract) wherein the aluminum wire is deposited on a two dimensional electron gas for the purpose of coupling the gate controlled probes to the nanowire (page 1, second column).
Therefore, it would have been obvious to one of ordinary skill in the art to provide the aluminum wire of Lutchyn deposited on a two dimensional electron gas in order to couple the gate controlled probes to the nanowire as taught by Poschl.
Regarding claims 6-7, 13-14 and 15; Poschl teaches aluminum probes coupled to the 2DEG for the purpose of providing several equivalent probes along the side of the nanowire (the probes act as helper gates and are able to control the electron density of the 2DEG by applying voltage; page 1-page 2).
Therefore, it would have been obvious to one of ordinary skill in the art to provide aluminum probes (helper gates) coupled to the 2DEG of Lutchyn in order to provide several equivalent probes along the side of the nanowire as taught by Poschl
Regarding claim 15; Lutchyn teaches a topological superconductor device and method of making thereof (abstract) comprising a superconducting wire having a first junction near a first end of the wire and a second junction near a second end of the wire (AI superconducting wire can be connected/disconnected from the topological layers indicates junctions at the end; para. 0032) a first side plunger gate in a first layer of the device operable to tune a first section of wire located between the first junction and a first end of the wire (fig. 7, #720; para. 0032-0034), a second side plunger gate in a first layer of the device operable to tune a second section of wire located between the second junction and a second end of the wire (fig. 7, #722; para. 0032-0034), a middle plunger formed int eh first layer of the device operable to tune a middle section of the wire between the first and second junction (fig. 7, #724; para. 0032-0034), a first cutter gate formed in the second layer operable to open/close the first junction (para. 0032), and a second cutter gate formed in the second layer operable to open/close the second junction (para. 0032).
Regarding claims 16-18, Lutchyn teaches that the external electric field results from applying a gate voltage to one or more bottom gates coupled to the segments of the quantum device the applying the field creates a non-topological segment of the quantum device in a region of the quantum device having a dielectric layer (para. 0053). From this disclosure, the middle plunger gate is operable to tune its corresponding middle segment of the wire into the topological phase by tuning its gate voltage away from the gate voltage that creates a non-topological phase. In the same way, the first and second plunger gates are operable to tune the first and second segments to non-topological phases (trivial phases) by applying gate voltages to said first and second plunger gates that create a similar field as the one that tunes the middle segment into a trivial phase (even if it would require much larger gate voltages than tuning the middle section due to reduced lever arm of the first and second plunger gates compared to the middle plunger gate).
Regarding claim 19, it appears that the plunger gates of the combined prior art would be able to deplete the 2DEG to help define a one dimensional conducting channel (Aghaee; page 10-11; sating that the plunger voltage bellow a level as a bottom of the lowest sub band and that voltage providing the 2DEG as depleted).
Regarding claim 20, Lutchyn teaches a dielectric layer formed between the superconductor wire and the first gate layer (the limitation is met as the arbitrary distinction of over and under are broad such that the disclosure of the dielectric between the wire and the first layer meets the limitation; fig. 7).
Claim(s) 5-7, 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lutchyn (US 2019/0013457) in view of Aghaee (InAs-Al Hybrid devices passing the topological gap protocol).
Lutchyn teaches a method and product as described above in claims 1, 8, 15.
Regarding claims 5, 12 and 15, Aghaee teaches a topological superconductor device (abstract) wherein the aluminum wire is deposited on a two dimensional electron gas for the purpose of providing low disorder environment at low temperatures (pages 5-6).
Therefore, it would have been obvious to one of ordinary skill in the art to provide the aluminum wire of Lutchyn deposited on a two dimensional electron gas in order to provide low disorder environment at low temperatures as taught by Aghaee.
Regarding claims 6-8, 13-15; Lutchyn fails to teach first and second helper gates operable to control density of electrons in a first and second region.
Aghaee teaches a topological superconductor device (abstract) comprising helper gates formed in a first layer for the purpose of controlling density of electrons in the respective regions of the 2DEG (pages 4-5).
Therefore, it would have been obvious to one of ordinary skill in the art to provide helper gates formed in a first layer of Lutchyn in order to control density of electrons in the respective regions of the 2DEG as taught by Aghaee.
Regarding claim 15; Lutchyn teaches a topological superconductor device and method of making thereof (abstract) comprising a superconducting wire having a first junction near a first end of the wire and a second junction near a second end of the wire (AI superconducting wire can be connected/disconnected from the topological layers indicates junctions at the end; para. 0032) a first side plunger gate in a first layer of the device operable to tune a first section of wire located between the first junction and a first end of the wire (fig. 7, #720; para. 0032-0034), a second side plunger gate in a first layer of the device operable to tune a second section of wire located between the second junction and a second end of the wire (fig. 7, #722; para. 0032-0034), a middle plunger formed int eh first layer of the device operable to tune a middle section of the wire between the first and second junction (fig. 7, #724; para. 0032-0034), a first cutter gate formed in the second layer operable to open/close the first junction (para. 0032), and a second cutter gate formed in the second layer operable to open/close the second junction (para. 0032).
Regarding claims 16-18, Lutchyn teaches that the external electric field results from applying a gate voltage to one or more bottom gates coupled to the segments of the quantum device the applying the field creates a non-topological segment of the quantum device in a region of the quantum device having a dielectric layer (para. 0053). From this disclosure, the middle plunger gate is operable to tune its corresponding middle segment of the wire into the topological phase by tuning its gate voltage away from the gate voltage that creates a non-topological phase. In the same way, the first and second plunger gates are operable to tune the first and second segments to non-topological phases (trivial phases) by applying gate voltages to said first and second plunger gates that create a similar field as the one that tunes the middle segment into a trivial phase (even if it would require much larger gate voltages than tuning the middle section due to reduced lever arm of the first and second plunger gates compared to the middle plunger gate).
Regarding claim 19, it appears that the plunger gates of the combined prior art would be able to deplete the 2DEG to help define a one dimensional conducting channel (Aghaee; page 10-11; sating that the plunger voltage bellow a level as a bottom of the lowest sub band and that voltage providing the 2DEG as depleted).
Regarding claim 20, Aghaee teaches a dielectric over the superconductor wire and under the gates (fig. 2(d)).
Conclusion
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/PAUL A WARTALOWICZ/ Primary Examiner, Art Unit 1735