DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Applicant is reminded of the proper content of an abstract of the disclosure.
A patent abstract is a concise statement of the technical disclosure of the patent and should include that which is new in the art to which the invention pertains. The abstract should not refer to purported merits or speculative applications of the invention and should not compare the invention with the prior art.
If the patent is of a basic nature, the entire technical disclosure may be new in the art, and the abstract should be directed to the entire disclosure. If the patent is in the nature of an improvement in an old apparatus, process, product, or composition, the abstract should include the technical disclosure of the improvement. The abstract should also mention by way of example any preferred modifications or alternatives.
Where applicable, the abstract should include the following: (1) if a machine or apparatus, its organization and operation; (2) if an article, its method of making; (3) if a chemical compound, its identity and use; (4) if a mixture, its ingredients; (5) if a process, the steps.
Extensive mechanical and design details of an apparatus should not be included in the abstract. The abstract should be in narrative form and generally limited to a single paragraph within the range of 50 to 150 words in length.
See MPEP § 608.01(b) for guidelines for the preparation of patent abstracts.
The abstract of the disclosure is objected to because it does not meet with the require length (should be a single paragraph within the range of 50 to 150 words in length). Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7-11, 13, 16-18, 21 and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chan et al. (US 2022/0393587), hereinafter Chan.
Regarding claim 1, Chan discloses (see figures 1-7) an apparatus (figure 4) comprising: a voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]); and a control circuitry (figure 4, part control circuitry generated by 402 and 406) coupled to the voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]) (paragraph [0022]; the voltage regulator 400 may be a multi-phase voltage regulator including N (N≥2) sets of power stage circuit and inductor coupled between the controller circuit 402 and the load 101 in parallel), the control circuitry (figure 4, part control circuitry generated by 402 and 406) to: receive a sensed current (figure 4, part Isen) that corresponds to a load current (figure 4, part Io) provided to a load (figure 4, part 101) of the voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]) (paragraph [0017]; In a steady state, the average inductor current ave(IL) is equal to the average load current ave (Io) due to ave(Ic)=0. The inductor current IL can be sensed to act as an approximation of the load current Io); determine a prediction of a dynamic voltage ID (DVID) inrush current (figure 4, part Icomp) associated with a DVID change (figure 5, part DVID change at t1-t2 and t3-t4) (paragraph [0023]; the compensation circuit 410 is arranged to generate the compensation signal Sc in response to a DVID event. As shown in FIG. 4, two parameters Co and SR [slew rate] are received by the compensation circuit 410, where the parameter Co is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage Vo from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID). As mentioned above, the increase of the inductor current IL during a DVID up event results from a non-zero charging current of the output capacitor Co, and the decrease of the inductor current IL during a DVID down event results from a non-zero discharging current of the output capacitor Co. A product of the parameters (i.e. C0×SR) may be regarded as an estimation of the charging/discharging current of the output capacitor Co that happens during a DVID up/down event. The compensation signal Sc is generated according to a compensation current Icomp with a current value set by a product of the two parameters (i.e. C0×SR), and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL). In this way, disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the DVID up/down event) and the load current IL (which may be increased/decreased by the charging/discharging current of the output capacitor Co during the DVID up/down event) can be compensated by the compensation signal Sc); and control (figure 4, part control circuitry generated by 702 and 706) a number of active phases of the voltage regulator (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]) based on the sensed current (figure 4, part Isen) and the prediction of the DVID inrush current (figure 4, part Icomp) (paragraphs [0020]-[0025]; during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens).
Regarding claim 2, Chan discloses everything claimed as applied above (see claim 1). Further, Chan discloses (see figures 1-7) the prediction of DVID inrush current (figure 4, part Icomp) is determined based on a slew rate (figure 4, part SR) and an output capacitance of the voltage regulator (figure 4, part Co) (paragraph [0023]; the compensation circuit 410 is arranged to generate the compensation signal Sc in response to a DVID event. As shown in FIG. 4, two parameters Co and SR [slew rate] are received by the compensation circuit 410, where the parameter Co is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage Vo from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID). As mentioned above, the increase of the inductor current IL during a DVID up event results from a non-zero charging current of the output capacitor Co, and the decrease of the inductor current IL during a DVID down event results from a non-zero discharging current of the output capacitor Co. A product of the parameters (i.e. C0×SR) may be regarded as an estimation of the charging/discharging current of the output capacitor Co that happens during a DVID up/down event. The compensation signal Sc is generated according to a compensation current Icomp with a current value set by a product of the two parameters (i.e. C0×SR), and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL). In this way, disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the DVID up/down event) and the load current IL (which may be increased/decreased by the charging/discharging current of the output capacitor Co during the DVID up/down event) can be compensated by the compensation signal Sc).
Regarding claim 3, Chan discloses everything claimed as applied above (see claim 2). Further, Chan discloses (see figures 1-7) the slew rate (figure 4, part SR) and output capacitance are predefined (figure 4, part Co) (paragraph [0023]; two parameters Co and SR are received by the compensation circuit 410, where the parameter Co is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage Vo from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID)).
Regarding claim 4, Chan discloses everything claimed as applied above (see claim 1). Further, Chan discloses (see figures 1-7) the number of active phases (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]) is controlled (figure 4, part through control circuitry generated by 402 and 406) based on a sum (figure 4, part sum of Isen and Icomp through Sc and Sfb) of the sensed current (figure 4, part Isen) and the prediction of the DVID inrush current (figure 4, part Icomp) (paragraphs [0020]-[0025]; during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens… The compensation signal Sc is generated according to a compensation current Icomp with a current value set by a product of the two parameters (i.e. C0×SR), and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL). In this way, disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the DVID up/down event) and the load current IL (which may be increased/decreased by the charging/discharging current of the output capacitor Co during the DVID up/down event).
Regarding claim 7, Chan discloses everything claimed as applied above (see claim 1). Further, Chan discloses (see figures 1-7) to control (figure 4, part control circuitry generated by 402 and 406) the number of active phases (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]), the control circuitry (figure 4, part control circuitry generated by 402 and 406) is to: determine a first number of active phases (figures 4 and 5, part first number of active phases of the voltage regulator generated by xN [404 and LN]; at DVID up/down event) based on the sensed current (figures 4 and 5, part Isen) and the prediction of the DVID inrush current (figures 4 and 5, part Icomp); determine a second number of active phases (figures 4 and 5, part second number of active phases of the voltage regulator generated by xN [404 and LN]; at steady state) based on the sensed current (figures 4 and 5, part Isen) without taking into account the prediction of the DVID inrush current (figures 4 and 5, part witout Icomp; at steady state Icomp = 0); and activate the greater (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]; active the greater number of active phases based on greater load current demand) of the first number of active phases (figure 4, part first number of active phases of the voltage regulator generated by xN [404 and LN]; at DVID up/down event) or the second number of active phase (figure 4, part second number of active phases of the voltage regulator generated by xN [404 and LN]; at steady state) (paragraphs [0017]-[0020]; the average inductor current ave(IL) of the inductor LN is equal to a sum of the average capacitor current ave(Ic) of the output capacitor Co and the average load current ave(Io) of the load 101 (i.e. ave(IL)=ave(Io)+ave(Ic)). In a steady state, the average inductor current ave(IL) is equal to the average load current ave (Io) due to ave(Ic)=0. The inductor current IL can be sensed to act as an approximation of the load current Io… during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases).
Regarding claim 8, Chan discloses everything claimed as applied above (see claim 1). Further, Chan discloses (see figures 1-7) the load (figure 4, part 101) coupled to an output of the voltage regulator (figure 4, part output of the voltage regulator generated by xN [404 and LN]).
Regarding claim 9, Chan discloses everything claimed as applied above (see claim 8). Further, Chan discloses (see figures 1-7) the load (figure 4, part 101) includes one or more processors (figure 4, part 101) (paragraph [0022]; the voltage regulator 400 is capable of regulating the output voltage Vo delivered to the load (e.g. microprocessor) 101).
Regarding claim 10, Chan discloses (see figures 1-7) an integrated circuit (figure 4) comprising: one or more processors (figure 4, part processor at 101) (paragraph [0022]; the voltage regulator 400 is capable of regulating the output voltage Vo delivered to the load (e.g. microprocessor) 101); a voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]) to provide a supply voltage (figure 4, part Vo) to the one or more processors (figure 4, part processor at 101), wherein the voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]) includes multiple phases (figure 4, part voltage regulator generated by xN [404 and LN]) (paragraph [0022]; the voltage regulator 400 may be a multi-phase voltage regulator including N (N≥2) sets of power stage circuit and inductor coupled between the controller circuit 402 and the load 101 in parallel); and control circuitry (figure 4, part control circuitry generated by 402 and 406) coupled to the voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]), the control circuitry (figure 4, part control circuitry generated by 402 and 406) to: receive a dynamic voltage ID (DVID) change command (figure 4, part DVID change command generated by Vref) to change a DVID (figure 5, part DVID change at t1-t2 and t3-t4) of the voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]) (paragraphs [0024]-[0025]; a DVID up event and a DVID down event according to an embodiment of the present invention. A DVID up event is triggered at t1, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t1 to a higher voltage setting at t2according to a slew rate SR_UP determined by the load 101 (e.g. microprocessor)… A DVID down event is triggered at t3, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t3 to a lower voltage setting at t4 according to a slew rate SR_DN determined by the load 101 (e.g. microprocessor)); estimate a dynamic voltage ID (DVID) inrush current (figure 4, part Icomp) associated with the change of the DVID (figure 5, part DVID change at t1-t2 and t3-t4) based on an output capacitance (figure 4, part Co) of the voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]) (paragraph [0023]; the compensation circuit 410 is arranged to generate the compensation signal Sc in response to a DVID event. As shown in FIG. 4, two parameters Co and SR [slew rate] are received by the compensation circuit 410, where the parameter Co is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage Vo from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID). As mentioned above, the increase of the inductor current IL during a DVID up event results from a non-zero charging current of the output capacitor Co, and the decrease of the inductor current IL during a DVID down event results from a non-zero discharging current of the output capacitor Co. A product of the parameters (i.e. C0×SR) may be regarded as an estimation of the charging/discharging current of the output capacitor Co that happens during a DVID up/down event. The compensation signal Sc is generated according to a compensation current Icomp with a current value set by a product of the two parameters (i.e. C0×SR), and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL). In this way, disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the DVID up/down event) and the load current IL (which may be increased/decreased by the charging/discharging current of the output capacitor Co during the DVID up/down event) can be compensated by the compensation signal Sc); and determine (figure 4, part control circuitry generated by 402 and 406) a number of the phases to be active (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]) based on the estimated DVID inrush current (figure 4, part Icomp) (paragraphs [0020]-[0025]; during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens).
Regarding claim 11, Chan discloses everything claimed as applied above (see claim 10). Further, Chan discloses (see figures 1-7) the control circuitry (figure 4, part control circuitry generated by 402 and 406) is further to obtain a sensed current of the voltage regulator (figure 4, part Isen), wherein the sensed current (figure 4, part Isen) corresponds to a load current (figure 4, part Io) provided to the one or more processors (figure 4, part processor at 101) (paragraph [0017]; In a steady state, the average inductor current ave(IL) is equal to the average load current ave (Io) due to ave(Ic)=0. The inductor current IL can be sensed to act as an approximation of the load current Io), and wherein the number of the phases to be active (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]) is determined further based on the sensed load current (figure 4, part Isen) (paragraphs [0020]-[0025]; during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens… The compensation signal Sc is generated according to a compensation current Icomp with a current value set by a product of the two parameters (i.e. C0×SR), and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL). In this way, disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the DVID up/down event) and the load current IL (which may be increased/decreased by the charging/discharging current of the output capacitor Co during the DVID up/down event).
Regarding claim 13, Chan discloses everything claimed as applied above (see claim 10). Further, Chan discloses (see figures 1-7) the DVID inrush current (figure 4, part Icomp) is estimated further based on a slew rate of the voltage regulator (figure 4, part SR) (paragraph [0023]; the compensation circuit 410 is arranged to generate the compensation signal Sc in response to a DVID event. As shown in FIG. 4, two parameters Co and SR [slew rate] are received by the compensation circuit 410, where the parameter Co is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage Vo from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID). As mentioned above, the increase of the inductor current IL during a DVID up event results from a non-zero charging current of the output capacitor Co, and the decrease of the inductor current IL during a DVID down event results from a non-zero discharging current of the output capacitor Co. A product of the parameters (i.e. C0×SR) may be regarded as an estimation of the charging/discharging current of the output capacitor Co that happens during a DVID up/down event. The compensation signal Sc is generated according to a compensation current Icomp with a current value set by a product of the two parameters (i.e. C0×SR), and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL). In this way, disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the DVID up/down event) and the load current IL (which may be increased/decreased by the charging/discharging current of the output capacitor Co during the DVID up/down event) can be compensated by the compensation signal Sc).
Regarding claim 16, claim 7 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 17, Chan discloses (see figures 1-7) one or more non-transitory, computer-readable media (NTCRM) (figure 4, part NTCRM that have the instructions stored to be executed by the processor at 101) having instructions, stored thereon, that when executed by one or more processors (figure 4, part processor at 101) (paragraph [0022]; the voltage regulator 400 is capable of regulating the output voltage Vo delivered to the load (e.g. microprocessor) 101) cause a control circuitry (figure 4, part control circuitry generated by 402 and 406) of a voltage regulator (figure 4, part voltage regulator generated by xN [404 and LN]) to: receive, from a power control unit of a load (figure 4, part 101), a command (figure 4, part command generated by Vref) to change an output voltage of the voltage regulator (figure 4, part Vo) (figure 5, part VID) (paragraphs [0024]-[0025]; a DVID up event and a DVID down event according to an embodiment of the present invention. A DVID up event is triggered at t1, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t1 to a higher voltage setting at t2according to a slew rate SR_UP determined by the load 101 (e.g. microprocessor)… A DVID down event is triggered at t3, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t3 to a lower voltage setting at t4 according to a slew rate SR_DN determined by the load 101 (e.g. microprocessor)); receive a sensed current (figure 4, part Isen) that corresponds to a load current (figure 4, part Io) provided to load of the voltage regulator (figure 4, part 101) (paragraph [0017]; In a steady state, the average inductor current ave(IL) is equal to the average load current ave (Io) due to ave(Ic)=0. The inductor current IL can be sensed to act as an approximation of the load current Io); estimate an inrush current (figure 4, part Icomp) associated with the change in the output voltage (figure 4, part Vo; through slew rate SR of Vo) (paragraph [0023]; the compensation circuit 410 is arranged to generate the compensation signal Sc in response to a DVID event. As shown in FIG. 4, two parameters Co and SR [slew rate] are received by the compensation circuit 410, where the parameter Co is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage Vo from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID). As mentioned above, the increase of the inductor current IL during a DVID up event results from a non-zero charging current of the output capacitor Co, and the decrease of the inductor current IL during a DVID down event results from a non-zero discharging current of the output capacitor Co. A product of the parameters (i.e. C0×SR) may be regarded as an estimation of the charging/discharging current of the output capacitor Co that happens during a DVID up/down event. The compensation signal Sc is generated according to a compensation current Icomp with a current value set by a product of the two parameters (i.e. C0×SR), and then injected to the feedback signal Sfb generated from the loadline 408 according to the sensed current signal Isen that provides information of the inductor current IL (Isen≅IL). In this way, disturbance of the feedback signal Sfb that results from mismatch between the load current Io (which may be unchanged during the DVID up/down event) and the load current IL (which may be increased/decreased by the charging/discharging current of the output capacitor Co during the DVID up/down event) can be compensated by the compensation signal Sc); and control a number of active phases of the voltage regulator (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]) based on the sensed current (figure 4, part Isen) and the estimated inrush current (figure 4, part Icomp) (paragraphs [0020]-[0025]; during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens).
Regarding claim 18, claim 2 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 21, claim 7 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 22, Chan discloses everything claimed as applied above (see claim 17). Further, Chan discloses (see figures 1-7) the command (figure 4, part command generated by Vref) is a dynamic voltage ID (DVID) command (figure 5, part VID) (paragraphs [0024]-[0025]; a DVID up event and a DVID down event according to an embodiment of the present invention. A DVID up event is triggered at t1, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t1 to a higher voltage setting at t2according to a slew rate SR_UP determined by the load 101 (e.g. microprocessor)… A DVID down event is triggered at t3, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t3 to a lower voltage setting at t4 according to a slew rate SR_DN determined by the load 101 (e.g. microprocessor)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0393587), hereinafter Chan, in view of Tang et al. (US 2007/0013350), hereinafter Tang.
Regarding claim 5, Chan discloses everything claimed as applied above (see claim 4). Further, Chan discloses (see figures 1-7) control (figure 4, part control circuitry generated by 702 and 706) the number of active phases (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]), the control circuitry (figure 4, part control circuitry generated by 702 and 706) and the sum (figure 4, part sum of Isen and Icomp through Sc and Sfb) (paragraphs [0020]-[0025]; during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens). However, Chan does not expressly disclose the control circuitry is to compare the sum to one or more automatic phase scaling (APS) thresholds.
Tang teaches (see figures 1-15) control (figure 7) the number of active phases (figure 7, part phase controls), the control circuitry (figure 7) is to compare (figures 7 and 8, part 708 [802-820]) the sum (figures 7 and 8, part I 705) to one or more automatic phase scaling (APS) thresholds (figure 8, parts THRESH 1-5) (Figures 2 and 3, parts Ix vs thresholds at A-C) (paragraphs [0051]-[0052] and [0057]-[0060]).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the control circuitry of Chan with phase control features as taught by Tang and obtain control the number of active phases, the control circuitry is to compare the sum to one or more automatic phase scaling (APS) thresholds, because it provides more efficient control with accurate increase or decrease number of active phases to achieve optimum power efficiency (Abstract).
Regarding claim 12, claims 4 and 5 in combination have the same limitations, based on this is rejected for the same reasons.
Regarding claim 19, claims 4 and 5 in combination have the same limitations, based on this is rejected for the same reasons.
Claims 6, 14, 15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chan et al. (US 2022/0393587), hereinafter Chan, in view of Carroll et al. (US 2013/0234691), hereinafter Carroll.
Regarding claim 6, Chan discloses everything claimed as applied above (see claim 1). Further, Chan discloses (see figures 1-7) to control (figure 4, part control circuitry generated by 702 and 706) the number of active phases (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]), the control circuitry (figure 4, part control circuitry generated by 702 and 706) is to: turn on phases of the voltage regulator (figure 4, part turn on phases of the voltage regulator generated by xN [404 and LN] at DVID change) in response to the DVID change (figure 5, part DVID change at t1-t2 and t3-t4) (paragraphs [0024]-[0025]; a DVID up event and a DVID down event according to an embodiment of the present invention. A DVID up event is triggered at t1, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t1 to a higher voltage setting at t2according to a slew rate SR_UP determined by the load 101 (e.g. microprocessor)… A DVID down event is triggered at t3, such that a VID voltage of the load 101 (e.g. microprocessor) changes from a present voltage setting at t3 to a lower voltage setting at t4 according to a slew rate SR_DN determined by the load 101 (e.g. microprocessor)), and then set the number of active phases (figure 4, part active phases of the voltage regulator generated by xN [404 and LN]) based on the sensed current (figure 4, part Isen) and the prediction of the DVID inrush current (figure 4, part Icomp) (paragraphs [0020]-[0025]; during a phase number change event that changes a number of phases enabled in the voltage regulator 100 from a first phase number to a second phase number different from the first phase number, the inductor current IL also cannot be an approximation of the load current Io. For example, when the phase number (i.e. the number of phases enabled in the multi-phase voltage regulator) decreases, the remaining phase current needs to be settled to a new level, which may result in undershoot of the output voltage Vo if no compensation is applied to the inaccurate loadline. The output voltage undershoot does not only happen when the phase number decreases. It could happen when an operation mode transition happens). However, Chan does no expressly disclose turn on all phases of the voltage regulator in response to the DVID change, and then set the number of active phases based on the sensed current and the prediction of the DVID inrush current, wherein the number of active phases is less than all the phases.
Carroll teaches (see figures 1-9) to control (figures 1 and 5, part through 140) the number of active phases (figures 1 and 5, part active phases from the multi-phase 100) (paragraph [0049]; power supply 100 includes multiple phases. Each of the multiple phases can operate in a similar manner as the example phase shown in FIG. 1. In such an embodiment, the controller 100 operates the phases to maintain the output voltage 190 within a desired range to power load 118. The phases can be operated out of phase with respect to each other), the control circuitry (figures 1 and 5, part 140) is to: turn on all phases of the voltage regulator (figures 1 and 5, part turn on all phases from the multi-phase 100) in response to the DVID change (figure 4, part DVID change), and then set the number of active phases (figures 1 and 5, part number of active phases from the multi-phase 100) based on the sensed current (figure 4, part Iinductor) and the prediction of the DVID inrush current (figure 4, part prediction of the DVID inrush current output from 582) (paragraph [0062]; via compensation value generator 145, the controller 140 multiplies an output capacitance associated with capacitors 125 by the desired rate of changing the output voltage as specified by the output voltage setting information 170 to produce a surge current value. The surge current value indicates an amount of current to account for a change in the output voltage 190 on the output capacitors 125 during a transition of changing the magnitude of the output voltage 190 from an initial output voltage setting to a specified target output voltage setting), wherein the number of active phases (figures 1 and 5, part number of active phases from the multi-phase 100) is less than all the phases (figures 1 and 5, part turn on all phases from the multi-phase 100) (paragraph [0051]; The controller 140 can select how many phases to activate depending on an amount of current consumed by the load 118. For example, when the load 118 consumes a relatively large amount of current, the controller 100 can activate multiple phases to power the load 118. When the load 118 consumes a relatively small amount of current, the controller 140 can activate a single phase or fewer phases to power the load 118).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the circuit of Chan with the control features as taught by Carroll and obtain to control the number of active phases, the control circuitry is to: turn on all phases of the voltage regulator in response to the DVID change, and then set the number of active phases based on the sensed current and the prediction of the DVID inrush current, wherein the number of active phases is less than all the phases, because it provides more accurate and efficient control in order to obtain more accurate output voltage for powering a respective load (paragraph [0040]).
Regarding claim 14, Chan discloses everything claimed as applied above (see claim 10). Further, Chan discloses (see figures 1-7) a value of the output capacitance (figure 4, part Co) (paragraph [0023]; two parameters Co and SR [slew rate] are received by the compensation circuit 410, where the parameter Co is the capacitance of the output capacitor, and the parameter SR may be provided by the load 101 (e.g. microprocessor) and indicates a slew rate of changing the output voltage Vo from a present voltage setting (which is indicated by a present VID) to a next voltage setting (which is indicated by a next VID)). However, Chan does not expressly disclose a register to store.
Carroll teaches (see figures 1-9) a register to store a value of the output capacitance (figures 1 and 5, part Cout 125) (paragraph [0093]; The value of the output capacitance associated with output capacitors 125 can be programmed in a storage device such as a register of the power supply 100. COUT is a pre-known value stored in non-volatile memory of the voltage regulator (i.e., power supply) because an output capacitance of the output capacitors is known depending on how the power supply is populated with components).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the circuit of Chan with the store features as taught by Carroll, because it provides more accurate and efficient control in order to obtain more accurate output voltage for powering a respective load (paragraph [0040]).
Regarding claim 15, claim 6 has the same limitations, based on this is rejected for the same reasons.
Regarding claim 20, claim 6 has the same limitations, based on this is rejected for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838