CTFR 17/982,391 CTFR 93529 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment The Amendment filed on 03/09/2026 has been entered. Claims 1-20 remain pending in the application. Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Step 1 : Claims 1-7 are directed to a method, claims 8-14 are directed to a product and claims 15-20 are directed to a system. Therefore, the claims are eligible under Step 1 for being directed to a process, a manufacture and a machine respectively. Independent claims 1, 8 and 15: Step 2A Prong 1: Claims recite: identifying quantum logic gates of a quantum circuit to be grouped together based on one or more gate characteristics comprising gate type, gate color, or gate barriers - Under its broadest reasonable interpretation in light of the specification, this limitation encompasses the mental process of evaluating data and selecting data based on judgement, which is observing, evaluating and judging that is practically capable of being performed in the human mind with the assistance of pen and paper ; grouping said identified quantum logic gates into a grouped set of quantum logic gates - Under its broadest reasonable interpretation in light of the specification, this limitation encompasses the mental process of evaluating data and selecting data based on judgement, which is observing, evaluating and judging that is practically capable of being performed in the human mind with the assistance of pen and paper ; and Step 2A Prong 2 : This judicial exception is not integrated into a practical application because they recite the additional elements: A method for assisting users in creating quantum circuits; A computer program product for assisting users in creating quantum circuits, the computer program product comprising one or more computer readable storage mediums having program code embodied therewith, the program code comprising programming instructions; A system, comprising: a memory for storing a computer program for assisting users in creating quantum circuits; and a processor connected to said memory, wherein said processor is configured to execute program instructions of the computer program; graphical user interface - These limitations amount to components of a general purpose computer that applies a judicial exception, by use of conventional computer functions (see MPEP § 2106.05(b)). displaying a plurality of filters in connection with said quantum circuit, wherein each of said plurality of filters is configured to display metadata retrieved by a filter engine regarding a transpilation of said grouped set of quantum logic gates to a specific quantum hardware structure - the steps recited at a high level of generality, and amounts to mere data outputting, which is a form of insignificant extra-solution activity (see MPEP § 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claims are thus directed to the abstract idea. Step 2B : The claims do not include additional elements that amount to significantly more than the judicial exception. The additional elements: A method for assisting users in creating quantum circuits; A computer program product for assisting users in creating quantum circuits, the computer program product comprising one or more computer readable storage mediums having program code embodied therewith, the program code comprising programming instructions; A system, comprising: a memory for storing a computer program for assisting users in creating quantum circuits; and a processor connected to said memory, wherein said processor is configured to execute program instructions of the computer program; graphical user interface - These limitations amount to components of a general purpose computer that applies a judicial exception, by use of conventional computer functions (see MPEP § 2106.05(b)). displaying a plurality of filters in connection with said quantum circuit, wherein each of said plurality of filters is configured to display metadata retrieved by a filter engine regarding a transpilation of said grouped set of quantum logic gates to a specific quantum hardware structure - which is a well-understood, routine, conventional activity similar to presenting offers and gathering statistics described in MPEP 2106.05(d)(II). Accordingly, these additional elements do not amount to significantly more than the judicial exception. As such, the claims are ineligible. Dependent claims 2, 9 and 16: Step 2A Prong 1: The claim recites the abstract ideas of claims 1, 8 and 15. Step 2A Prong 2 : This judicial exception is not integrated into a practical application because they recite the additional elements: wherein one of said plurality of filters is configured to illustrate which gates form said grouped set of quantum logic gates - the steps recited at a high level of generality, and amounts to mere data outputting, which is a form of insignificant extra-solution activity (see MPEP § 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claims are thus directed to the abstract idea. Step 2B : The claims do not include additional elements that amount to significantly more than the judicial exception. The additional elements: wherein one of said plurality of filters is configured to illustrate which gates form said grouped set of quantum logic gates - which is a well-understood, routine, conventional activity similar to presenting offers and gathering statistics described in MPEP 2106.05(d)(II). Accordingly, these additional elements do not amount to significantly more than the judicial exception. As such, the claims are ineligible. Dependent claims 3, 10 and 17: Step 2A Prong 1: The claim recites the abstract ideas of claims 1, 8 and 15. Step 2A Prong 2 : This judicial exception is not integrated into a practical application because they recite the additional elements: wherein said plurality of filters are initially displayed in a hidden state on said graphical user interface, wherein said metadata regarding said transpilation is retrieved and displayed by said filter engine only in response to a user interaction with said graphical user interface to reveal said hidden state - the steps recited at a high level of generality, and amounts to mere data outputting, which is a form of insignificant extra-solution activity (see MPEP § 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claims are thus directed to the abstract idea. Step 2B : The claims do not include additional elements that amount to significantly more than the judicial exception. The additional elements: wherein one of said plurality of filters is configured to illustrate how said grouped set of quantum logic gates is transpiled to a hardware system - which is a well- understood, routine, conventional activity similar to presenting offers and gathering statistics described in MPEP 2106.05(d)(II). Accordingly, these additional elements do not amount to significantly more than the judicial exception. As such, the claims are ineligible. Dependent claims 4, 11 and 18: Step 2A Prong 1: The claim recites the abstract ideas of claims 1, 8 and 15. Step 2A Prong 2 : This judicial exception is not integrated into a practical application because they recite the additional elements: wherein one of said plurality of filters is configured to provide information regarding one or more quantum logic gates of said grouped set of quantum logic gates not being able to run on a quantum computer - the steps recited at a high level of generality, and amounts to mere data outputting, which is a form of insignificant extra-solution activity (see MPEP § 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claims are thus directed to the abstract idea. Step 2B : The claims do not include additional elements that amount to significantly more than the judicial exception. The additional elements: wherein one of said plurality of filters is configured to provide information regarding one or more quantum logic gates of said grouped set of quantum logic gates not being able to run on a quantum computer - which is a well-understood, routine, conventional activity similar to presenting offers and gathering statistics described in MPEP 2106.05(d)(II). Accordingly, these additional elements do not amount to significantly more than the judicial exception. As such, the claims are ineligible. Dependent claims 5, 12 and 19: Step 2A Prong 1: The claim recites the abstract ideas of claims 1, 8 and 15. Step 2A Prong 2 : This judicial exception is not integrated into a practical application because they recite the additional elements: wherein one of said plurality of filters is configured to provide fidelity information regarding said grouped set of quantum logic gates - the steps recited at a high level of generality, and amounts to mere data outputting, which is a form of insignificant extra-solution activity (see MPEP § 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claims are thus directed to the abstract idea. Step 2B : The claims do not include additional elements that amount to significantly more than the judicial exception. The additional elements: wherein one of said plurality of filters is configured to provide fidelity information regarding said grouped set of quantum logic gates - which is a well-understood, routine, conventional activity similar to presenting offers and gathering statistics described in MPEP 2106.05(d)(II). Accordingly, these additional elements do not amount to significantly more than the judicial exception. As such, the claims are ineligible. Dependent claims 6, 13 and 19: Step 2A Prong 1: The claim recites the abstract ideas of claims 1, 8 and 15. Step 2A Prong 2 : This judicial exception is not integrated into a practical application because they recite the additional elements: wherein one of said plurality of filters is configured to illustrate interchangeable gates within said grouped set of quantum logic gates, wherein one of said plurality of filters is configured to illustrate performance of a quantum logic gate within said grouped set of quantum logic gates when it is transpiled to said quantum circuit - the steps recited at a high level of generality, and amounts to mere data outputting, which is a form of insignificant extra-solution activity (see MPEP § 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claims are thus directed to the abstract idea. Step 2B : The claims do not include additional elements that amount to significantly more than the judicial exception. The additional elements: wherein one of said plurality of filters is configured to illustrate interchangeable gates within said grouped set of quantum logic gates, wherein one of said plurality of filters is configured to illustrate performance of a quantum logic gate within said grouped set of quantum logic gates when it is transpiled to said quantum circuit - which is a well-understood, routine, conventional activity similar to presenting offers and gathering statistics described in MPEP 2106.05(d)(II). Accordingly, these additional elements do not amount to significantly more than the judicial exception. As such, the claims are ineligible. Dependent claims 7 and 14: Step 2A Prong 1: Claims recite: identifying, by said filter engine, a subset of quantum logic gates within said grouped set of quantum logic gates that are incompatible with said specific quantum hardware structure - Under its broadest reasonable interpretation in light of the specification, this limitation encompasses the mental process of evaluating data and selecting data based on judgement, which is observing, evaluating and judging that is practically capable of being performed in the human mind with the assistance of pen and paper . Step 2A Prong 2 : This judicial exception is not integrated into a practical application because they recite the additional elements: displaying a content warning filter indicating that said subset of quantum logic gates cannot be run on said specific quantum hardware structure - the steps recited at a high level of generality, and amounts to mere data outputting, which is a form of insignificant extra-solution activity (see MPEP § 2106.05(g)). Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claims are thus directed to the abstract idea. Step 2B : The claims do not include additional elements that amount to significantly more than the judicial exception. The additional elements: displaying a content warning filter indicating that said subset of quantum logic gates cannot be run on said specific quantum hardware structure - which is a well-understood, routine, conventional activity similar to presenting offers and gathering statistics described in MPEP 2106.05(d)(II). Accordingly, these additional elements do not amount to significantly more than the judicial exception. As such, the claims are ineligible. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-4, 7-11 and 14-18 are rejected under 35 U.S.C. 103 as being unpatentable over Bishop et al. (hereinafter Bishop), US 20190102496 A1, in view of GONCIULEA et al. (hereinafter GONCIULEA), US 20210357229 A1 . Regarding independent claim 1 , Bishop teaches a method for assisting users in creating quantum circuits ([0002] a computer-implemented method for composing a quantum circuit is disclosed. The method includes providing a user interface. The user interface includes a set of interactive elements corresponding to qubits of a physical quantum processor, where each interactive element represents a progression of quantum information over time in a respective qubit) , the method comprising: identifying quantum logic gates of a quantum circuit to be grouped together ([0068] Referring first to FIG. 11, at block 1102 , user input indicative of a request to generate a subroutine may be received at the GUI 304 . Referring now to FIG. 6, the GUI 304 may further include a set of symbols 602 corresponding to subroutines previously generated and stored for re-use. The GUI 304 may also include a selectable element 604 for adding a new subroutine. The user input received at block 1102 may be generated responsive to user selection of the selectable element 604 . Subroutines may include multiple gates combined into a particular grouping that can be applied to any number of qubits in the qubit register; [0069] At block 1104 , further user input may be received at the GUI 304 . This further user input may be indicative of a set of selected symbols from the set of available symbols 506 to include in the subroutine and a number of qubits that the subroutine operates on) based on one or more gate characteristics comprising gate type, gate color, or gate barriers (Fig. 5; [0059] The operations represented by the symbols 506 may further include a symbol representative of a barrier operation that can be used to create a temporal boundary between operations of a quantum circuit. For example, placement of the barrier symbol on the set of interactive elements 502 at a particular temporal node may cause a temporal separation between a first portion of the quantum circuit that includes operations performed prior to the barrier and a second portion of the quantum circuit that includes operations performed after the barrier. This temporal separation prevents concatenation of a first operation in the first portion with a second operation in the second portion during compilation); grouping said identified quantum logic gates into a grouped set of quantum logic gates ([0069] At block 1106 , the subroutine may be generated based on the user input) ; and displaying a plurality of filters, via graphical user interface, in connection with said quantum circuit ([0069] at block 1108 , a new symbol representing the generated subroutine may be added to the set of symbols 602 ) . Bishop does not explicitly teach wherein each of said plurality of filters is configured to display metadata retrieved by a filter engine regarding a transpilation of said grouped set of quantum logic gates to a specific quantum hardware structure. However, in the same field of endeavor, GONCIULEA teaches wherein each of said plurality of filters is configured to display metadata retrieved by a filter engine regarding a transpilation of said grouped set of quantum logic gates to a specific quantum hardware structure (Fig. 5; [0041] In step 525 , the classical computer program may then continue transpiling the quantum circuit, which results in the lowest-level instructions that the quantum computer will accept. In step 530 , the classical computer program may then send the instructions to the quantum computer. In step 535 , the quantum computer may execute the instructions, and in step 540 , the classical computer program may receive the results. In one embodiment, the classical computer program may output the results visually, and may perform analysis). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of transpiling the quantum circuit into a plurality of quantum instructions as suggested in GONCIULEA into Bishop’s system because both of these systems are addressing creating a quantum circuit. This modification would have been motivated by the desire for performance improvements (GONCIULEA, [0034]). Regarding dependent claim 2 , the combination of Bishop and GONCIULEA teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Bishop further teaches wherein one of said plurality of filters is configured to illustrate which gates form said grouped set of quantum logic gates ([0070] At block 1110 , user input may be received at the GUI 304 that is indicative of a selection of the symbol representing the subroutine generated at block 1106 . Responsive to selection of this symbol, an object 610 representing the selected subroutine and spanning all interactive elements 502 may be rendered in the GUI 304 . The object 610 may include a number of markers (e.g., marker 612 ) equaling the number of qubits that the subroutine operates on). Regarding dependent claim 3 , the combination of Bishop and GONCIULEA teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. GONCIULEA teaches wherein said plurality of filters are initially displayed in a hidden state on said graphical user interface, wherein said metadata regarding said transpilation is retrieved and displayed by said filter engine only in response to a user interaction with said graphical user interface to reveal said hidden state (Fig. 5; [0041] In step 525 , the classical computer program may then continue transpiling the quantum circuit, which results in the lowest-level instructions that the quantum computer will accept. In step 530 , the classical computer program may then send the instructions to the quantum computer. In step 535 , the quantum computer may execute the instructions, and in step 540 , the classical computer program may receive the results. In one embodiment, the classical computer program may output the results visually, and may perform analysis; [0061] In the system and method of the invention, a variety of “user interfaces” may be utilized to allow a user to interface with the processing machine or machines that are used to implement the invention. As used herein, a user interface includes any hardware, software, or combination of hardware and software used by the processing machine that allows a user to interact with the processing machine. A user interface may be in the form of a dialogue screen for example. A user interface may also include any of a mouse, touch screen, keyboard, keypad, voice reader, voice recognizer, dialogue screen, menu box, list, checkbox, toggle switch, a pushbutton or any other device that allows a user to receive information regarding the operation of the processing machine as it processes a set of instructions and/or provides the processing machine with information. Accordingly, the user interface is any device that provides communication between a user and a processing machine. The information provided by the user to the processing machine through the user interface may be in the form of a command, a selection of data, or some other input, for example; [0062] As discussed above, a user interface is utilized by the processing machine that performs a set of instructions such that the processing machine processes data for a user. The user interface is typically used by the processing machine for interacting with a user either to convey information or receive information from the user). Regarding dependent claim 4 , the combination of Bishop and GONCIULEA teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. GONCIULEA teaches wherein one of said plurality of filters is configured to provide information regarding one or more quantum logic gates of said grouped set of quantum logic gates not being able to run on a quantum computer (Fig. 5; [0041] In step 535 , the quantum computer may execute the instructions, and in step 540 , the classical computer program may receive the results. In one embodiment, the classical computer program may output the results visually, and may perform analysis). Regarding dependent claim 7 , the combination of Bishop and GONCIULEA teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Bishop further teaches further comprising: identifying, by said filter engine, a subset of quantum logic gates within said grouped set of quantum logic gates that are incompatible with said specific quantum hardware structure and displaying a content warning filter indicating that said subset of quantum logic gates cannot be run on said specific quantum hardware structure ([0028] The GUI for composing quantum circuits in accordance with example embodiments avoids the complexity of the mathematical formulation of quantum circuits involving matrices and/or tensor products by providing a graphical representation of the composed quantum circuit that is easy to visualize and that provides an intuition as to how operations occur over time. A quantum circuit is a representation of how quantum information progresses through time as qubit registers and classical bit registers are operated on by various controls and gate operations. The visual interface disclosed herein enables programming of a quantum processor in a manner that intuitively reflects this progression of quantum information over time. In addition, a visual programming interface as disclosed herein provides immediate feedback to a user regarding what operations are allowed and what operations may not be allowed at various points in time based on what operations have been specified at earlier points in time). Regarding independent claim 8 , it is a product claim that corresponding to the method of claim 1. Therefore, it is rejected for the same reason as claim 1 above. Bishop further teaches a computer program product for assisting users in creating quantum circuits, the computer program product comprising one or more computer readable storage mediums having program code embodied therewith, the program code comprising programming instructions ([0004]; [0107]). Regarding dependent claim 9 , it is a product claim that corresponding to the method of claim 2. Therefore, it is rejected for the same reason as claim 2 above. Regarding dependent claim 10 , it is a product claim that corresponding to the method of claim 3. Therefore, it is rejected for the same reason as claim 3 above. Regarding dependent claim 11 , it is a product claim that corresponding to the method of claim 4. Therefore, it is rejected for the same reason as claim 4 above. Regarding dependent claim 14 , it is a product claim that corresponding to the method of claim 7. Therefore, it is rejected for the same reason as claim 7 above. Regarding independent claim 15 , it is a system claim that corresponding to the method of claim 1. Therefore, it is rejected for the same reason as claim 1 above. Bishop further teaches a system, comprising: a memory for storing a computer program for assisting users in creating quantum circuits; and a processor connected to said memory, wherein said processor is configured to execute program instructions of the computer program ([0003]). Regarding dependent claim 16 , it is a system claim that corresponding to the method of claim 2. Therefore, it is rejected for the same reason as claim 2 above. Regarding dependent claim 17 , it is a system claim that corresponding to the method of claim 3. Therefore, it is rejected for the same reason as claim 3 above. Regarding dependent claim 18 , it is a system claim that corresponding to the method of claim 4. Therefore, it is rejected for the same reason as claim 4 above . 07-21-aia AIA Claim s 5-6, 12-13 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bishop, in view of GONCIULEA as applied in claims 1, 8 and 15, in view of Kasprowicz et al. (hereinafter Kasprowicz), US 20210158425 A1 . Regarding dependent claim 5 , the combination of Bishop and GONCIULEA teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Bishop does not explicitly teach wherein one of said plurality of filters is configured to provide fidelity information regarding said grouped set of quantum logic gates. However, in the same field of endeavor, Kasprowicz teaches wherein one of said plurality of filters is configured to provide fidelity information regarding said grouped set of quantum logic gates (Fig. 4; [0117] a quantum algorithm development kit 114 may include a recommendation button, such as cost/performance estimation/recommendation button 414 . For example, selecting cost/performance estimation/recommendation button 414 may cause a customer to be provided with an estimate of performance of a quantum task/algorithm/circuit being designed in the design space 404 and also estimated cost to execute the task/algorithm/circuit using various quantum hardware providers. In some embodiments, selecting cost/performance estimation/recommendation button 414 may cause a customer to be provided with performance and cost estimates for executing the task/algorithm/circuit being designed using various quantum computing paradigms, types of quantum computers, or quantum computer providers. Additionally, in some embodiments, selecting cost/performance estimation/recommendation button 414 may cause a customer to be provided with a recommendation as to which quantum computing paradigm, quantum computer type, or quantum hardware provider to select to execute the task/algorithm/circuit being designed). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of providing a cost/performance estimation/recommendation button to provide a customer with an estimate of performance of a quantum task/algorithm/circuit being designed in the design space as suggested in Kasprowicz into Bishop and GONCIULEA’s system because both of these systems are addressing development tool interface for defining a quantum circuit. This modification would have been motivated by the desire to performance improvements (Kasprowicz, [0034]). Regarding dependent claim 6 , the combination of Bishop and GONCIULEA teaches all the limitations as set forth in the rejection of claim 1 that is incorporated. Bishop does not explicitly teach wherein one of said plurality of filters is configured to illustrate interchangeable gates within said grouped set of quantum logic gates, wherein one of said plurality of filters is configured to illustrate performance of a quantum logic gate within said grouped set of quantum logic gates when it is transpiled to said quantum circuit. However, in the same field of endeavor, Kasprowicz teaches wherein one of said plurality of filters is configured to illustrate interchangeable gates within said grouped set of quantum logic gates (Fig. 12; [0176] In some embodiments, to perform an optimization, a translation module, at 1202 , identifies one or more sets of gates in a translated version of a quantum circuit that can be replaced by a smaller set of gates having equivalent functionality; [0177] At 1204 , the translation module replaces or combines the identified gates. At 1206 , the translation module may optionally simulate the modified quantum circuit to verify equivalent functionality. At 1208 , the translation module may provide the optimized translated quantum circuit for execution, via a back-end API transport) , wherein one of said plurality of filters is configured to illustrate performance of a quantum logic gate within said grouped set of quantum logic gates when it is transpiled to said quantum circuit ([0117] a quantum algorithm development kit 114 may include a recommendation button, such as cost/performance estimation/recommendation button 414 . For example, selecting cost/performance estimation/recommendation button 414 may cause a customer to be provided with an estimate of performance of a quantum task/algorithm/circuit being designed in the design space 404 and also estimated cost to execute the task/algorithm/circuit using various quantum hardware providers. In some embodiments, selecting cost/performance estimation/recommendation button 414 may cause a customer to be provided with performance and cost estimates for executing the task/algorithm/circuit being designed using various quantum computing paradigms, types of quantum computers, or quantum computer providers). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of providing a cost/performance estimation/recommendation button to provide a customer with an estimate of performance of a quantum task/algorithm/circuit being designed in the design space as suggested in Kasprowicz into Bishop and GONCIULEA’s system because both of these systems are addressing development tool interface for defining a quantum circuit. This modification would have been motivated by the desire for performance improvements (Kasprowicz, [0034]). Regarding dependent claim 12 , it is a product claim that corresponding to the method of claim 5. Therefore, it is rejected for the same reason as claim 5 above. Regarding dependent claim 13 , it is a product claim that corresponding to the method of claim 6. Therefore, it is rejected for the same reason as claim 6 above. Regarding dependent claim 19 , it is a system claim that corresponding to the method of claim 5. Therefore, it is rejected for the same reason as claim 5 above. Regarding dependent claim 20 , it is a system claim that corresponding to the method of claim 6. Therefore, it is rejected for the same reason as claim 6 above . Response to Arguments Applicant's arguments filed 03/09/2026 have been fully considered. Each of applicant’s remarks is set forth, followed by examiner’s response. (1) Regarding claim rejections under 35 U.S.C. § 101, Applicant alleges "identifying quantum logic gates of a quantum circuit to be grouped together based on one or more gate characteristics comprising gate type, gate color, or gate barriers; grouping said identified quantum logic gates into a grouped set of quantum logic gates; and displaying a plurality of filters, via graphical user interface, in connection with said quantum circuit, wherein each of said plurality of filters is configured to display metadata retrieved by a filter engine regarding a transpilation of said grouped set of quantum logic gates to a specific quantum hardware structure," as recited in claim 1 and similarly in claims 8 and 15, identifying quantum logic gates of a quantum circuit to be grouped together based on one or more gate characteristics comprising gate type, gate color, or gate barriers; and displaying a plurality of filters, via graphical user interface, in connection with the quantum circuit, where each of the plurality of filters is configured to display metadata retrieved by a filter engine regarding a transpilation of the grouped set of quantum logic gates to a specific quantum hardware structure, cannot practically be performed in the human mind, including using a pen and paper. Hence, such claim limitations do not recite the judicial exception (abstract idea) of a mental process. As to point (1), Examiner respectfully disagrees. Under the broadest reasonable interpretation, the terms of the claim are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP 2111. Claims 1, 8 and 15 recite “identifying quantum logic gates of a quantum circuit to be grouped together based on one or more gate characteristics comprising gate type, gate color, or gate barriers; grouping said identified quantum logic gates into a grouped set of quantum logic gates”. The term “quantum logic gates” and “a quantum circuit” are recognized as having its plain meaning of graphical elements in graphical quantum programming tools as disclosed in the specification. The claimed identifying and grouping steps encompass mental choices or evaluations which may be practically performed in the human mind using observation, evaluation, judgment, and opinion. For example, the claimed identifying quantum logic gates of a quantum circuit to be grouped together based on one or more gate characteristics comprising gate type, gate color, or gate barriers; grouping said identified quantum logic gates into a grouped set of quantum logic gates encompasses observing quantum logic gates, performing an evaluation based on gate type, gate color, or gate barriers, judgment, and opinion to make a determination about grouping. Under its broadest reasonable interpretation when read in light of the specification, the “identifying” and “grouping” encompass mental processes practically performed in the human mind by observation, evaluation, judgment, and opinion. See MPEP 2106.04(a)(2), subsection III. (2) Applicant further alleges that Applicant's claimed invention, such as claimed in claims 1, 8 and 15, improves the technology or technical field of graphical quantum programming tools by citing [0018]-[0024], [0110], [0142]-[0143] of the specification. As to point (2), Examiner respectfully disagrees. One way to determine integration into a practical application is when the claimed invention improves the functioning of a computer or improves another technology or technical field. To evaluate an improvement to a computer or technical field, the specification must set forth an improvement in technology and the claim itself must reflect the disclosed improvement. See MPEP 2106.04(d)(1) and 2106.05(a). The consideration of whether the claim as a whole includes an improvement to a computer or to a technological field requires an evaluation of the specification and the claim to ensure that a technical explanation of the asserted improvement is present in the specification, and that the claim reflects the asserted improvement. While the disclosure states that “the principles of the present disclosure improve the technology or technical field involving graphical quantum programming tools”, there is no improvement to the functioning of a computer nor to any other technology. At best, the claimed combination amounts to an improvement to the abstract idea rather than to any technology. See MPEP 2106.05(a). Any purported improvements are provided by the judicial exception alone, i.e. mental process, thus the claim as a whole does not integrate the judicial exception into a practical application nor provide significantly more than the judicial exception. Thus, the claims are patent ineligible and are rejected under 35 U.S.C. 101 as detailed in the rejections set forth above. (3) Applicant’s prior art arguments with respect to the pending claims have been considered but they are moot in view of the new ground(s) of rejections presented above. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action . Shi et al. (US 20230099621 A1) discloses providing quantum computing services to customers and enabling customers to seamlessly use one or more quantum computing technologies. It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)). Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY P HOANG whose telephone number is (469)295-9134. The examiner can normally be reached M-TH 8:30-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JENNIFER WELCH can be reached at 571-272-7212. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMY P HOANG/ Examiner, Art Unit 2143 /JENNIFER N WELCH/ Supervisory Patent Examiner, Art Unit 2143 Application/Control Number: 17/982,391 Page 2 Art Unit: 2143 Application/Control Number: 17/982,391 Page 3 Art Unit: 2143 Application/Control Number: 17/982,391 Page 4 Art Unit: 2143 Application/Control Number: 17/982,391 Page 5 Art Unit: 2143 Application/Control Number: 17/982,391 Page 6 Art Unit: 2143 Application/Control Number: 17/982,391 Page 7 Art Unit: 2143 Application/Control Number: 17/982,391 Page 8 Art Unit: 2143 Application/Control Number: 17/982,391 Page 9 Art Unit: 2143 Application/Control Number: 17/982,391 Page 10 Art Unit: 2143 Application/Control Number: 17/982,391 Page 11 Art Unit: 2143 Application/Control Number: 17/982,391 Page 12 Art Unit: 2143 Application/Control Number: 17/982,391 Page 13 Art Unit: 2143 Application/Control Number: 17/982,391 Page 14 Art Unit: 2143 Application/Control Number: 17/982,391 Page 15 Art Unit: 2143 Application/Control Number: 17/982,391 Page 16 Art Unit: 2143 Application/Control Number: 17/982,391 Page 17 Art Unit: 2143 Application/Control Number: 17/982,391 Page 18 Art Unit: 2143 Application/Control Number: 17/982,391 Page 19 Art Unit: 2143 Application/Control Number: 17/982,391 Page 20 Art Unit: 2143 Application/Control Number: 17/982,391 Page 21 Art Unit: 2143 Application/Control Number: 17/982,391 Page 22 Art Unit: 2143 Application/Control Number: 17/982,391 Page 23 Art Unit: 2143 Application/Control Number: 17/982,391 Page 24 Art Unit: 2143 Application/Control Number: 17/982,391 Page 25 Art Unit: 2143
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