DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed on 03/23/2026 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yamaguchi (USPN 2001/0000218).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al (USPN 2016/0156178) in view of Yamaguchi (USPN 2001/0000218).
Regarding claim 1, Yamamoto discloses a radio frequency device (see figures 1-2), comprising: a first radio frequency (RF) switch (Fswa) coupled in series to a first RF port (P1) and coupled in parallel to an RF common (RFC) port (Com); and an electrostatic discharge (ESD) dissipation switch (ESDc, see figure 11) coupled to the RF common port (RFC) (Com) and comprising a switch field effect transistor (FET) (such as FET switch Fa, see par. 0056).
Yamamoto does not explicitly disclose the FET as claimed.
Yamaguchi discloses an ESD protection FET structure (15B, shown in figure 10, configured to be as an ESD protection transistor, see par. 0108) comprises including a drain region (6C) in an active layer (an active layer 3) on an insulator layer (such as SOI substructure 1-3, see par. 0105), a drain silicide region (a drain silicide region of a silicide protection layer 14 formed on the drain region 6C) in the drain region (6C), and a gate (a gate electrode 5) on the active layer (3) on the insulator layer (the SOI substrate 1-3), and having a first side wall spacer (a first side wall spacer 11) and a second side wall spacer (a second side wall spacer 11), opposite the first side wall spacer, and a symmetric silicide area block (SAB) (such as a symmetric silicide area blocking formed on the drain region 6C and symmetrically with respect to the source region 7C, see figure 10) on the first sidewall spacer (the first side wall 11) and the second sidewall spacer (the second wall 11), the symmetric SAB on a gate surface (a surface of the gate 5) and extending cross the gate surface between the first side wall spacer (11) and the second side wall spacer (11), opposite the active layer of the substrate (see par. 0110 and figure 10).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the ESD protection FET of Yamamoto to incorporate an ESD protection FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
Regarding claim 2, Yamamoto does not explicitly disclose the SAB as claimed.
Yamaguchi discloses an ESD protection FET structure (15B, see figure 10) comprises the silicide area block (the covered regions of the silicide protection layer 14 on the side walls 11 and the gate electrode 5) on a first surface region (a first surface region of the SOI layer 3) of the active layer (3) on the insulator layer (the SOI substrate 1-3), proximate the first sidewall spacer (the first sidewall spacer 11), and on a second surface region (a second surface region 2) of the active layer (3) on the insulator layer (the SOI substrate 1-3), proximate the second sidewall spacer (11).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains to have modified the ESD protection FET of Yamamoto to incorporate an ESD protection FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
Regarding claims 3, 4, Yamamoto does not explicitly disclose the SAB as claimed.
Yamaguchi discloses an ESD protection FET structure (15B, see figure 10) comprises the FET switch (the clamping transistor shown in figure 1, see par. 0118) comprises
a source region (a source region 7C) in the active layer (3) on the insulator layer (1-3) (see par. 0105); and a source silicide region (a silicide blocking region of the silicide protection layer 14 disposed on the source region 7C, see figure 10) coupled to the source region (7C), in which the source silicide region is separated from the first sidewall spacer(11) by a portion of the symmetric SAB on a surface of the insulator layer (1-3), a drain region (a drain region 140 sub 1) in the active layer of the substrate (105); and the drain silicide region (the second silicide blocking region disposed on the drain region 6C) is separated from the second sidewall spacer (11) by a portion of the symmetric SAB on the insulator layer (1-3) (see par. 0108, 0110).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains to have modified the ESD protection FET of Yamamoto to incorporate an ESD protection FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
Regarding claim 5, Yamamoto discloses a first shunt ESD dissipation switch (Fswc) coupled in a shunt connection between the first RF port (P1) and the first RF switch (Fswa).
Regarding claim 6, Yamamoto discloses a second RF switch (Fswb) coupled in series to the first RF switch and a second RF port (P2), and coupled in parallel to the RFC port (Com).
Regarding claim 7, Yamamoto discloses a second shunt ESD dissipation switch (Fswd) coupled in a shunt connection between the second RF port (P2) and the second RF switch (Fswb).
Regarding claims 8, 18, Yamamoto and Uchida disclose coupling a second shunt ESD dissipation switch (Fswd) in a shunt connection between the second RF port (P2) and the second RF switch (Fswb) in which the second RF port (the port P2) comprises an ESD pulse port (such as an ESD pulse entered the port P2 and protected by an ESD2) (see figures 2, and par. 0038). .
Regarding claims 9, 19, Yamamoto discloses the RF device is integrated in an RF front end module (see figure 16, see par. 0004).
Regarding claims 10, 20, Yamamoto discloses incorporating the RFFE module in at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, a mobile phone (see figure 16, par. 0004), and a portable computer.
Regarding claim 11, Yamamoto discloses a method for constructing a radio frequency (RF) device (see figures 1, 2,11) having a RF electrostatic discharge (ESD) dissipation switch (ESDc, see the details of the ESDc shown in figure 11, see par. 0056), comprising: forming a switch field effect transistor (FET) (a FET switch Fa of the ESDc).
Yamamoto does not explicitly disclose the steps of depositing, patterning, forming as claimed.
Yamaguchi discloses a method for forming a switching structure (an ESD protection FET structure 15B shown in figure 10, wherein the first switch (15B) is configured to function as An ESD protection transistor, see par. 0108) comprises
forming a switch field effect transistor (a switching transistor structure 15B, see figure 10) including a gate (a gate electrode 5) on an active layer (a SOI layer 3) on an insulator layer (a SOI substrate 1-3),
depositing an oxide layer (such as cobalt silicide film or titanium silicide film) on the switch FET (the first transistor 15B) and on a surface of the active layer (the SOI layer 3) on the insulator layer (the SOI substrate structure 1-3) (see par. 0109);
patterning the oxide layer (such as by creating patterns using the cobalt silicide film or the titanium silicide film, by using a silicide formation process, see par. 0092, 0101) to expose portions (such as exposed drain and source regions 6C, 7C) of the active layer (3) on the insulator layer (1-3) to form a symmetric silicide area block (SAB) (a symmetric silicide area block formed by silicide portions on the drain 6C and the source 7C) on the gate surface of the gate (a surface of the gate electrode 5), on exposed portions of the active layer (3) on the insulator layer (1-3) proximate sidewalls of the gate (the sidewalls 11), and extending across the gate surface opposite the active layer on the insulator layer (1-3) (see figure 10);
forming a drain silicide region (a drain silicide region of the silicide protection layer 14 formed on a drain region 6C) on exposed portions of the active layer (3) on the insulator layer (1-3), adjacent to the symmetric SAB (the symmetric silicide portions of the silicide protection layer 14 shown in figure 10); and
forming a drain contact (such as silicide layer 13) to the drain silicide region (the drain silicide region of the silicide protection layer 14 on the drain region 6C) (see figure 10).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the method of forming the ESD protection FET of Yamamoto to incorporate a method of forming an ESD protection FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
the switching device so that performing more securely in the an ESD stress environment.
Regarding claim 12, Yamamoto does not disclose the SAB as claimed.
Yamaguchi discloses the method for forming a switching structure (a FET structure of a first switch shown in figure 10, wherein the first switch is configured to function as an ESD clamping transistor, see par. 0108) comprises the symmetric SAB (the symmetric silicide area blocking formed on the drain region 6C and symmetrically with silicide region on the source region 7C) is on a first surface region (a source region 7C) of the active layer (3) on the insulator layer (1-3) proximate a first sidewall spacer (11), and on a second surface region (a drain region 6C) of the active layer on the insulator layer (1-3), proximate a second sidewall spacer (11) (see par. 0110).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the method of forming an ESD FET of Yamamoto to incorporate a method of forming an ESD FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
Regarding claim 13, Yamamoto does not disclose the switch FET as claimed.
Yamaguchi discloses the method for forming a switching structure (a FET structure of a first switch 15B shown in figure 10, wherein the first switch is configured to function as a clamping transistor, see par. 0108) comprises
forming a source region (a source region 7C) in the active layer (3) on the insulator layer (1-3), in which a source silicide region (a silicide source region form on the source region 7C) is coupled to the source region (7C) and separated from a first sidewall spacer (11) of the gate (the gate electrode 5) by a portion of the symmetric SAB on a surface of the active layer on the insulator layer; and
forming a source contact (a silicide contact layer 13) to the source silicide region (see figure 10).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the method of forming an ESD FET of Yamamoto to incorporate a method of forming an ESD FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
Regarding claim 14, Yamamoto does not disclose the switch FET as claimed.
Yamaguchi discloses the method for forming a switching structure (a FET structure of a first switch 15B shown in figure 10, wherein the first switch is configured to function as a clamping transistor, see par. 0108) comprises
forming a drain region (a drain region 6C) in the active layer (3) on the insulator layer (1-3), in which a drain silicide region (the silicide region formed on the drain region 6C) is coupled to the drain region (6C) and separated from a second sidewall spacer (11) of the gate (5) by a portion of the symmetric SAB on a surface of the active layer on the insulator layer (see figure 10).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the method of forming an ESD FET of Yamamoto to incorporate a method of forming an ESD FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
Regarding claim 15, Yamamoto coupling a first radio frequency (RF) switch (Fswa) in series to a first RF port (P1) and in parallel to an RF common (RFC) port (Com); and coupling the RFESD dissipation switch (ESDc) to the RFC port (Com)(see figure 2).
Yamamoto does not explicitly disclose the symmetric FET as claimed.
Yamaguchi discloses the method for forming a switching structure (a FET structure of a first switch 15B shown in figure 10, wherein the first switch is configured to function as a clamping transistor, see par. 0108) comprises a symmetric FET switch structure (a FET structure 15B shown in figure 10).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the method of forming an ESD FET of Yamamoto to incorporate a method of forming a symmetric ESD FET structure as disclosed by Yamaguchi in order to improve an ESD protection.
Regarding claim 16, Yamamoto discloses coupling a first shunt ESD dissipation switch (Fswc) in a shunt connection between the first RF port (P1) and the first RF switch.
Regarding claim 17, Yamamoto discloses coupling a second RF switch (Fswb) in series to the first RF switch and a second RF port (P2), and in parallel to the RFC port (Com).
Conclusion
3. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY NGUYEN/ Primary Examiner, Art Unit 2838
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