DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/15/2024 was filed after the mailing date of the non-final action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 contains the limitation “wherein the first portion, the second portion and the third portion are electrically connected, lie in a single plane, are non-layered and integrally formed for transmission of an electrical signal across the electrical component.”
It is unclear what is meant by the three portions being non-layered since fig.7 of the instant application shows otherwise and whether the three portions are non-layered from one another from a side view with different lengths or if the applicant means the three portions are non-layered as in not overlapping each other and instead side by side to each other.
For the purpose of examination, the claim will be interpreted as non-layered meaning the three portions are not overlapping each other and instead side by side to each other.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 14-18 are rejected under 35 U.S.C. 102(a)(1) and 102 (a) (2) as being anticipated by Mazellier (US 2011/0156055 A1).
Re claim 14: Mazellier teaches (fig.6) An electrical component (150) comprising:
a) at least a first portion (112) defined as an insulator (passivation layer, par.98);
b) at least a second portion (122) defined as a conductor (electrically conductive material par.107);
c) at least a third portion (108-104) defined as a semiconductor (par.83);
d) wherein the first portion (118), the second portion (122) and the third portion (104) are electrically connected, lie in a single plane (XY plane, par 99), are non-layered (components in plane XY do not overlap and are side by side, par. 34) and integrally formed for transmission (par.42) of an electrical signal across the electrical component (150).
Re claim 15: Mazellier teaches the electrical component according to claim 14 wherein the first portion (112), the second portion (122) and the third portion (108-104) are adjacent each other in the single plane (XY plane, par.99).
Re claim 16: Mazellier teaches the electrical component according to claim 14 wherein the first portion (112), the second portion (122) and the third portion (108-104) may be adjacent each other in the single plane (XY plane, par.99).
Re claim 17: Mazellier teaches the electrical component according to claim 14 wherein a metallic compound (par.107) is present in the second portion (122).
Re claim 18: Mazellier teaches the electrical component according to claim 14 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination (par. 96, CMOS sensor circuit) therein.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-6 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-14 of U.S. Patent No. US 10,700,165 B2.
.
Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated by the reference claims as illustrated below and as directed to Figures 2-7 of both applications:
Instant Application
US 10,700,165 B2
1. An electrical component comprising:
a) at least a first portion formed from and composed of diamond, the first portion primarily defined as an insulator;
b) at least a second portion formed from and composed of doped diamond, the second portion primarily defined as a conductor; and,
c) wherein the first portion and the second portion are electrically connected, lie in a single plane and are integrally formed for transmission of electricity across the electrical component, wherein the first portion and the second portion are non- layered.
9. An electrical component comprising:
a) at least a first portion formed from and composed of diamond, the first portion primarily defined as an insulator;
b) at least a second portion formed from and composed of doped diamond, the second portion primarily defined as a conductor; and,
c) wherein the first portion and the second portion are electrically connected, lie in a single plane and are integrally formed by laser ablation for transmission of electricity across the electrical component, wherein the first portion and the second portion are non-layered.
2. The electrical component according to claim 1 wherein the electrical component is a resistor.
10. The electrical component according to claim 9 wherein the electrical component is a resistor.
3. The electrical component according to claim 1 wherein a third portion is formed from and composed of a doped diamond, the third portion primarily defined as a semiconductor and wherein the first portion, the second portion and the third portion are non-layered, lie in a single plane, are integrally formed and electrically connected for transmission of electricity across the electrical component.
4. The electrical component according to 1 wherein a fourth portion is formed from and composed of metal, the fourth portion primarily defined as a conductor, wherein the fourth portion is electrically connected and integrally formed with the first, second and third portions, lies in the same plane as the first, second and third portions, and is non-layered in relation to the first, second and third portions for transmission of electricity across the electrical component.
11. The electrical component according to claim 9 herein a third portion is formed from and composed of a doped diamond, the third portion primarily defined as a semiconductor and wherein the first portion, the second portion and the third portion are non-layered, lie in a single plane, are integrally formed and electrically connected for transmission of electricity across the electrical component.
12. The electrical component according to 9 wherein a fourth portion is formed from and composed of metal, the fourth portion primarily defined as a conductor, wherein the fourth portion is electrically connected and integrally formed with the first, second and third portions, lies in the same plane as the first, second and third portions, and is non-layered in relation to the first, second and third portions for transmission of electricity across the electrical component.
5. The electrical component according to claim 1 formed as a resistor, a transistor, capacitor, an inductor or a diode or combination therein.
13. The electrical component according to claim 9 formed as a resistor, a transistor, capacitor, an inductor or a diode or combination therein.
6. The electrical component according to claim 1 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein and a plurality of the electrical components are further assembled to form an integrated circuit.
14. The electrical component according to claim 9 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein and a plurality of the electrical components are further assembled to form an integrated circuit.
Claims 7-13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1-7 of U.S. Patent No. US 11,495,664 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated by the reference claims as illustrated below and as directed to Figures 2-7 of both applications:
Instant Application
US 11,495,664 B2
7. A confined pulsed laser deposition method for production of an electrical component comprising:
a) placing an ablative coating between a transparent confinement layer and a backing plane, wherein the ablative coating is composed of graphite particles and a dopant material;
b) directing a laser beam through the transparent confinement layer to irradiate and ablate the ablative coating;
c) vaporizing the ablative coating into an oxidized plasma gas using the laser beam;
d) confining the vaporized ablative coating using the confinement layer to generate laser induced pressure between the confinement layer and the backing plane; and,
e) synthesizing a metaphase from the ablative coating using the laser induced pressure between the confinement layer and the backing plane forming an electrical component therein, the electrical component further comprising:
i. at least a first portion formed from and composed of diamond, the first portion primarily defined as an insulator;
ii. at least a second portion formed from and composed of graphite, the second portion primarily defined as a conductor;
iii. at least a third portion formed from and composed of a doped diamond, the third portion primarily defined as a semiconductor;
iv. wherein the first portion, the second portion and the third portion are electrically connected, lie in a single plane and are integrally formed for electricity transmission across the electrical component.
1. A confined pulsed laser deposition method for production of an electrical component comprising:
a) placing an ablative coating between a transparent confinement layer and a backing plane, wherein the ablative coating is composed of graphite particles and a dopant material;
b) directing a laser beam through the transparent confinement layer to irradiate and ablate the ablative coating at generally ambient temperature and pressure;
c) vaporizing the ablative coating into an oxidized plasma gas using the laser beam;
d) confining the vaporized ablative coating using the confinement layer to generate laser induced pressure between the confinement layer and the backing plane; and,
e) synthesizing a metaphase from the ablative coating using the laser induced pressure between the confinement layer and the backing plane forming an electrical component therein, the electrical component further comprising:
i. at least a first portion formed from and composed of diamond, the first portion primarily defined as an insulator;
ii. at least a second portion formed from and composed of graphite, the second portion primarily defined as a conductor;
iii. at least a third portion formed from and composed of a doped diamond, the third portion primarily defined as a semiconductor;
iv. wherein the first portion, the second portion and the third portion are electrically connected, lie in a single plane and integrally formed for transmission of an electrical signal across the electrical component.
8. The confined pulsed laser deposition method for production of an electrical component according to claim 7 wherein a metallic compound is present in the second portion.
2. The confined pulsed laser deposition method for production of an electrical component according to claim 1 wherein a metallic compound is present in the second portion.
9. The confined pulsed laser deposition method for production of an electrical component according to claim 7 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein.
3. The confined pulsed laser deposition method for production of an electrical component according to claim 1 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein.
10. The confined pulsed laser deposition method for production of an electrical component according to claim 8 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein.
4. The confined pulsed laser deposition method for production of an electrical component according to claim 2 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein.
11. The confined pulsed laser deposition method for production of an electrical component according to claim 7 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein and a plurality of the electrical components are further assembled to form an integrated circuit.
5. The confined pulsed laser deposition method for production of an electrical component according to claim 1 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein and a plurality of the electrical components are further assembled to form an integrated circuit.
12. The confined pulsed laser deposition method for production of an electrical component according to claim 7, wherein the ablative coating includes metal.
6. The confined pulsed laser deposition method for production of an electrical component according to claim 1, wherein the ablative coating includes metal.
13. The confined pulsed laser deposition method for production of an electrical component according to claim 7, wherein the dopant material is selected from the selected from the group comprising: boron, aluminium, nitrogen, gallium, indium, phosphorus, phosphine gas, arsenic, antimony, bismuth, lithium, germanium, silicon, xenon, gold, platinum, gallium arsenide, tellurium, sulphur, tin, zinc, chromium, gallium phosphide, magnesium, cadmium telluride, chlorine, sodium, cadmium sulfide, iodine, fluorine, each acting alone or in combination with any of the preceding elements, in any formulation, to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced.
7. The confined pulsed laser deposition method for production of an electrical component according to claim 1, wherein the dopant material is selected from the selected from the group comprising: boron, aluminium, nitrogen, gallium, indium, phosphorus, phosphine gas, arsenic, antimony, bismuth, lithium, germanium, silicon, xenon, gold, platinum, gallium arsenide, tellurium, sulphur, tin, zinc, chromium, gallium phosphide, magnesium, cadmium telluride, chlorine, sodium, cadmium sulfide, iodine, fluorine, each acting alone or in combination with any of the preceding elements, in any formulation, to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced.
Claim 14-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3 and 5 of U.S. Patent No. US 10,700,165 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are anticipated by the reference claims as illustrated below and as directed to Figures 2-7 of both applications:
Instant Application
US 10,700,165 B2.
14. An electrical component comprising:
a) at least a first portion defined as an insulator;
b) at least a second portion defined as a conductor;
c) at least a third portion defined as a semiconductor;
d) wherein the first portion, the second portion and the third portion are electrically connected, lie in a single plane, are non-layered and integrally formed for transmission of an electrical signal across the electrical component.
1. An electrical component comprising:
a. at least a first portion formed from and composed of diamond, the first portion primarily defined as an insulator;
b. at least a second portion formed from and composed of graphite, the second portion primarily defined as a conductor;
c. at least a third portion formed from and composed of a doped diamond, the third portion primarily defined as a semiconductor;
d. wherein the first portion, the second portion and the third portion are electrically connected, lie in a single plane and are integrally formed by laser ablation for transmission of an electrical signal across the electrical component, wherein the first portion, the second portion and the third portion are non-layered.
15. The electrical component according to claim 14 wherein the first portion, the second portion and the third portion are adjacent each other in the single plane.
2. The electrical component according to claim 1 wherein the first portion, the second portion and the third portion are adjacent each other in the single plane.
16.The electrical component according to claim 14 wherein the first portion, the second portion and the third portion may be adjacent each other in the single plane.
2. The electrical component according to claim 1 wherein the first portion, the second portion and the third portion are adjacent each other in the single plane.
17. The electrical component according to claim 14 wherein a metallic compound is present in the second portion.
3. The electrical component according to claim 1 wherein a metallic compound is present in the second portion.
18. The electrical component according to claim 14 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein.
5. The electrical component according to claim 1 formed as a resistor, a transistor, capacitor, inverter, an inductor or a diode or combination therein.
Allowable Subject Matter
Claims 1-13 are otherwise patentable over prior art under 35 U.S.C. 102 and 103, and would be in condition for allowance provided that the applicant filed a terminal disclaimer to overcome the nonstatutory double patenting rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICKY VERDES whose telephone number is (703)756-1401. The examiner can normally be reached Monday - Friday 07:30 - 03:30 PM.
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/RICKY VERDES/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898