DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 11, 20, 22, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Orita et al PN 2007/0239972 in view of Kates et al PN 2004/0268172.
In regards to claims 1, 20: Orita et al teaches a system comprising: two or more processor circuitry components (multiple processors [0025] “The node 202A includes multiple processors 204A, 204B, . . . , 204N, collectively referred to as the processors 204”) and a power management circuitry (ACPI [0006] “Two such examples are the advanced configuration and power interface (ACPI) power management (PM) timer counter, and the high-precision event timer (HPET) counter”) comprising timestamp generator circuitry (timer counter [0006] “ There may be one such counter within a given system, so there is no issue as to counter synchronization as there is with the internal timestamp counters of multiple processors”) , wherein the timestamp generator circuitry is to generate timestamp values based on a single clock source (claim 12: “wherein the external counter comprises a phase-locked loop (PLL) clock”) and provide generated timestamp values to the two or more processor circuitry components ([0001] “The present invention relates generally to timestamp counters, and more particularly, to processing internal timestamp counter instructions in reference to an external counter instead”), wherein the two or more processor circuitry components share timestamp values ([0003] “Application programs running on such multiple-node systems may presume that, regardless of which processor is currently executing a given program, the timestamp counter value will be the same. That is, it may be presumed that the timestamp counters of all the processors over all the nodes are synchronized with one another”). While Orita et al teaches the power management providing the timestamp counter value to all processors so that they all have the same timestamps, Orita et al never mentions generating performance data associate with the timestamp. Kates et al teaches ([0004] “Timestamps may be associated with performance information as it is written to a trace buffer or to a trace file, and the timestamps assist in an analysis of the performance information. A timestamp data structure or record may comprise multiple items of information, but each timestamp may be assumed to contain a clock value that is based on one or more processor clocks within the data processing system”). Kates et al provides a reason one would want to share timestamps ([0006] “If the clock values in the timestamps are based on processor clocks that are significantly askew, then any correlation based on the timestamps will be inaccurate, thereby causing unpredictable analytical results”) but does not mention shared timestamps. It would have been obvious to use Orita et al’s shared timestamps to perform performance monitoring because this would have allowed for correlating trace information from multiple processors ([0006] “For example, a performance analysis application may attempt to correlate trace information from multiple processors through the use of timestamps”).
In regards to claims 2, 22: Orita et al teaches CPUs [0002].
In regards to claim 3: Orita et al teaches event timer [0006]. Kates et al teaches logging events [0084].
In regards to claims 11, 24: Orita et al teaches (claim 12: “wherein the external counter comprises a phase-locked loop (PLL) clock”).
Claim(s) 4, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Orita et al PN 2007/0239972 in view of Kates et al PN 2004/0268172 as applied to claim 1 above, and further in view of Lakshminarayanan et al PN 10,635,431.
In regards to claims 4, 21: Orita et al teaches the processors all having the same timestamp. While it would be logical that all sub-components would have the same timestamps, Orita et al never expressly mentions subcomponents. Lakshminarayanan et al expressly mentions (“In FIG. 5A, working source code 112 has a metadata artifact component 524, which is comprised of subcomponents 528 that share a timestamp 526”). It would be obvious to have all subcomponents share the same timestamp because this would have synchronized the data for all parts of the system.
Claim(s) 5-6, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Orita et al PN 2007/0239972 in view of Kates et al PN 2004/0268172 as applied to claim 1 above, and further in view of Han et al PN 2013/00061077.
In regards to claims 5, 23: Orita et al teaches the processors in ([0005] “various power-conservation modes”) but does not teach subcomponents in independent power states. Han et al teaches (claim 1: “a power management unit (PMU) of a system on a chip (SoC) on a sideband channel coupled between the first subsystem and the PMU, the SoC further including a second subsystem heterogeneous to the first subsystem and controllable to be in a different power state than the first subsystem”). It would have been obvious to allow independent power states of the subsystems/subcomponents because this would have allowed greater granularity in power control.
In regards to claim 6: Han et al teaches the processor being a (SOC).
Claim(s) 7-9, 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Orita et al PN 2007/0239972 in view of Kates et al PN 2004/0268172 as applied to claim 1 above, and further in view of Baugh PN 2022/0300418.
In regards to claims 7-9, 25: Orita et al does not teach the physical structure of the processor system whether it is a tile, package, or cluster. Baugh teaches a computer system that may be include tile(s) ([0027] “FIG. 1 depicts an example compute tile architecture”, “ the compute unit 100 is a hardware (HW) accelerator, or a cluster or pool of HW accelerators”, “In other example implementations, the compute unit 100 can be a multiprocessor system, a multi-chip package (MCP)”). It would have been obvious to have the system components be in any of the formats of tiles, clusters, packages because this would have prevented limiting the construction format.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Orita et al PN 2007/0239972 in view of Kates et al PN 2004/0268172 as applied to claim 1 above, and further in view of Lee et al PN 2012/0072743.
In regards to claim 10: Orita et al teaches a power management circuitry and processors but never mentions the operation of the power management circuitry. Lee et al teaches ([0004] “The power management circuit reduces power consumption of the mobile SoC by using a method of stopping an operation of a circuit installed in the mobile SoC or blocking power provided to the mobile SoC. However, because power is always provided to the power management circuit, power consumption of the power management circuit increases when the power management circuit has a complex structure”). It would have been obvious to include the power management circuitry in an always-on domain because this is how power management circuitry are routinely operated.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Orita et al PN 2007/0239972 in view of Kates et al PN 2004/0268172 as applied to claim 1 above, and further in view of Smith et al PN 4,239,982.
In regards to claim 12: Orita et al only teaches one clock. Smith et al teaches (Column 1 line 12 et seq. “Fault-tolerant clock systems using redundant clock sources have been available for providing timing signals in the face of the failure of one or more of the individual clock sources therein”). It would have been obvious to have a redundant/backup clock because this would have allowed fault tolerance in the clock.
Allowable Subject Matter
Claim 13-19 are allowed.
The following is an examiner’s statement of reasons for allowance: Multiple references were found including a power management unit including a timestamp such as Sauvage et al PN 8,817,000 (“A power management application running on the computer may timestamp and store the power-related data for later retrieval”), Imamura PN 2014/0304496 ([0028] “Also, at the time of a global reset, the power management IC 108 initializes the date and time information stored in the register and requests a reset to the RTC 1081”). Srinivasan et al PN 2019/0384348 ([0033] “For example, power management circuit 110 may set up a timestamp counter (TSC) to run at the target base clock frequency value”). Multiple references were also found teaching a power management unit powered while other components are powered off. Such as Ono PN 2006/0129251 ([0069] “electric power is always supplied to the power management circuit 10 alone”), Lee et al PN 2012/0072743 ([0004] “However, because power is always provided to the power management circuit, power consumption of the power management circuit increases when the power management circuit has a complex structure”). References related to performance monitoring with timestamps such as Chiaramonte et al PN 2007/0079308 teaches ([0054] “In certain embodiments, hardware element affinity for one or more virtual machines 200 may be adjusted based on the performance of one or more than one virtual machine”). The claim language however states “performance data of two or more circuitries with timestamp values generated by a power management unit that is powered-on regardless of whether the two or more circuitries are powered off." The examiner found no references that taught generating timestamps of performance of a circuit that is powered off. The examiner would assume the performance of a circuit that is powered off would be 0. While it would be obvious to generate performance data with timestamps while a non-related circuit is powered off. The examiner found no motivation to generate performance data with timestamps for a circuit that is powered off.
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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/Paul R. MYERS/Primary Examiner, Art Unit 2176