Prosecution Insights
Last updated: July 17, 2026
Application No. 17/984,183

CURRENT EQUALIZATION AND RECONFIGURABLE DOUBLE CONTROL LOOP FOR VOLTAGE REGULATORS

Non-Final OA §103
Filed
Nov 09, 2022
Examiner
HARRINGTON, CHERI L.
Art Unit
2176
Tech Center
2100 — Computer Architecture & Software
Assignee
Intel Corporation
OA Round
1 (Non-Final)
69%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 69% — above average
69%
Career Allowance Rate
219 granted / 318 resolved
+13.9% vs TC avg
Strong +27% interview lift
Without
With
+27.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
18 currently pending
Career history
340
Total Applications
across all art units

Statute-Specific Performance

§101
1.9%
-38.1% vs TC avg
§103
79.1%
+39.1% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
12.4%
-27.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 318 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-10 in the reply filed on 05/22/2026 is acknowledged. Claims 1-10 are pending. Claims 11-20 are withdrawn. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over in Le et al. (US 20190181756) view of Chapuis et al (US 20080072080). Regarding claim 1, Le teaches a group of voltage regulators (Fig. 1 (Voltage phase regulator – 114) to power a compute domain (Fig.1 (Information handling system – 116)) ; and (Fig. 1) a control circuit (Fig. 1 (power controller – 112)) coupled to the group of voltage regulators, ([0084], “a power management module 812 that is configured to determine, in substantially real-time, an amount of current drawn by each of the power domains in the SoC 802. If the difference between (1) the maximum output current value of the diced IVR(s) associated with a first power domain and (2) the amount of current drawn by the first power domain is less than a predetermined threshold, then the power management module 812 can be configured to assign an additional diced IVR to the first power domain so that the newly assigned IVRs can provide additional current to the first power domain.” wherein the control circuit is to set an initial configuration of each voltage regulator of the group of voltage regulators, to detect an increase in a load for one or more of the voltage regulators and based on the detection of the increase in the load, adjust the one or more voltage regulators. ([0021-22], “the first voltage regulator and the second voltage regulator are configured to provide, to the load chip, operating information associated with the first voltage regulator and the second voltage regulator, respectively. … the first voltage regulator is configured to receive, from the load chip, an adjustment command, requesting the first voltage regulator to adjust its operation.”, [0084], “the electronic system 800 can include a power management module 812 that is configured to determine, in substantially real-time, an amount of current drawn by each of the power domains in the SoC 802. If the difference between (1) the maximum output current value of the diced IVR(s) associated with a first power domain and (2) the amount of current drawn by the first power domain is less than a predetermined threshold, then the power management module 812 can be configured to assign an additional diced IVR to the first power domain so that the newly assigned IVRs can provide additional current to the first power domain. This way, the power management module 812 can adapt the amount of current provided to a power domain in real time.” Where the different between a maximum output current value and the amount of current draw is less than a threshold is interpreted as an increase in the load.) Le teaches configuring the voltage regulators but does not specifically teach that the control circuit sets an initial configuration of the voltage regulators. Chapuis teaches wherein the control circuit is to set an initial configuration of each voltage regulator of the group of voltage regulators, ([0040], “ the system controller 102 is adapted to provide initial-configuration data to each POL regulator (i.e., 106, 108, 110, 112, 114).”) Le and Chapuis are analogous art. Chapuis is cited to teach a similar concept of a plurality of voltage regulators which can be combined to supply power to a load. Chapuis teaches setting initial configurations to the voltage regulators before determining how to combine the voltage regulators to supply power. Based on Chapuis, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Le to set an initial configurations of the voltage regulators. Furthermore, being able to set an initial configurations of the voltage regulators improves on Le by being able to control a group of voltage regulators and supply power to a load. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “it would be advantageous to have a system and method for controlling and monitoring POL regulators within a distributed power system.”, [0008] Regarding claim 2, Chapuis teaches wherein the initial configuration is common to each of the voltage regulators. ([0034], “The other POL regulators of FIG. 3 have substantially identical configuration.”) Regarding claim 3, Le teaches wherein based on the detection of the increase in the load, the control circuit is to adjust the one or more voltage regulators to equalize loads of the voltage regulators. ([0091], “Once the SoC 902 receives the operating information of a unit IVR or an IVR group, the SoC 902 can be configured to balance the unit IVRs or IVR groups by sending adjustment commands to one or more of the unit IVRs or IVR groups, indicating that the one or more of the unit IVRs or the IVR groups should adjust their operation parameter to adjust the amount of current delivered to the SoC 902.”) Regarding claim 4, Le teaches wherein the initial configuration comprises a reference clock frequency and to adjust the one or more voltage regulators, the control circuit is to adjust the reference clock frequency of the one or more voltage regulators. ([0091], “Once the SoC 902 receives the operating information of a unit IVR or an IVR group, the SoC 902 can be configured to balance the unit IVRs or IVR groups by sending adjustment commands to one or more of the unit IVRs or IVR groups, indicating that the one or more of the unit IVRs or the IVR groups should adjust their operation parameter to adjust the amount of current delivered to the SoC 902. The operation parameter can include, for example, the IVR's switching frequency” and [0099], “The digital control signal can be encoded by adjusting the frequency of the signal and/or the pulse-width of the signa”) Regarding claim 5, Le and Chapuis teach wherein the initial configuration comprises a voltage identification definition and to adjust the one or more voltage regulators, the control circuit is to adjust the voltage identification definition of the one or more voltage regulators. ([0097], “ As discussed above, the IVR group 1314 can communicate with the load chip using communication protocols, such as I2C, SPI or PMBus, so that the IVR group 1314 can deliver the correct V.sub.OUT to the load chip 1302.” (Le) Or [0035], The hardwired settings interface 150 may include as inputs the address setting (Addr) of the POL to alter or set some of the settings as a function of the address (i.e., the identifier or the POL), e.g., phase displacement, enable/disable bit (En), trim., and VID code bits. Further, the address identifies the POL regulator during communication operations through the serial interface 144. The trim input allows the connection of one or more external resistors to define an output voltage level for the POL regulator. Similarly, the VID code bits can be used to program the POL regulator for a desired output voltage/current level” (Chapuis)) Regarding claim 6, Chapuis teaches wherein to detect the increase in the load for the one or more of the voltage regulators, the control circuit is to detect a temperature of the one or more of the voltage regulators. ([0041], “The POL controller 146, in response to a condition (e.g., receiving a request, exceeding a known parameter, having a register's contents change, etc.), is then adapted to provide at least a portion of the fault-monitoring data to the system controller 102. It should be appreciated that the fault-monitoring data may include, but is not limited to, one or more of the following types of data: output-voltage data, which may include actual-output-voltage data (i.e., the measured output voltage) or voltage-comparison data (e.g., whether the measured output voltage is above or below the highest desired output voltage, whether the measured output voltage is above or below the lowest desired output voltage, etc.); output-current data, which may include actual-output-current data (i.e., the measured output current) or current-comparison data (e.g., whether the measured output current is above or below the highest desired output current); temperature-status data, which may include actual-temperature data (i.e., the measured temperature of a POL regulator, or more particularly its heat generating components) or temperature-comparison data (e.g., whether the temperature of the POL regulator (or its components) is above or below a known value, etc.)” Regarding claim 7, Chapuis teaches wherein to detect the increase in the load for the one or more of the voltage regulators, the control circuit is to detect a local current sensor output of the one or more of the voltage regulators. ([0041], “The POL controller 146, in response to a condition (e.g., receiving a request, exceeding a known parameter, having a register's contents change, etc.), is then adapted to provide at least a portion of the fault-monitoring data to the system controller 102. It should be appreciated that the fault-monitoring data may include, but is not limited to, one or more of the following types of data: output-voltage data, which may include actual-output-voltage data (i.e., the measured output voltage) or voltage-comparison data (e.g., whether the measured output voltage is above or below the highest desired output voltage, whether the measured output voltage is above or below the lowest desired output voltage, etc.); output-current data, which may include actual-output-current data (i.e., the measured output current) or current-comparison data (e.g., whether the measured output current is above or below the highest desired output current); temperature-status data, which may include actual-temperature data (i.e., the measured temperature of a POL regulator, or more particularly its heat generating components) or temperature-comparison data (e.g., whether the temperature of the POL regulator (or its components) is above or below a known value, etc.)” Regarding claim 8, Le teaches wherein to detect the increase in the load for the one or more of the voltage regulators, the control circuit is to detect a toggle rate of the one or more of the voltage regulators. ([0069], “ For example, the unit IVRs in the IVR group can be configured to provide the same predetermined load current specification, including, for example, an output current range, a tolerable range of output current ripples, an output voltage range, a tolerable range of output voltage ripples, a switching frequency of the unit IVR, and/or any other parameters that may affect the output of the unit IVR.”, [0090], “In some embodiments, the operating information can include information on a unit IVR's or an IVR group's operating condition. The operating condition can include one or more of: (1) a frequency at which the switches in the IVR is switching (also referred to as a switching frequency),”) Regarding claim 9, Le teaches wherein the control circuit is to adjust each voltage regulator of the group of voltage regulators independently of other voltage regulators of the group of voltage regulators. ([0092], “If any one of the unit IVRs is running too fast or to slow, the SoC 902 can send an adjustment command to implicated IVR groups to correspondingly increase or decrease their switching frequency. … in other embodiments, the adjustment commands can be sent independently to individual unit IVRs or IVR groups.”) Regarding claim 10, Le teaches wherein the control circuit is to identify when one of the voltage regulators starts to provide more current than others of the voltage regulators and to reduce at least one of a target voltage or a reference frequency of the one of the voltage regulators. ([0090], “In some cases, the operating information can also include one or more of: (1) information on whether power switches are skipping any power conversion cycle (also known as pulse-skipping), and (2) a value of a current output by the IVR, which can be determined by a current sensor.” [0091], “Once the SoC 902 receives the operating information of a unit IVR or an IVR group, the SoC 902 can be configured to balance the unit IVRs or IVR groups by sending adjustment commands to one or more of the unit IVRs or IVR groups, indicating that the one or more of the unit IVRs or the IVR groups should adjust their operation parameter to adjust the amount of current delivered to the SoC 902.”) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHERI L HARRINGTON/Examiner, Art Unit 2176 June 22, 2026 /PHIL K NGUYEN/Primary Examiner, Art Unit 2176
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Prosecution Timeline

Nov 09, 2022
Application Filed
May 23, 2023
Response after Non-Final Action
Jun 25, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
69%
Grant Probability
96%
With Interview (+27.0%)
2y 9m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 318 resolved cases by this examiner. Grant probability derived from career allowance rate.

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