Prosecution Insights
Last updated: July 17, 2026
Application No. 17/984,462

MICRO LIGHT EMITTING SEMICONDUCTOR DEVICE, DISPLAY APPARATUS INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103
Filed
Nov 10, 2022
Priority
Dec 01, 2021 — RE 10-2021-0170365
Examiner
KOLAHDOUZAN, HAJAR
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
273 granted / 367 resolved
+6.4% vs TC avg
Strong +23% interview lift
Without
With
+22.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
9 currently pending
Career history
382
Total Applications
across all art units

Statute-Specific Performance

§103
87.5%
+47.5% vs TC avg
§102
8.3%
-31.7% vs TC avg
§112
2.8%
-37.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 367 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 21-30 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/4/2025. Applicant’s election without traverse of claims 1-20 in the reply filed on 12/4/2025 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 7-14, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mezouari (US 2023/0317892 A1; hereinafter Mezouari) in view of Han et al. (US 2020/0152841 A1; hereinafter Han). Regarding Independent Claim 1, Mezouari (Fig.2) discloses a micro light emitting semiconductor device comprising: a first semiconductor layer (112; [0047]); a light emitting layer (110; [0047]) provided on the first semiconductor layer; a second semiconductor layer ([109; [0047]) provided on the light emitting layer (110); and a color conversion layer (118, [0048]) provided on the second semiconductor layer, the color conversion layer comprising a layer that comprises quantum dots (118; [0049]). Mezouari does not particularly disclose wherein a doping type of the second semiconductor layer is different from a doping type of the color conversion layer. However, it is well known in the art to use different doping layers like the color conversion layer and the second semiconductor layer. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have any desired doping for the layers, since having mismatched doping types between the QDs and the surrounding semiconductor layer facilitates tailored band alignment to create charge injection or hole-blocking junctions, which are essential for driving electrons or holes into the QDs to make them luminesce. Mezouari does not particularly disclose wherein the color conversion layer comprises a porous layer. Han ([0055], [0057]-[0059]) discloses in a related art discloses wherein the color conversion layer comprises a porous layer comprising quantum dots, like CdSe metal particles ([0059]). Therefore, it would have been obvious in the art before the effective filing of the application to have a porous color conversion layer to enhance light conversion efficiency in the LED device. Regarding Claim 2. The micro light emitting semiconductor device of claim 1, Mezouari does not particularly disclose wherein the first semiconductor layer (112) includes an n-type semiconductor, and the second semiconductor layer includes a p-type semiconductor (Mezouari discloses a vise versa doping type than claimed). Mezouari does not particularly disclose wherein a doping type of the second semiconductor layer is different from a doping type of the color conversion layer. However, it is well known in the art to use different doping layers like the color conversion layer and the second semiconductor layer. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have any desired doping for the layers, since having mismatched doping types between the QDs and the surrounding semiconductor layer facilitates tailored band alignment to create charge injection or hole-blocking junctions, which are essential for driving electrons or holes into the QDs to make them luminesce. Regarding Claim 3. The micro light emitting semiconductor device of claim 1, Han (Fig.1B; [0066]) discloses wherein the porous layer (108B) includes an n-GaN. Regarding Claim 4. The micro light emitting semiconductor device of claim 1, Mezouari (Fig.2) discloses wherein the first semiconductor layer (112), the light emitting layer (110), and the second semiconductor layer (109) are included in a micro light emitting chip, and the color conversion layer (118) is connected to the micro light emitting chip in a monolithic structure ([0008], [0031]). Regarding Claim 7. The micro light emitting semiconductor device of claim 1, Mezouari (Fig.2) discloses further comprising a protective layer (302; [0050]) provided adjacent to the color conversion layer (118). Regarding Claim 8. The micro light emitting semiconductor device of claim 7, Mezouari (Fig.2) discloses wherein the protective layer (302) extends to the second semiconductor layer (109) and the light emitting layer (110). Regarding Claim 9. The micro light emitting semiconductor device of claim 1, Mezouari (Fig.2) discloses further comprising a distributed Bragg reflective layer (106; [0036]) provided on the color conversion layer (118). Regarding Claim 10. The micro light emitting semiconductor device of claim 1, Mezouari (Fig.2) discloses the micro light emitting semiconductor device is a GaN based light emitting device ([0018]). Regarding Independent Claim 11. Mezouari (Fig.2) discloses A display ([0008], [0031]) apparatus comprising: a substrate (116/114; [0051]); partition walls (300; [0050]) provided on the substrate (116/114) and spaced apart from each other; and micro light emitting semiconductor devices (100B; [0050]) respectively provided in wells partitioned by the partition walls (300), wherein each of the micro light emitting semiconductor devices comprises: a first semiconductor layer (112; [0047]); a light emitting layer (110; [0047]) provided on the first semiconductor layer (112); a second semiconductor layer (109; [0047]) provided on the light emitting layer (110); and a color conversion layer (118; [0048]) provided on the second semiconductor layer (109), the color conversion layer (118) comprising a layer that comprises quantum dots ([0049]). Mezouari does not particularly disclose wherein a doping type of the second semiconductor layer is different from a doping type of the color conversion layer. However, it is well known in the art to use different doping layers like the color conversion layer and the second semiconductor layer. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have any desired doping for the layers, since having mismatched doping types between the QDs and the surrounding semiconductor layer facilitates tailored band alignment to create charge injection or hole-blocking junctions, which are essential for driving electrons or holes into the QDs to make them luminesce. Mezouari does not particularly disclose wherein the color conversion layer comprises a porous layer. Han ([0055]) in a related art discloses wherein the color conversion layer comprises a porous layer comprising quantum dots. Therefore, it would have been obvious in the art before the effective filing of the application to have a porous color conversion layer to enhance light conversion efficiency in the LED device. Regarding Claim 12. The display apparatus of claim 11, Mezouari does not particularly disclose wherein the first semiconductor layer (112) includes an n-type semiconductor, and the second semiconductor layer includes a p-type semiconductor (Mezouari discloses a vise versa doping type than claimed). Mezouari does not particularly disclose wherein a doping type of the second semiconductor layer is different from a doping type of the color conversion layer. However, it is well known in the art to use different doping layers like the color conversion layer and the second semiconductor layer. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have any desired doping for the layers, since having mismatched doping types between the QDs and the surrounding semiconductor layer facilitates tailored band alignment to create charge injection or hole-blocking junctions, which are essential for driving electrons or holes into the QDs to make them luminesce. Regarding Claim 13. The display apparatus of claim 11, Han (Fig.1B; [0066]) wherein the porous layer (108B) includes an n-GaN layer. Regarding Claim 14. The display apparatus of claim 11, Mezouari (Fig.2) discloses wherein the first semiconductor layer (112), the light emitting layer (110), and the second semiconductor layer (109) are included in a micro light emitting chip, and the color conversion layer (118) is connected to the micro light emitting chip in a monolithic structure ([0008], [0031]). Regarding Claim 17. The display apparatus of claim 11, Mezouari (Fig.2) discloses further comprising a protective layer (302; [0050]) provided adjacent to the color conversion layer (118). Regarding Claim 18. The display apparatus of claim 17, Mezouari (Fig.2) discloses wherein the protective layer (302) extends to the second semiconductor layer (109) and the light emitting layer (110). Regarding Claim 19. The display apparatus of claim 11, Mezouari (Fig.2) discloses a distributed Bragg reflective layer (106; [0042]) provided on the color conversion layer (118). Regarding Claim 20. The display apparatus of claim 11, Mezouari (Fig.2) discloses the micro light emitting semiconductor device is a GaN based light emitting device ([0018]). Claim(s) 5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Mezouari in view of Han in view of Bhat et al. (US 20140179029 A1; hereinafter Bhat). Regarding Claim 5. The micro light emitting semiconductor device of claim 1, Mezouari does not particularly disclose an interlayer provided between the second semiconductor layer and the color conversion layer. Bhat (Fig.3; [0028]) discloses an interlayer (23; Fig 8, Fig3; [0028]) provided between the second semiconductor layer (12 of LED 13; Fig 3) and the color conversion layer (24; Fig 3, 8). Therefore, it would have been obvious in the art before the effective filing of the application to have an interlayer between the second semiconductor layer and the color conversion layer since this inclusion of bonding layer as interlayer will facilitate parallel manufacturing of both LED and color conversion layer, and bonding them in a more cost-efficient way. Regarding Claim 15. The micro light emitting semiconductor device of claim 1, Mezouari does not particularly disclose an interlayer provided between the second semiconductor layer and the color conversion layer. Bhat (Fig.3; [0028]) discloses an interlayer (23; Fig 8, Fig3; [0028]) provided between the second semiconductor layer (12 of LED 13; Fig 3) and the color conversion layer (24; Fig 3, 8). Therefore, it would have been obvious in the art before the effective filing of the application to have an interlayer between the second semiconductor layer and the color conversion layer since this inclusion of bonding layer as interlayer will facilitate parallel manufacturing of both LED and color conversion layer, and bonding them in a more cost-efficient way. Claim(s) 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Mezouari in view of Han in view of Bhat in view of Park et al. (US 2016/0133805 A1; hereinafter Park) Regarding Claim 6. The micro light emitting semiconductor device of claim 5, Bhat (Figs 8, 3; [0028]) discloses wherein the interlayer includes one of an oxide including at least one of SiO2, LiNbO3, and LiTaO3, and a metal. But it does not disclose specific metal compounds including at least one of Au:Ni, Au:Si, AI:Ge, Au:In, and Au:Sn. Park ([0179]) in a related art discloses an interlayer comprising both SiO and AuSn (The bonding layers 1902 and 1912 may be formed of an electrically insulating material or an electrically conductive material, and in this regard, examples of the electrically insulating material may include oxide such as SiO.sub.2, SiN, or the like, or resin materials including a silicon resin, an epoxy resin, or the like, and examples of the electrically conductive material may include Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, NiSn, TiW, AuSn, or a eutectic metal thereof. The bonding process may be performed in a manner in which the bonding layers 1902 and 1912 are arranged on bonding surfaces of the LED 1910 and the mounting substrate 1911 and then are bonded together). Therefore, it would have been obvious in the art before the effective filing of the application to have an interlayer comprising the oxide and metal compound between the second semiconductor layer and the color conversion layer to provide an improved bonding layers with better bonding effects. Regarding Claim 16. The micro light emitting semiconductor device of claim 5, Bhat (Figs 8, 3; [0028]) discloses wherein the interlayer includes one of an oxide including at least one of SiO2, LiNbO3, and LiTaO3, and a metal. But it does not disclose specific metal compounds including at least one of Au:Ni, Au:Si, AI:Ge, Au:In, and Au:Sn. Park ([0179]) in a related art discloses an interlayer comprising both SiO and AuSn (The bonding layers 1902 and 1912 may be formed of an electrically insulating material or an electrically conductive material, and in this regard, examples of the electrically insulating material may include oxide such as SiO.sub.2, SiN, or the like, or resin materials including a silicon resin, an epoxy resin, or the like, and examples of the electrically conductive material may include Ag, Al, Ti, W, Cu, Sn, Ni, Pt, Cr, NiSn, TiW, AuSn, or a eutectic metal thereof. The bonding process may be performed in a manner in which the bonding layers 1902 and 1912 are arranged on bonding surfaces of the LED 1910 and the mounting substrate 1911 and then are bonded together). Therefore, it would have been obvious in the art before the effective filing of the application to have an interlayer comprising the oxide and metal compound between the second semiconductor layer and the color conversion layer to provide an improved bonding layers with better bonding effects. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAJAR KOLAHDOUZAN whose telephone number is (571)270-5842. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached on (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAJAR KOLAHDOUZAN/Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Nov 10, 2022
Application Filed
May 28, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
97%
With Interview (+22.6%)
2y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 367 resolved cases by this examiner. Grant probability derived from career allowance rate.

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