DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-23 have been examined.
Information Disclosure Statement
The information disclosure statement filed 9/13/2023 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. The “Lapicque” reference cited on p. 4 of the 9/13/2023 NPL listings is not in the English language and is not provided with an explanation of relevance. It has been placed in the application file, but the information referred to therein has not been considered.
The title of the ”Taheri” citation on p. 5 of the 9/13/2023 NPL listings appears to be incorrect. The proper title appears to be “A low-power, high-resolution, adaptive sensitivity readout circuit with selective detection range for capacitive biosensors.” A new citation has been added to the 9/13/2023 IDS and the reference has been considered accordingly.
Claim Objections
Claim 7 is objected to because of the following informalities: line 6 includes “about equal or great than.” This includes a typo where the word “great” should be “greater.” Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
Claim 23 … input-dependent variable sampling module being configured to: receive an input current … and select a first predefined time step …; start a timer …; forward the input current …
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-7 and 16-22 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “substantially” in claims 2-6 and 17-21 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purpose of further examination, the associated limitations will be interpreted without the word “substantially.”
Claim 3 recites the limitation "the output or output signal" in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of further examination, the limitation will be interpreted as “an output or output signal.”
The term “about” in claims 3-4 and 18-19 (e.g. see line 6 of claim 3, “at or about”) is a relative term which renders the claim indefinite. The term “about” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purpose of further examination, the associated limitations will be interpreted without the phrase “or about.”
The term “about equal” in claims 7 and 22 (e.g. see claim 7 lines 2 and 6) is a relative term which renders the claim indefinite. The term “about equal” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purpose of further examination, the associated limitations will be interpreted without the word “about.”
The term “substantially” in claims 7 and 22 is a relative term which renders the claim indefinite. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purpose of further examination, the associated limitations will be interpreted “
The term “generally” in claim 16 is a relative term which renders the claim indefinite. The term “generally” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purpose of further examination, the associated limitations will be interpreted without the word “generally.”
Claims 4-7 and 19-22 are also rejected as including the deficiencies of a rejected base claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13, 16-21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by "Time Step Impact on Performance and Accuracy of Izhikevich Neuron: Software Simulation and Hardware Implementation" by Heidarpur et al. (“Heidarpur”).
In regard to claim 13, Heidarpur discloses:
13. A method for operating a spiking neural network, the method comprising: See p. 4, section IV, “For instance, in a network by knowing the number of the inputs and the maximum weight of each one, the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
receiving an input current; determining a time step based on the input current; See Heidarpur, bottom right on p. 2, “By increasing the input current, the spike frequency of the neuron increases. Therefore, for a specific time step (sampling time), higher input currents result in a larger error. In addition, neurons simulated with higher input current tend to become unstable for a smaller time steps compared to those with lower currents.” Also see bottom right on p. 4, “the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
starting a timer; and forwarding the input current to an artificial neuron when the timer reaches the time step for a time period selected for the artificial neuron to perform a single evaluation. Heidarpur Fig. 1 depicts various input signals that are provided to a neuron at a variety of sample frequencies. Also see section II(A), bottom right column on p. 3, “A rectangular current pulse with maximum level of 4 was applied to the neurons as depicted in this figure with a red line. First, Izhikevich neuron was simulated with small time step of 0.001, and subsequently, the simulation repeated with larger time steps.” Note that implementation using a particular “time step” requires the use of some form of timer.
In regard to claim 16, Heidarpur also discloses:
16. The method of claim 13, wherein said determining the time step comprises determining the time step [] inversely exponentially proportional to the input current. See Heidarpur Fig. 3 along with bottom right column of p. 2, “As this figure shows, the threshold time steps are decreasing exponentially with the input current.”
In regard to claim 17, Heidarpur also discloses:
17. The method of claim 13, wherein said determining the time step comprises determining the time step based on the input current and one or more reference time steps, wherein the reference time steps are determined at a plurality of preselected input currents, whereby an output or output signal of the artificial neuron from each said preselected input current is [] stable at or lower than the associated time step. Heidarpur Fig. 3, depicting preselected input amplitudes and associated time steps/frequencies associated with stability thresholds. Also see p. 2, bottom right column, “The threshold time step that triggers dumped oscillation and the threshold that neuron becomes unstable are plotted against the input current in Fig. 3.” Also p. 4, lower right column, “… the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.” Also see p. 2, lower right column, “A function approximation to the measured data in Fig. 3 (a) is: tsth = 5.76 I-0.22 − 1.26 (4) Where tsth is the stability threshold and I is the input current.”
In regard to claim 18, Heidarpur also discloses:
18. The method of claim 13, wherein said determining the time step comprises selecting one of two or more predefined time steps based on the input current, each said predefined time step being selected for a range of the input current, whereby the output or output signal of the artificial neuron from the input current in at least a portion of the range is [] stable at or about the associated predefined time step. See Heidarpur Fig. 3 and pp. 2 and 4 as cited above with respect to claim 17.
In regard to claim 19, Heidarpur also discloses:
19. The method of claim 17, wherein said determining the time step comprises selecting one of two or more predefined time steps obtained from the reference time steps, each said predefined time step being selected for a range of the input current, whereby the output or output signal of the artificial neuron from the input current in at least a portion of the range is [] stable at [] the associated predefined time step. See Heidarpur Fig. 3 and pp. 2 and 4 as cited above with respect to claim 2.
In regard to claim 20, Heidarpur also discloses:
20. The method of claim 19, wherein each said predefined time step is [] equal to at least one said reference time step determined at the associated preselected input current falling within the associated range. Heidarpur Fig. 3 and pp. 2 and 4 as cited above. Also p. 2, bottom right column, “Where tsth is the stability threshold.” Also see section IV, p. 4, “For instance, in a network by knowing the number of the inputs and the maximum weight of each one, the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
In regard to claim 21, Heidarpur also discloses:
21. The method of claim 19, wherein the output or output signal of the artificial neuron from the input current in the range is [] stable at or about the associated predefined time step. Heidarpur section V, p. 5, top left column, “In this work, the relation between the threshold time step that neuron produces stable output and its input current was uncovered.” Also section IV, p. 4, “the appropriate time step could be determined using Fig. 3.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Heidarpur in view of U.S. Patent Application Publication 20140101420 by Wu ("Wu").
In regard to claim 1, Heidarpur discloses:
1. A method for operating an artificial neural network, the method comprising: See p. 4, section IV, “For instance, in a network by knowing the number of the inputs and the maximum weight of each one, the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
receiving an input signal; [analyzing] … a sampling frequency of an artificial neuron based on the input signal; and See Heidarpur, bottom right on p. 2, “By increasing the input current, the spike frequency of the neuron increases. Therefore, for a specific time step (sampling time), higher input currents result in a larger error. In addition, neurons simulated with higher input current tend to become unstable for a smaller time steps compared to those with lower currents.” Also see bottom right on p. 4, “the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
While Heidarpur discloses analysis of various sample frequencies, Heidarpur does not expressly disclose: modulating. This is taught by Wu. See ¶ 0026-0027, “… determines a supply voltage and a clock rate (e.g. frequency) of the processor being controlled (according to lookup table 116, in an embodiment). … During runtime, an adaptive adjustment module 120 adaptively adjusts a sampling frequency and gain of the control loop (e.g., controller 108, DVFS HW/SW 106, and tracker 110) coupled to processor 104 in response to characteristics of the input workload. … According to an embodiment, lookup table 116 may include a plurality of entries of the form <C, S, f, V>, where f and V are desired frequency and supply voltage values.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Wu’s sample rate modulation with Heidarpur’s analysis in order to achieve a performance-workload match even when workload characteristics change substantially as suggested by Wu (see ¶ 0022).
Heidarpur also discloses:
forwarding the input signal or a further input signal obtained from the input signal to the artificial neuron at the sampling frequency, Heidarpur Fig. 1 depicts various input signals that are provided to a neuron at a variety of sample frequencies. Also see section II(A), bottom right column on p. 3, “A rectangular current pulse with maximum level of 4 was applied to the neurons as depicted in this figure with a red line. First, Izhikevich neuron was simulated with small time step of 0.001, and subsequently, the simulation repeated with larger time steps.”
wherein said modulating the sampling frequency comprises one or both of increasing the sampling frequency with an increased input signal and reducing the sampling frequency with a decreased input signal. See Heidarpur, bottom right on p. 2 and bottom right on p. 4 as cited above.
In regard to claim 2, Heidarpur also discloses:
2. The method of claim 1, wherein said modulating the sampling frequency comprises modulating the sampling frequency based on an amplitude of the input signal and one or more reference sampling frequencies, wherein the reference sampling frequencies are determined at a plurality of preselected input signal amplitudes, whereby an output or output signal of the artificial neuron from each said preselected input signal amplitude is []stable at or above the associated reference sampling frequency. Heidarpur Fig. 3, depicting preselected input amplitudes and associated time steps/frequencies associated with stability thresholds. Also see p. 2, bottom right column, “The threshold time step that triggers dumped oscillation and the threshold that neuron becomes unstable are plotted against the input current in Fig. 3.” Also p. 4, lower right column, “… the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.” Also see p. 2, lower right column, “A function approximation to the measured data in Fig. 3 (a) is: tsth = 5.76 I-0.22 − 1.26 (4) Where tsth is the stability threshold and I is the input current.” Also see Wu, ¶ 0026-0027, as cited above, e.g. “According to an embodiment, lookup table 116 may include a plurality of entries of the form <C, S, f, V>, where f and V are desired frequency and supply voltage values.”
In regard to claim 3, Heidarpur also discloses:
3. The method of claim 1, wherein said modulating the sampling frequency comprises selecting one of two or more predefined sampling frequencies based on an amplitude of the input signal, each said predefined sampling frequency being selected for a range of the amplitude of the input signal, whereby [an] output or output signal of the artificial neuron from the amplitude of the input signal in at least a portion of the range is [] stable at [] the associated predefined sampling frequency. See Heidarpur Fig. 3 and pp. 2 and 4 as cited above with respect to claim 2.
In regard to claim 4, Heidarpur also discloses:
4. The method of claim 2, wherein said modulating the sampling frequency comprises selecting one of two or more predefined sampling frequencies obtained from the reference sampling frequencies, each said predefined sampling frequency being selected for a range of the amplitude of the input signal, whereby the output or output signal of the artificial neuron from the amplitude of the input signal in at least a portion of the range is [] stable at []the associated predefined sampling frequency. See Heidarpur Fig. 3 and pp. 2 and 4 as cited above with respect to claim 2.
In regard to claim 5, Heidarpur also discloses:
5. The method of claim 4, wherein each said predefined sampling frequency is [] equal to at least one said reference sampling frequency determined at the associated preselected input signal amplitude falling within the associated range. Heidarpur Fig. 3 and pp. 2 and 4 as cited above. Also p. 2, bottom right column, “Where tsth is the stability threshold.” Also see section IV, p. 4, “For instance, in a network by knowing the number of the inputs and the maximum weight of each one, the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
In regard to claim 6, Heidarpur also discloses:
6. The method of claim 3, wherein the output or output signal of the artificial neuron from the amplitude of the input signal in the range is [] stable at or about the associated predefined sampling frequency. Heidarpur section V, p. 5, top left column, “In this work, the relation between the threshold time step that neuron produces stable output and its input current was uncovered.” Also section IV, p. 4, “the appropriate time step could be determined using Fig. 3.”
In regard to claim 8, Heidarpur discloses:
8. The method of claim 1, wherein the input signal is an input current. See Heidarpur, bottom right on p. 2, “By increasing the input current, …”
In regard to claim 9, Heidarpur discloses:
9. The method of claim 1, wherein the artificial neural network is a spiking neural network. See Heidarpur, section I, “Spiking neural networks.”
In regard to claim 12, Heidarpur discloses:
12. The method of claim 1, wherein the method is operable to reduce power consumption in the artificial neural network. Heidarpur, section 1, p. 1, right column, “Results indicated that larger time steps than those that used in the previous works could be employed which significantly improves performance and cost of the design.” Also see p. 4, top right column, “smaller time steps consume marginally less power. However, energy consumption is a function of the total time taken to complete a task. Table IV presents the number of clock cycles required for each design to generate 5 spikes. According to this table, generating 5 spikes with a time step of 1/1024 consumes 64 x (90=85) = 67:8 times more power compared to those with time step of 1/16.”
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Heidarpur and Wu as applied above, and further in view of U.S. Patent Application Publication 20180120916 by Lin et al. ("Lin").
In regard to claim 7, Heidarpur also discloses:
7. The method of claim 2, wherein said modulating the sampling frequency comprises:
i) modulating the sampling frequency to be [] equal to or greater than one said reference sampling frequency if the amplitude of the input signal is [] said preselected input signal amplitude associated with the reference sampling frequency; and Heidarpur p. 4, bottom right column, “For instance, in a network by knowing the number of the inputs and the maximum weight of each one, the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
Heidarpur does not expressly disclose: ii) if the amplitude of the input signal is different from all said preselected input signal amplitudes, modulating the sampling frequency to be [] equal to or great[er] than an estimated sampling frequency interpolated or extrapolated from one or more said reference sampling frequencies. This is taught by Lin. See Lin ¶ 0039, “The power calculator circuit 124 conducts an interpolation calculation by using the two adjacent frequency values F1 and F2 and the two candidate power values P1 and P2. For example (but not limited hereto), the power calculator circuit 124 performs a calculation according to an equation, PA=P1*(FA−F1)/(F2−F1), for acquiring the power value PA of the target IP circuit 110. Under certain circumstances, when the system clock frequency value FA of the target IP circuit 110 falls outside the border of the power model, the power calculator circuit 124 conducts an extrapolation calculation by using these adjacent frequency values so as to acquire the power value of the target IP circuit 110.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Lin’s interpolation/extrapolation with Heidarpur’s frequencies in order to acquire appropriate values as suggested by Lin.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Heidarpur and Wu as applied above, and further in view of “A Survey of Neuromorphic Computing and Neural Networks in Hardware” by Schuman et al. (“Schuman”) and "Spike-based strategies for rapid processing" by Thorpe et al. (“Thorpe”).
In regard to claim 10, Heidarpur discloses:
10. The method of claim 1, wherein the artificial neural network comprises a digital neuron model selected from the group consisting of … Izhikevich model, See Heidarpur, p. 1, right column, “… Izhikevich model.”
Heidarpur does not expressly disclose the remaining models.
Schuman teaches: Adaptive-Exponential Integrate-and-Fire model, Hodgkin-Huxley model, Leaky Integrate-and-Fire model, … probabilistic and stochastic spiking neuron model and probabilistic neurogenetic model. See Schuman, p. 5, section III(A)(1), “Hodgkin-Huxley.” Also p. 6, section III(A)(4), “leaky integrate-and-fire … adaptive exponential integrate-and-fire.” Also section III(C), p. 7, “spiking probabilistic networks.” Also section III (C), p. 8, “Probabilistic neural networks … Stochastic neural networks.” Also section IV(A), p. 10, “Off-chip nature based implementations include differential evolution [1321]-[1324], evolutionary or genetic algorithms.” In practicality there are only a finite number of neural models. It would have been obvious to one of ordinary skill in the art to try the various models of Schuman in the neural network of Heidarpur in an attempt to provide better neural computation, as a person with ordinary skill has a good reason to pursue the known replacement algorithms within his or her technical grasp. In turn, because neural models when used in the system of Heidarpur has the predicted properties of the neural behavior, it would have been obvious.
Schuman does not expressly disclose: Thorpe's model. This is taught by Thorpe. See Thorpe, p. 715, right column, “… a coding scheme that encodes information in the relative timing of spikes across a population of neurons, or more specifically, in the order in which neurons fire.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Thorpe’s model with Heidarpur’s spiking neural network in order to utilize efficient computation as suggested by Thorpe (see section 1, p. 715, right column).
In regard to claim 11, Heidarpur discloses:
11. The method of claim 10, wherein the digital neuron model is Adaptive-Exponential Integrate-and-Fire model or Izhikevich model, and said modulating the sampling frequency comprises selecting the sampling frequency between dt= 1/4096 ms and dt=8 ms. See Heidarpur, p. 1, right column, “… Izhikevich model.” Also see Fig. 1 depicting time steps between 0.001 and 3 ms.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Heidarpur as applied above, and further in view of Schuman and Thorpe.
In regard to claims 14-15, parent claim 13 is addressed above.
All further limitations of claims 14-15 have been addressed in the above rejection of claims 10-11, respectively.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Heidarpur as applied above, and further in view of Lin.
In regard to claim 22, Heidarpur also discloses:
22. The method of claim 17, wherein said determining the time step comprises:
i) determining the time step to be [] equal to or lower than one said reference time step if the input current is [] said preselected input current associated with the reference time step; and Heidarpur p. 4, bottom right column, “For instance, in a network by knowing the number of the inputs and the maximum weight of each one, the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
Heidarpur does not expressly disclose: ii) if the input current is different from all said preselected input currents, determining the time step to be [] equal to or lower than an estimated time step interpolated or extrapolated from one or more said reference time steps. This is taught by Lin. See Lin ¶ 0039, “The power calculator circuit 124 conducts an interpolation calculation by using the two adjacent frequency values F1 and F2 and the two candidate power values P1 and P2. For example (but not limited hereto), the power calculator circuit 124 performs a calculation according to an equation, PA=P1*(FA−F1)/(F2−F1), for acquiring the power value PA of the target IP circuit 110. Under certain circumstances, when the system clock frequency value FA of the target IP circuit 110 falls outside the border of the power model, the power calculator circuit 124 conducts an extrapolation calculation by using these adjacent frequency values so as to acquire the power value of the target IP circuit 110.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Lin’s interpolation/extrapolation with Heidarpur’s frequencies in order to acquire appropriate values as suggested by Lin.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Heidarpur in view of Wu and U.S. Patent Application Publication 20130117589 by Satyamoorthy et al. ("Satyamoorthy").
In regard to claim 23, Heidarpur discloses:
23. A spiking neural network comprising an input-dependent variable sampling … and a digital neuron module, the input-dependent variable sampling module being configured to: Heidarpur, Fig. 4 and section II(B) on p. 3, describing hardware implementation. Also see Fig. 5 on p. 4, depicting time step events (i.e. sampling events). The presence of time step events requires some form of sampling module or they would not exist. Also see bottom right column on p. 3, “the spiking frequency linearly changes with the time step.”
While disclosing a neuron module and associated sampling, Heidarpur does not expressly disclose a sampling module. This is taught by Wu. See Wu, Fig. 1 and ¶ 0026, “an adaptive adjustment module 120 adaptively adjusts a sampling frequency.” Also ¶ 0061, “The monitoring and/or adaptive adjustment may be initiated by a trigger based upon, for example, a configured duration (e.g., periodically triggered by a timer).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Wu’s module with Heidarpur’s sampling in order to provide system control as suggested by Wu.
Heidarpur also discloses:
receive an input current to be compared to a threshold value and select a first predefined time step … and a second predefined time step …; Heidarpur Fig. 3, depicting preselected input amplitudes and associated time steps/frequencies for comparison with associated stability thresholds. Also p. 4, lower right column, “… the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
While disclosing comparison of currents, Heidarpur does not expressly disclose: if the input current is less than the threshold value … if the input current is more than the threshold value. However, this is taught by Satyamoorthy. See Satyamoorthy ¶ 0020, “A first set of weight values and a first set of preset values for the parameters can correspond to a first frequency or frequency range, and a second set of weight values and a second set of preset values for the parameters can correspond to a second frequency or frequency range. … The controller can reduce a sampling rate of a hardware monitor if a performance margin of the hardware monitor is greater than a first threshold and a rate of change of the power supply output voltage level is less than a second threshold.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Satyamoorthy’s threshold comparisons with Heidarpur’s current/frequency graphs in order to optimize performance as suggested by Satyamoorthy.
Heidarpur also discloses:
receiving an input current; determining a time step based on the input current; See Heidarpur, bottom right on p. 2, “By increasing the input current, the spike frequency of the neuron increases. Therefore, for a specific time step (sampling time), higher input currents result in a larger error. In addition, neurons simulated with higher input current tend to become unstable for a smaller time steps compared to those with lower currents.” Also see bottom right on p. 4, “the maximum input to the neuron and accordingly the appropriate time step could be determined using Fig. 3.”
start a timer; and forward the input current to the digital neuron module when the timer reaches a selected one of the first and second predefined time steps for a time period selected for the digital neuron module to perform a single evaluation, Heidarpur Fig. 1 depicts various input signals that are provided to a neuron at a variety of sample frequencies. Also see section II(A), bottom right column on p. 3, “A rectangular current pulse with maximum level of 4 was applied to the neurons as depicted in this figure with a red line. First, Izhikevich neuron was simulated with small time step of 0.001, and subsequently, the simulation repeated with larger time steps.” Note that implementation using a particular “time step” requires the use of some form of timer. Note also Wu ¶ 0061 as cited above, i.e. “triggered by a timer.”
wherein the first predefined time step is longer than the second predefined time step. See Heidarpur Fig. 3, depicting variously sized time steps.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication 20080192841 by Chen et al. ¶ 0012, “Another advantage is that the technique allows the sampling rate to be reduced whenever the input signal exhibits low amplitude--typically due to noise in the absence of an information-carrying signal--while maintaining a high sampling rate for input signals exhibiting high amplitude, which is characteristic of signals that convey information.” Also See ¶ 0054, “Furthermore, the techniques provided by the invention have the added advantage of dynamically reducing the sampling rate in regions of low input (typically noise) while maintaining a high sampling rate in regions of high input (typically the signal).”
U.S. Patent Application Publication 20140074761 by Hunzinger et al. See ¶ 0228-0229, “If there is a high rate of input events, the Model dynamics are advanced at small time intervals. However, if there is a low rate of input events, the Model dynamics, without artificial events, may be advanced by larger time intervals. … Artificial events can also be defined to occur conditionally, such as dependent on state or spiking rate.” ¶ 0253, “In order to configure the model parameters, the dynamical neuron parameters described by Izhikevich can be considered: … net current during a spike d.” Also see Fig. 50, depicting increasing spike frequency (element 5002) related to increasing input amplitude (element 5004). Also ¶ 0357, “A class 1 behavior, or increasing spiking rate, may be achieved by decreasing both the negative regime voltage time constant and current time constants.”
U.S. Patent 10831384 to Myers et al. See Fig. 4 and col. 6 and lines 39-41, “Each row in the consumption estimate profile 504 can correspond to one of the memory components 110 of FIG. 1 (e.g., the memory dies 118 of FIG. 1), and each column can correspond to a particular time interval 410 of FIG. 4 (e.g., corresponding to the sampling frequency).”
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/James D. Rutten/Primary Examiner, Art Unit 2121