Prosecution Insights
Last updated: October 02, 2026
Application No. 17/985,020

Photonic Ising Compute Engine with An Optical Phased Array

Non-Final OA §103§112
Filed
Nov 10, 2022
Priority
Nov 10, 2021 — provisional 63/278,033
Examiner
DASGUPTA, SHOURJO
Art Unit
2144
Tech Center
2100 — Computer Architecture & Software
Assignee
Raytheon Technologies Corporation
OA Round
2 (Non-Final)
65%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 65% — above average
65%
Career Allowance Rate
303 granted / 465 resolved
+10.2% vs TC avg
Strong +39% interview lift
Without
With
+39.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
26 currently pending
Career history
491
Total Applications
across all art units

Statute-Specific Performance

§101
12.6%
-27.4% vs TC avg
§103
57.9%
+17.9% vs TC avg
§102
11.0%
-29.0% vs TC avg
§112
16.3%
-23.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 465 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Detailed Action This second Non-Final Office Action is responsive to Applicants’ amendments and arguments as received 6/8/26. Claims 1-29 were pending, but by way of the reply then Applicants cancelled claim 3. Hence, claims 1-2 and 4-29 remain pending, of which claims 1, 17-18, and 24 are independent. Claim Rejections - 35 USC § 112 3. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 4. Claims 2 and 14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding claim 2, the claim recites “A photonic processor computing engine device of claim 1” which practices improper antecedent basis. Hence, because a “photonic processor computing engine device” as recited has already been introduced in independent claim 1, from which claim 2 depends, the further recitation as noted here using “a” in claim 2 raises the ambiguity of whether an entirely different device instance is being claimed by Applicants in claim 2, or whether Applicants intend to further clarify the same instance as introduced in independent claim 1 from which this present claim depends. For this reason, the improper antecedent basis of claim 2’s recitation as noted here renders the claim vague and indefinite. Regarding claim 14, the claim as amended now recites “The photonic processor computing engine device of claim 1, the focal plane array (FPA) comprising a plurality of imaging pixels, wherein the plurality of image pixels are fewer in number than the plurality of radiating pixels of the optical phased array (OPA).” Applicants’ amendment to clarify “a plurality of pixels” to now read “a plurality of imaging pixels” still creates an antecedent basis disagreement with the later recitation of “the plurality of image pixels”, thereby rendering the claim vague and indefinite. The Examiner recommends a clarifying amendment that makes the two recitations consistent in terms of word choice for either one of “imaging” or “image” in their clarification of “pixels.” Claim Rejections - 35 USC § 103 5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 7. Claims 1-2, 4-6, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2018/0172935 (“Collins”) in view of Non-Patent Literature “Collective Techniques for Coherent Beam Combining of Fiber Amplifiers” (“Brignon”, previously cited). Regarding claim 1, COLLINS teaches A photonic processor computing engine device () comprising: a photonic integrated circuit (PIC) ([0002]: “This invention relates to a photonic integrated circuit (PIC).”, as shown in FIG. 1 and discussed starting at [0032]) comprising: an optical phased array (OPA) comprising a plurality of radiating pixels that radiate optical signal beams based on electromagnetic radiation ([0032] discussing “The integrated circuit also comprises a layer of III-V material 104, which is arranged in a recess 105 of the passive layer. The layer of III-V material 104 incorporates an active photonic device 106. The layer of III-V material 104 is configured to allow light to be transferred between the passive photonic device and the active photonic device”, where the active photonic device may be “lasers, which generate photons in response to an electrical trigger, and electro-absorption modulators (EAM), which can be used to modulate the intensity of light via an electrical voltage” (i.e., reading on recitation for “radiating pixels that radiate optical signal beams based on electromagnetic radiation”) and the Examiner reads [0052] to understand that there may be multiple active devices fabricated into a common layer, i.e., an “array” of a “plurality” of active photonic device instances/elements), each of the plurality of radiating pixels comprising: an optical antenna ([0035]: “An active photonic device is typically capable of generating, manipulating or detecting light. Active photonic devices are usually provided with some form of electrical input or output. This enables electronic signals to be converted into light and vice versa. Examples of active photonic devices include lasers, which generate photons in response to an electrical trigger …”, where the Examiner understands the active photonic device to be/include a light emitter for sending to a passive device in the passive layer, i.e., akin to an antenna as recited); and an optical phase modulator ([0035]: “Examples of active photonic devices include lasers, which generate photons in response to an electrical trigger, and electro-absorption modulators (EAM), which can be used to modulate the intensity of light via an electrical voltage.”); an electronic control circuit in electrical communication with the optical phased array (OPA) to calibrate and control the optical phase modulators of the optical phased array (OPA) ([0035] as discussed above teaches that the active layer and its active devices as taught include a modulator (e.g., “generate photons in response to an electrical trigger, and electro-absorption modulators (EAM), which can be used to modulate the intensity of light via an electrical voltage”) that is equivalent to the recited “optical phase modulator”); an … array … positioned to receive the optical signal beams transmitted from the plurality of radiating pixels (the passive layer as discussed per [0032], [0034], [0036]-[0040], and [0042]-[0045], which the Examiner understands to receive the transfer for light/photons from an active layer); an electronic feedback circuit in electrical communication with the … array … and the electronic control circuit to process a measured intensity of the optical signal beams received by a defined portion of the … array … from the optical phased array (OPA) and provide a feedback signal to the electronic control circuit based on the measured intensity for recalibrating the optical phase modulators of the plurality of radiating pixels to control the phase of the optical signal beams emitted by the plurality of radiating pixels ([0061] discussing close integration of electronics and photonics, with examples provided per [0062]-[0065] providing examples of modulation devices in an electronic layer/capacity as closely integrated with the photonic elements of the active layer, and the Examiner understands these examples to actively regulate the active elements/devices via an applied voltage based on a measurement used to govern loss); a plurality of layers including: a photonic layer comprising the optical phased array (OPA) (layer 104 as discussed per [0032], featuring the active photonic devices which may constitute an array per [0052]); and an electronic layer comprising the electronic control circuit disposed on a surface of the photonic layer, the electronic control circuit comprising a digital read-in integrated circuit (DRIIC) board in electrical communication with each of the optical phase modulators of the radiating pixels, the digital read-in integrated circuit being configured to apply voltages to control each of the optical phase modulators ([0061] discussing close integration of electronics and photonics, with examples provided per [0062]-[0065] providing examples of modulation devices in an electronic layer/capacity as closely integrated with the photonic elements of the active layer, and the Examiner understands these examples to actively regulate the active elements/devices via an applied voltage based on a measurement used to govern loss, and that [0061]’s discussion of this close integration amounts to electronics and photonics elements being on adjoining layers such that there is a physical/surface contact). As discussed above, Collins teaches a passive layer, as discussed per [0032], [0034], [0036]-[0040], and [0042]-[0045], which the Examiner understands to receive the transfer for light/photons from an active layer, and which the Examiner has equated essentially with “an array positioned to receive the optical signal beams transmitted from the plurality of radiating pixels.” The Examiner notes that Applicants’ claim more fully characterizes this array element as discussed above as a focal plane array (FPA). Regarding this limitation as fully clarified, the Examiner notes that Collins is silent as to any lens or focal elements disposed between the active and passive layers/elements of its architecture, and hence does not explicitly teach this claimed feature as fully clarified. Rather, the Examiner relies upon BRIGNON to teach what Collins otherwise lacks, see e.g., Brignon’s Figure 5.15 teaching a lenslet array as situated in between an optical/photon emitter and a receiving side where the beams are projected and measured for phase modulation, where discussions relating to lens use, calibration, etc. (as found in section 5.2.2.2 on pages 143-145 and section 5.3.1 on pages 150-151) suggest that the lens use as taught improves the photon transfer in a manner that is meaningful to the system’s efficiency and hence functioning. Both Collins and Brignon relate to photonic integrated circuit systems, and hence are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Brignon’s lens feature, as discussed above, into a framework such as Collins’s to regulate the transfer of photons/light between its active and passive elements in a manner that can be calibrated via the lens for efficiency and hence improved performance. Regarding claim 2, Collins in view of Brignon teach A photonic processor computing engine device of claim 1, as discussed above. The aforementioned references further teach the additional limitations further comprising: a lens assembly comprising one or more lenses and disposed between the photonic integrated circuit (PIC) and the focal plane array (FPA) to project the far field from the radiating pixels onto the focal plane array (FPA) (). The motivation for combining the references is as discussed above in relation to claim 1. Regarding claim 4, Collins in view of Brignon teach The photonic processor computing engine device of claim 1, as discussed above. The aforementioned references further teach the additional limitations wherein the electronic layer comprises one or more CMOS circuits (). The motivation for combining the references is as discussed above in relation to claim 1. Regarding claim 5, Collins in view of Brignon teach The photonic processor computing engine device of claim 1, as discussed above. The aforementioned references further teach the additional limitations wherein the (PIC) further comprises: a plurality of optical waveguides, each optically coupled to one of the plurality of radiating pixels of the optical phased array (OPA); and a cascading waveguide tree comprising an electromagnetic radiation inlet configured to receive electromagnetic radiation from an electromagnetic radiation source, and a plurality of waveguide branches in optical communication with the electromagnetic radiation inlet and the plurality of optical waveguides. The motivation for combining the references is as discussed above in relation to claim 1. Regarding claim 6, Collins in view of Brignon teach The photonic processor computing engine device of claim 1, as discussed above. The aforementioned references further teach the additional limitations wherein the (PIC) further comprises: a main optical waveguide in communication with an electromagnetic radiation source, and configured to receive electromagnetic radiation from the electromagnetic radiation source; a plurality of branch optical waveguides each optically coupled to the main optical waveguide and two or more radiating pixels of the plurality of radiating pixels. The motivation for combining the references is as discussed above in relation to claim 1. Regarding claim 14, Collins in view of Brignon teach The photonic processor computing engine device of claim 1, as discussed above. The aforementioned references further teach the additional limitations where the focal plane array (FPA) comprising a plurality of imaging pixels, wherein the plurality of image pixels are fewer in number than the plurality of radiating pixels of the optical phased array (OPA). The motivation for combining the references is as discussed above in relation to claim 1. 8. Claims 7-10, 13, 17-21, and 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Brignon and further in view of Non-Patent Literature “Solving complex optimization problems with a coherent Ising machine” (“Takesue”, previously cited). Regarding claim #, 9. Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Brignon and further in view of Non-Patent Literature “Coupling strategies for silicon photonics integrated chips” (“Marchetti”, previously cited). Regarding claim #, 10. Claims 11-12, 22-23, and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Collins in view of Brignon and further in view of Takesue and then Non-Patent Literature “Photonic simulation of entanglement growth and engineering after a spin chain quench” (“Pitsios”, previously cited). Regarding claim #, Response to Arguments Applicants’ arguments, filed 6/8/26, with respect to the pending claims have been fully considered and are persuasive. Therefore, the prior art rejections as previously presented have been withdrawn. However, upon further consideration, new grounds of rejection are presented via this present Action. In particular, the Examiner believes newly-applied Collins, as discussed above in relation to claim 1 for example, addresses the arguments made by Applicants relating to recitations found in previously-presented and now cancelled claim 3: namely a recitation for a configuration where the electronic control circuit is disposed on a surface of a photonic layer, which the Examiner agrees Brignon as previously relied-upon does not teach. See the obviousness rejection for claim 1 as presented in this Action. Further, Takesue, which was previously-presented and asserted, is relied upon to address arguments relating to Applicants’ recitations for “ground energy state”, e.g., per claims 13, 17-19, and 24-25 (which explicitly recite the aforementioned term) and any further dependent claims relating thereto. See the obviousness rejection for claim 13 as presented in this Action, for example. Conclusion The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure: US 2014/0376857 A1, Chantre, teaching phase shifting as integrated into the photonic layer (paras 32, 56). US 2020/0233164 A1, Carpentier, teaching a photonic system per FIG. 1, where the emitter (LIC) and processing (PIC) layers are adjacently situated. CN 111025671 B, Wang, teaching “a multifunctional super-lens array, at the same time with colour separation and focusing function, so as to simplify the structure of the interference imaging system, improve the system integration degree and reduce the energy loss and cost” (section Contents of the Invention), such that “The invention further claims an optical system, comprising a multifunctional superlens array; a photon integrated loop and a detector array; the multifunctional super-lens array is the multifunctional super-lens array according to any one of the above; the multifunctional super-lens array is used for collecting light information to obtain the target optical information; the incident light is divided into a plurality of narrow-band beams after passing through each super-lens unit; the photon integrated loop is used for focusing coupling narrow band light beam and performing phase adjustment to make two beams of light from the same wavelength of different super-lens unit into coherent light satisfying the interference condition; the detector array obtains the coherent light information and performs image restoration to obtain high resolution image.” CN 1732506 A, Pan CN 110954966 B, Zhao/Hu, teaching “The invention belongs to the technical field of optical imaging, claims a plane photoelectric detection system based on super-lens array, the system comprises a radiation-shaped plane super-lens array composed of multiple plane super-lenses orderly arranged along the light path, a photon integrated loop and an information processing module; the plane super-lens array is used for dividing the incident light into multiple narrow-wave band beams and focusing; the photonic integrated loop is used for receiving the incident light passing through the plane super-lens array, and adjusting the phase of the incident light, satisfying the interference condition; the information processing module is used for recovering the image based on the interference image generated by the photonic integrated loop; obtaining the high resolution image. The system does not need to use large amount of grating beam splitter to split light; the scale of the photon integrated loop is reduced; the whole structure is compact; the integration degree is high; at the same time, it reduces the loss; the energy utilization rate is high; Further, it can greatly reduce the size and weight of the remote sensing load.” (Abstract) Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHOURJO DASGUPTA whose telephone number is (571)272-7207. The examiner can normally be reached M-F 8am-5pm CST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tamara Kyle can be reached at 571 272 4241. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHOURJO DASGUPTA/Primary Examiner, Art Unit 2144
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Prosecution Timeline

Nov 10, 2022
Application Filed
Mar 10, 2026
Non-Final Rejection mailed — §103, §112
Jun 08, 2026
Response Filed
Aug 31, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

2-3
Expected OA Rounds
65%
Grant Probability
99%
With Interview (+39.3%)
3y 5m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 465 resolved cases by this examiner. Grant probability derived from career allowance rate.

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