Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
3. Claim 14 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
The claim recites “The photonic processor computing engine device of claim 1, the focal plane array (FPA) comprising a plurality of pixels, wherein the plurality of image pixels are fewer in number than the plurality of radiating pixels of the optical phased array (OPA).”
The Examiner asserts that there is no proper antecedent basis for “image pixels” either in this present claim or in the independent claim from which it depends. Hence, the ambiguity of the term bolded by the Examiner in the claim as reproduced just above has the effect of rendering the claim vague and indefinite.
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office Action:
A person shall be entitled to a patent unless—
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-3, 5-6, 14, 17-18, and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Non-Patent Literature “Collective Techniques for Coherent Beam Combining of Fiber Amplifiers” (“Brignon”, cited in Applicants’ IDS dated 4/28/25).
Regarding claim 1, BRIGNON teaches A photonic processor computing engine device (the architecture of Figure 5.8, per page 147) comprising:
a photonic integrated circuit (PIC) (the operations for the architecture thereof is based on photonics, see e.g., the discussion characterizing the architecture’s fiber array found in section 5.3.1 specifically on page 150 and also the discussion characterizing the architecture’s phase modulators as using integrated photonics found in section 5.3.3 specifically on page 155, and where such architecture per Figure 5.8 or as further clarified per Figure 5.15 (on page 157) are clear examples of circuits that happen to provide a feedback loop element therein to tune their operation) comprising:
an optical phased array (OPA) comprising a plurality of radiating pixels that radiate optical signal beams based on electromagnetic radiation (in the reference’s discussion of near field, see fibers arranged per sections 5.2.2 - 5.2.2.1 (and shown in Figure 5.3 on page 142), which are characterized as having a phased difference per section 5.1 (specifically page 137) and clarified further in same section on the following page 138 as having “individual phase control” such that they can “behave like optical phased array antennas”, and where the basis of the light/laser operation is essentially a radiating source as discussed in the first paragraph of section 5.1 on page 137), each of the plurality of radiating pixels comprising:
an optical antenna (section 5.1 on page 138: emitters/fibers essentially behaving “like optical phased array antennas”); and
an optical phase modulator (section 5.1 on page 138: emitters/fibers having individual phase control, as further and more extensively clarified in section 5.3.3 on page 155 (“Phase modulators are key elements for the control of the phase of the beam from each fiber. Different solutions can be employed for this purpose.” and that for the reference’s experiment, see section 5.4’s discussion of PLZT-based electro-optic phase modulators (which is illustrated in Figure 5.15 via the “16 x 4 channels PLZT phase modulators”)); and
an electronic control circuit in electrical communication with the optical phased array (OPA) to calibrate and control the optical phase modulators of the optical phased array (OPA) (see the computer/processing element in Figure 5.15 on page 157, in between the depicted QWLSI and the feedback array returning to the phase modulators);
a focal plane array (FPA) positioned to receive the optical signal beams transmitted from the plurality of radiating pixels (page 157, Figure 5.15: “lenslet array” (as discussed in section 5.5.1 on page 159), where the Examiner generally understands this lens array as taught to correspond 1-1 to the taught fiber array); and
an electronic feedback circuit in electrical communication with the focal plane array (FPA) and the electronic control circuit to process a measured intensity of the optical signal beams received by a defined portion of the focal plane array (FPA) from the optical phased array (OPA) and provide a feedback signal to the electronic control circuit based on the measured intensity for recalibrating the optical phase modulators of the plurality of radiating pixels to control the phase of the optical signal beams emitted by the plurality of radiating pixels (section 5.3.2.2 on page 153 discussing a QWLSI (e.g., as shown in relation to a phase processing and feedback loop computer/controller in Figure 5.15 on page 157), where the QWLSI is understood to measure the phase and use it to correct a phase via the feedback loop, e.g. by providing a feedback loop signal to the PLZT-based electro-optic phase modulators (e.g., illustrated in Figure 5.15 via the “16 x 4 channels PLZT phase modulators”), and where the measurement of phase is performed as discussed in section 5.3 specifically on page 148 (“The
N fiber outputs are disposed in a matrix arrangement and collimated by a lens array. A small fraction of the output beams is sampled and launched to a phase sensor device in order to measure the piston-phase errors between the N fibers.”, where the sampling of output beams corresponds to the recitation for “a defined portion” of the FPA)).
Regarding claim 2, Brignon teaches A photonic processor computing engine device of claim 1, further comprising: a lens assembly comprising one or more lenses and disposed between the photonic integrated circuit (PIC) and the focal plane array (FPA) to project the far field from the radiating pixels onto the focal plane array (FPA) (page 157, Figure 5.15: “lenslet array” (as discussed in section 5.5.1 on page 159), where the Examiner generally understands this lens array as taught to correspond 1-1 to the taught fiber array).
Regarding claim 3, Brignon teaches The photonic processor computing engine device of claim 1, comprising:
a plurality of layers including:
a photonic layer comprising the optical phased array (OPA) (a manufactured high-precision optical fiber holder, as discussed in section 5.3.1 specifically on page 149 (generally in the first paragraph but more specifically in the second paragraph), which the Examiner understands to essentially constitute a container for depicted “fiber array” of page 157’s Figure 5.15); and
an electronic layer comprising the electronic control circuit disposed on a surface of the photonic layer, the electronic control circuit comprising a digital read-in integrated circuit (DRIIC) board in electrical communication with each of the optical phase modulators of the radiating pixels, the digital read-in integrated circuit being configured to apply voltages to control each of the optical phase modulators (adjacent to Figure 5.15’s “fiber array” see the other architectural elements such as the QWLSI, the computer/control element that follows the QWLSI in forming the phase processing and feedback loop, and the 16 x 4 channels PLZT phase modulators).
Regarding claim 5, Brignon teaches the photonic processor computing engine device of claim 1, wherein the (PIC) further comprises:
a plurality of optical waveguides, each optically coupled to one of the plurality of radiating pixels of the optical phased array (OPA) (page 149, 1st paragraph, discussing the grooves implemented into the surface that permit different lines in the implementation of different fibers, which the Examiner equates with a waveguide as recited, and further see Figure 5.8 where fibers are laid out in a design such that it reasons that each groove/line as mentioned above would correspond to teach fiber associated with the fiber array, and the same reasoning provided here can be extensible to Figure 5.15 on page 157); and
a cascading waveguide tree comprising an electromagnetic radiation inlet configured to receive electromagnetic radiation from an electromagnetic radiation source, and a plurality of waveguide branches in optical communication with the electromagnetic radiation inlet and the plurality of optical waveguides (Figure 5.15 as mentioned above is a clarification or extension of the sort of circuit shown in Figure 5.8, but with the Figure 5.15 the lines that connect the source/inlet on the left side are branched leading to the phase modulators which then lead to the waveguides that further connect the fiber to the fiber array).
Regarding claim 6, Brignon teaches the photonic processor computing engine device of claim 1, wherein the (PIC) further comprises: a main optical waveguide in communication with an electromagnetic radiation source, and configured to receive electromagnetic radiation from the electromagnetic radiation source (both Figures 5.8 and 5.15 showing the source/inlet in connection with the rest of the circuit to the right, where that connection is at least one line/groove that could constitute a “main” waveguide as recited); and
a plurality of branch optical waveguides each optically coupled to the main optical waveguide and two or more radiating pixels of the plurality of radiating pixels (Figure 5.15 as mentioned above is a clarification or extension of the sort of circuit shown in Figure 5.8, but with the Figure 5.15 the lines that connect the source/inlet on the left side are branched leading to the phase modulators which then lead to the waveguides that further connect the fiber to the fiber array).
Regarding claim 14, Brignon teaches The photonic processor computing engine device of claim 1, the focal plane array (FPA) comprising a plurality of pixels, wherein the plurality of image pixels are fewer in number than the plurality of radiating pixels of the optical phased array (OPA) (page 157, Figure 5.15: “lenslet array” (as discussed in section 5.5.1 on page 159), where the Examiner generally understands this lens array as taught to correspond 1-1 to the taught fiber array).
Regarding claims 17-18 and 24, the claims grouped here feature the same or similar limitations discussed above per claim 1.
In addition, they discuss correlating the measured phase to a “ground energy state”, which was absent in claim 1. However, the Examiner believes the reference teaches this, see e.g., section 5.4 beginning on page 156, discussing “an ideal in-phase coherent summation of the 64 beamlets in a square lattice arrangement” and the determination of a deviation corresponding to efficiency degradation, which is subject to evaluation per the last two paragraphs of section 5.4 on page 158.
Further recitations for these claims grouped here as relating to processor or memory / non-transitory machine-readable storage medium elements can be satisfied via the computer/control element that follows the QWLSI in forming the phase processing and feedback loop, which the Examiner believes would feature processor and persistent memory aspects to function as intended in transforming a measured phase into a corrected or adjusted phase.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Brignon in view of Non-Patent Literature “Photonic Integrated Circuits (PICs) for Next Generation Space Applications” (“Bozovich”).
Regarding claim 4, Brignon teaches the photonic processor computing engine device of claim 3, as discussed above. The present claim further recites the additional limitation wherein the electronic layer comprises one or more CMOS circuits, which Brignon does not explicitly teach. At best, Brignon contemplates the use of various metallic plating aspects to the manufacturing/fabrication (section 5.3.1) of its circuits/architecture (e.g., those explicitly mentioned in relation to claim 1) but not specifically a CMOS element as recited. Rather, the Examiner relies upon BOZOVICH to teach what Brignon lacks, see e.g., Bozovich’s slides 8 and 11 teaching integration of a silicon integrated photonics implementation with CMOS electronics.
Both Brignon and Bozovich relate to a photonics system implementation through the managing of light, power, radiation, and the like. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to extend manufacturing aspects to a circuit such as Brignon’s using materials and techniques as taught by Bozovich with a reasonable expectation of success.
9. Claims 7-10, 19-21, and 25-27 are rejected under 35 U.S.C. 103 as being unpatentable over Brignon in view of Non-Patent Literature “Solving complex optimization problems with a coherent Ising machine” (“Takesue”).
Regarding claim 7, Brignon teaches the photonic processor computing engine device of claim 1, as discussed above. Brignon further teaches the additional limitation wherein the electronic control circuit controls the optical phase modulators of the optical phased array (OPA) (as discussed above in relation to claim 1: section 5.1 on page 138: emitters/fibers having individual phase control, as further and more extensively clarified in section 5.3.3 on page 155 (“Phase modulators are key elements for the control of the phase of the beam from each fiber. Different solutions can be employed for this purpose.” and that for the reference’s experiment, see section 5.4’s discussion of PLZT-based electro-optic phase modulators (which is illustrated in Figure 5.15 via the “16 x 4 channels PLZT phase modulators”)) but is silent as to doing so to map a computationally hard problem as an Ising spin glass matrix to the radiating pixels. Rather, the Examiner relies upon TAKESUE to teach what Brignon lacks, see e.g., Takesue’s Figure 1 (page 2 of the reference) teaching a feedback loop for a photonics-type framework comparable to Brignon’s features discussed above in relation to claim 1, and where Takesue’s framework can be adapted to “find solutions for NP-hard” problems.
Brignon and Takesue are directed to comparable optical circuits with similar feedback aspects. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt Brignon’s framework in view of Takesue’s teachings, with a reasonable expectation of success, to solve a computational hard problem as Takesue teaches, e.g. to reap benefits of applying quantum-type frameworks to solve problems that are otherwise too intensive for classical computing frameworks.
Regarding claim 8, Brignon in view of Takesue teach the photonic processor computing engine device of claim 7, as discussed above. The aforementioned references further teach the additional limitations wherein the electronic control circuit controls the optical phase modulators to have phase values of either 0 or π as Ising spin values for the Ising spin glass matrix mapped to the radiating pixels (Takesue’s 1st page, 4th paragraph, discussing the use of phase values 0 or π with what is understood to be a coherent Ising machine).
Regarding claim 9, Brignon in view of Takesue teach the photonic processor computing engine device of claim 8, as discussed above. The aforementioned references further teach the additional limitations wherein the PIC further comprises an optical attenuator or amplifier, and the electronic control circuit independently controls each of the optical phase modulators and attenuator or amplifiers to independently control an amplitude and phase of each of the optical signal beams of the plurality of radiating pixels (Brignon’s section 5.5.1, on page 159, discussing an array of fiber amplifiers, as further clarified in the introduction portion of section 5.3 on page 147) to represent an Ising Spin Glass matrix of the Ising Spin Model mapped to the radiating pixels (Takesue’s 2nd – 4th paragraphs on its page 1).
Regarding claim 10, Brignon in view of Takesue teach the photonic processor computing engine device of claim 9, as discussed above. The aforementioned references further teach the additional limitations wherein the electronic feedback circuit is programmed to provide feedback of the measured intensity of the optical signal beams received by at least a defined portion of the focal plane array (FPA) to the electronic control circuit, and the electronic control circuit is programmed to process the feedback to adjust the setting of each of the optical phase modulators of the plurality of radiating pixels (as discussed above per claim 1, Brignon: section 5.3.2.2 on page 153 discussing a QWLSI (e.g., as shown in relation to a phase processing and feedback loop computer/controller in Figure 5.15 on page 157), where the QWLSI is understood to measure the phase and use it to correct a phase via the feedback loop, e.g. by providing a feedback loop signal to the PLZT-based electro-optic phase modulators (e.g., illustrated in Figure 5.15 via the “16 x 4 channels PLZT phase modulators”), and where the measurement of phase is performed as discussed in section 5.3 specifically on page 148 (“The
N fiber outputs are disposed in a matrix arrangement and collimated by a lens array. A small fraction of the output beams is sampled and launched to a phase sensor device in order to measure the piston-phase errors between the N fibers.”, where the sampling of output beams corresponds to the recitation for “a defined portion” of the FPA)).
Regarding claim 19, Brignon teaches the computer implemented method of claim 18, as discussed above. The aforementioned reference teaches the additional limitations for the method further comprising:
controlling, individually, each of the optical phase modulators such that optical signal beams radiating from each of the radiating pixels have binary phase values of either a first value or a second value (as discussed in relation to claim1: see Brignon’s discussion of near field, with fibers arranged per sections 5.2.2 - 5.2.2.1 (and shown in Figure 5.3 on page 142), which are characterized as having a phased difference per section 5.1 (specifically page 137) and clarified further in same section on the following page 138 as having “individual phase control”);
providing feedback of the measured intensity of the optical signal beams received by a defined portion of the focal plane array (FPA) to the optical phase modulators and processing the feedback signal to recalibrate the optical phase modulators of the plurality of radiating pixels to the condition correlated to the ground energy state ... mapped to the radiating pixels (as discussed in relation to claim 1: see Brignon’s section 5.3.2.2 on page 153 discussing a QWLSI (e.g., as shown in relation to a phase processing and feedback loop computer/controller in Figure 5.15 on page 157), where the QWLSI is understood to measure the phase and use it to correct a phase via the feedback loop, e.g. by providing a feedback loop signal to the PLZT-based electro-optic phase modulators (e.g., illustrated in Figure 5.15 via the “16 x 4 channels PLZT phase modulators”), and where the measurement of phase is performed as discussed in section 5.3 specifically on page 148 (“The N fiber outputs are disposed in a matrix arrangement and collimated by a lens array. A small fraction of the output beams is sampled and launched to a phase sensor device in order to measure the piston-phase errors between the N fibers.”, where the sampling of output beams corresponds to the recitation for “a defined portion” of the FPA), and further the Examiner notes section 5.4 beginning on page 156 as discussing “an ideal in-phase coherent summation of the 64 beamlets in a square lattice arrangement” and the determination of a deviation corresponding to efficiency degradation, which is subject to evaluation per the last two paragraphs of section 5.4 on page 158, as equivalent to the correlated “ground energy state” as further recited).
Brignon does not explicitly teach that the ground energy state is to of the Ising spin glass and rather, the Examiner relies upon Takesue to teach what Brignon otherwise lacks, see e.g., Takesue’s 2nd – 4th paragraphs on its page 1.
Brignon and Takesue are directed to comparable optical circuits with similar feedback aspects. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt Brignon’s framework in view of Takesue’s teachings, with a reasonable expectation of success, to solve a computational hard problem as Takesue teaches, e.g. to reap benefits of applying quantum-type frameworks to solve problems that are otherwise too intensive for classical computing frameworks.
Regarding claim 20, the claim includes the same or similar limitations as claim 8 discussed above, and is therefore rejected under the same rationale.
Regarding claim 21, the claim includes the same or similar limitations as claim 9 discussed above, and is therefore rejected under the same rationale.
Regarding claim 25, the claim includes the same or similar limitations as claim 19 discussed above, and is therefore rejected under the same rationale.
Regarding claim 26, the claim includes the same or similar limitations as claim 8 discussed above, and is therefore rejected under the same rationale.
Regarding claim 27, the claim includes the same or similar limitations as claim 9 discussed above, and is therefore rejected under the same rationale.
9. Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Brignon in view of Non-Patent Literature “Coupling strategies for silicon photonics integrated chips” (“Marchetti”).
Regarding claim 15, Brignon teaches the photonic processor computing engine device of claim 1, as discussed above. The present claim modifies claim 1 to recite not one PIC element but an array of PIC elements, see e.g. the language for a plurality of the photonic integrated circuits (PIC), each comprising: what are essentially the limitations to claim 1 as already discussed above and further wherein the focal plane array (FPA) is positioned to receive the optical signal beams transmitted from the plurality of radiating pixels of one or more of the plurality of photonic integrated circuits (PIC). As discussed above, Brignon teaches what claim 1 requires but Brignon does not further teach the joining of numerous instances of PICs, e.g. as the claim requires. To teach what Brignon lacks, the Examiner then relies upon MARCHETTI: pages 201-202 teaching edge and vertical coupling configurations. The Examiner reasons that the joining of PIC instances, as permitted by either configuration, would read on the recited features of the present claim.
Regarding claim 16, Brignon in view of Marchetti teach the photonic processor computing engine device of claim 15, as discussed above. The aforementioned references further teach the additional limitations further comprising: a plurality of focal plane arrays (FPA), each positioned to receive the optical signal beams transmitted from the plurality of radiating pixels of one or more of the plurality of photonic integrated circuits (PIC) (see Marchetti as discussed above in relation to claim 15).
10. Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Brignon in view of Non-Patent Literature “Photonic simulation of entanglement growth and engineering after a spin chain quench” (“Pitsios”).
Regarding claim 22, Brignon teaches the method of claim 18, as discussed above. While Brignon teaches phase modulation and, implicitly, different values possible as subject to feedback correction, the reference does not teach specifically the further limitation wherein the optical phase modulators have phase values from −π to π as values in the XY Hamiltonian model for each radiating pixel. Rather, the Examiner relies upon PITSIOS to teach what Brignon lacks, see e.g., Pitsios: page 4’s 1st column in its 1st paragraph: “The quenching from the Ising Hamiltonian to the XY Hamiltonian is simulated when the initial state is injected in the quantum transport chip.”
Brignon and Pitsios are directed to comparable optical circuits with similar feedback aspects. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt Brignon’s framework in view of Pitsios’s quenching, with a reasonable expectation of success, to provide the advantage of benchmarking features of solvable problems as discussed in Pitsios’s Introduction section.
Regarding claim 23, Brignon teaches the method of claim 18, as discussed above. Brignon teaches the additional limitations wherein PIC further comprises an optical attenuator or amplifier, and each of the optical phase modulators and optical attenuators/amplifiers are independently controlled to control an amplitude and phase of each radiating optical signal beam of each of the plurality of radiating pixels to represent a model mapped to the radiating pixels (Brignon’s section 5.5.1, on page 159, discussing an array of fiber amplifiers, as further clarified in the introduction portion of section 5.3 on page 147) but not specifically an XY Hamiltonian model as is further recited. Rather, the Examiner relies upon PITSIOS to teach what Brignon lacks, see e.g., Pitsios: page 4’s 1st column in its 1st paragraph: “The quenching from the Ising Hamiltonian to the XY Hamiltonian is simulated when the initial state is injected in the quantum transport chip.”
Brignon and Pitsios are directed to comparable optical circuits with similar feedback aspects. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt Brignon’s framework in view of Pitsios’s quenching, with a reasonable expectation of success, to provide the advantage of benchmarking features of solvable problems as discussed in Pitsios’s Introduction section.
11. Claims 11-12 and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Brignon in view of Takesue and further in view of Pitsios.
Regarding claim 11, Brignon in view of Takesue teach the photonic processor computing engine device of claim 7, as discussed above. While Brignon teaches phase modulation and, implicitly, different values possible as subject to feedback correction, the reference does not teach specifically the further limitation wherein the electronic control circuit controls the optical phase modulators to have phase values of from −π to π as values for an XY Hamiltonian model mapped to the radiating pixels. Rather, the Examiner relies upon PITSIOS to teach what Brignon lacks, see e.g., Pitsios: page 4’s 1st column in its 1st paragraph: “The quenching from the Ising Hamiltonian to the XY Hamiltonian is simulated when the initial state is injected in the quantum transport chip.”
Brignon and Pitsios are directed to comparable optical circuits with similar feedback aspects. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adapt Brignon’s framework in view of Pitsios’s quenching, with a reasonable expectation of success, to provide the advantage of benchmarking features of solvable problems as discussed in Pitsios’s Introduction section.
Regarding claim 12, Brignon in view of Takesue and further in view of Pitsios teach the photonic processor computing engine device of claim 11, as discussed above. Brignon teaches the additional limitations wherein PIC further comprises an optical attenuator or amplifier, and each of the optical phase modulators and optical attenuators/amplifiers are independently controlled to control an amplitude and phase of each radiating optical signal beam of each of the plurality of radiating pixels to represent a model mapped to the radiating pixels (Brignon’s section 5.5.1, on page 159, discussing an array of fiber amplifiers, as further clarified in the introduction portion of section 5.3 on page 147) but not specifically an XY Hamiltonian model as is further recited. Rather, the Examiner relies upon PITSIOS to teach what Brignon lacks, see e.g., Pitsios: page 4’s 1st column in its 1st paragraph: “The quenching from the Ising Hamiltonian to the XY Hamiltonian is simulated when the initial state is injected in the quantum transport chip.”
Regarding claim 28, the claim includes the same or similar limitations as claim 11 discussed above, and is therefore rejected under the same rationale.
Regarding claim 29, the claim includes the same or similar limitations as claim 12 discussed above, and is therefore rejected under the same rationale.
Conclusion
12. The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure:
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US 20200185120 A1
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EP 3761528 A1
TW 202107788 A
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13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHOURJO DASGUPTA whose telephone number is (571)272-7207. The examiner can normally be reached M-F 8am-5pm CST.
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/SHOURJO DASGUPTA/ Primary Examiner, Art Unit 2144