Prosecution Insights
Last updated: April 19, 2026
Application No. 17/985,949

DEVICES AND METHODS FOR ENHANCED TIME SYNCHRONIZATION

Non-Final OA §103§112
Filed
Nov 14, 2022
Examiner
HSU, BAILOR CHIA-JONG
Art Unit
2461
Tech Center
2400 — Computer Networks
Assignee
Intel Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
94%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
274 granted / 308 resolved
+31.0% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
29 currently pending
Career history
337
Total Applications
across all art units

Statute-Specific Performance

§101
2.8%
-37.2% vs TC avg
§103
52.2%
+12.2% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
28.9%
-11.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 308 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2, 5, and 12-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 2, the claim recites the term “and/or” in line 4, which renders the scope of the claim indefinite. To be more specific, it is unclear as to whether the update of the clock follower device comprises “an update of a clock value of the clock of the follower device…”, “an update of a clock rate of the clock of the follower device…”, or both. For examination purposes, the term will be interpreted as “or.” Regarding claim 5, the claim recites the term “and/or” in line 4, which renders the scope of the claim indefinite. To be more specific, it is unclear as to whether the clock drift between the clock of the follower device and the clock of the leader device comprises “a drift of a clock value of the clock of the follower device…”, “a drift of a clock rate of the clock of the follower device…”, or both. For examination purposes, the term will be interpreted as “or.” Regarding claim 12, the claim recites the term “and/or” in line 10, which renders the scope of the claim indefinite. To be more specific, it is unclear as to whether each update value is representative of “an update of the clock value of the clock of the follower device…”, “an update of the clock rate of the clock of the follower device…”, or both. For examination purposes, the term will be interpreted as “or.” Additionally, the claim recites the term “and/or” in line 12, which renders the scope of the claim indefinite. To be more specific, it is unclear as to whether the update value is used for updating the clock value of the clock of the follower device, the clock rate of the clock of the follower device, or both. For examination purposes, the term will be interpreted as “or.” Regarding claim 13, the claim recites the term “and/or” in line 3, which renders the scope of the claim indefinite. To be more specific, it is unclear as to whether the defined update value is used to update the clock value of the clock of the follower device, the clock rate of the clock of the follower device, or both. For examination purposes, the term will be interpreted as “or.” Regarding claim 14, the claim recites the term “and/or” in line 3, which renders the scope of the claim indefinite. To be more specific, it is unclear as to whether the update value is used for updating the clock value of the clock of the follower device, the clock rate of the clock of the follower device, or both. For examination purposes, the term will be interpreted as “or.” Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-6, 15, 17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Haartsen et al. (US 2010/0112950 A1), hereinafter referred to as Haartsen, in view of Aweya (US 2015/0092793 A1). Regarding claim 1, Haartsen teaches a device comprising a processor coupled to storage, wherein the processor is configured to: detect a failed reception, at a follower device, of time synchronization information providing an update of a clock of the follower device for synchronization to a clock of a leader device (Haartsen – Paragraph [0050], note a slave unit in sniff mode may wake up periodically in order to listen to transmissions from the master unit and in order to re-synchronize its clock offset, if a packet reception fails, e.g. due to multipath fading, the master unit may re-transmit at a different frequency but still in the same sniff interval, packet exchange may provide timing information to update the clock of the slave unit); determine a predefined drift threshold (Haartsen – Paragraph [0060], note the slave unit may remain in recovery scan until the link is re-established or when a timeout TFASTRECOVERY has exceeded indicating the end of the fast recovery state, assuming a worst case mutual drift of e.g. 40 ppm, the timeout TFASTRECOVERY may, preferably, be set to about 30 minutes); and instruct an update of the clock of the follower device based on time synchronization information previously received at the follower device (Haartsen – Paragraph [0050], note when no packets are exchanged, the clocks of the master unit and slave unit, respectively, may remain loosely in sync due to the previous adjustments, clock information should, therefore, preferably be stored during a previous connection stage, the clock information may, e.g., be stored as a time offset to its own native clock, the offset in the slave unit may have to be adjusted to compensate for drift, the reception of packets sent by the master unit may be used to adjust the offset). Haartsen does not teach determining whether a clock drift between the clock of the follower device and the clock of the leader device is less than a predefined drift threshold; and instructing an update of the clock of the follower device in the case that the clock drift is less than the predefined drift threshold. In an analogous art, Aweya teaches determining whether a clock drift between the clock of the follower device and the clock of the leader device is less than a predefined drift threshold (Aweya – Paragraph [0058], note determining the skew of the slave clock according to the updated state equation, and if the skew is less than a predetermined level); and instructing an update of the clock of the follower device in the case that the clock drift is less than the predefined drift threshold (Aweya – Paragraph [0058], note only proceeding to adjust the actual time of the slave clock based on the updated state equation if the skew is less than a predetermined level). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Aweya into Haartsen in order to update the clock of a slave/follower when the drift/skew is below a threshold, and additionally verify time offset estimates for use in clock alignment, reducing clock update errors (Aweya – Paragraph [0059]). Regarding claim 2, the combination of Haartsen and Aweya, specifically Haartsen teaches wherein the update of the clock of the follower device for synchronization to the clock of the leader device comprises an update of a clock value of the clock of the follower device for synchronization to a clock value of the clock of the leader device or an update of a clock rate of the clock of the follower device for synchronization to a clock rate of the clock of the leader device (Haartsen – Paragraph [0050], note the packet exchange may provide timing information to update the clock of the slave unit). Regarding claim 3, the combination of Haartsen and Aweya, specifically Haartsen teaches wherein the processor is configured to detect the failed reception of time synchronization information by detecting a failed reception of a time synchronization packet at the follower device (Haartsen – Paragraph [0054], note a unit (master or slave) may move from connected state to pending state when a loss of link is experienced (a timeout on the number of missed packets in a row, such as packets containing time information, see Paragraph [0050])). Regarding claim 4, Haartsen does not teach wherein the time synchronization packet is or comprises a generic Precision Time Protocol packet. In an analogous art, Aweya teaches wherein the time synchronization packet is or comprises a generic Precision Time Protocol packet (Aweya – Paragraph [0008], note IEEE 1588 PTP messages; Paragraph [0025], note PTP message exchange, the slave possesses all four timestamps, which may be used to compute the offset of the slave’s clock with respect to the clock reference in the master). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Aweya into Haartsen for the same reason as claim 1 above. Regarding claim 5, Haartsen does not teach wherein the clock drift between the clock of the follower device and the clock of the leader device comprises a drift of a clock value of the clock of the follower device with respect to a clock value of the clock of the leader device or a drift of a clock rate of the clock of the follower device with respect to a clock rate of the clock of the leader device. In an analogous art, Aweya teaches wherein the clock drift between the clock of the follower device and the clock of the leader device comprises a drift of a clock value of the clock of the follower device with respect to a clock value of the clock of the leader device or a drift of a clock rate of the clock of the follower device with respect to a clock rate of the clock of the leader device (Aweya – Paragraph [0056], note skew of the slave clock compared to the master clock using the estimated variance of the measurement noise following receipt of each timing message in the slave device). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Aweya into Haartsen for the same reason as claim 1 above. Regarding claim 6, the combination of Haartsen and Aweya, specifically Haartsen teaches wherein the processor is configured to detect the failed reception of time synchronization information at the follower device by determining that a time synchronization interval has elapsed without the follower device receiving time synchronization information during the time synchronization interval (Haartsen – Paragraph [0054], note a unit (master or slave) may move from connected state to pending state when a loss of link is experienced (a timeout on the number of missed packets in a row, such as packets containing time information, see Paragraph [0050])). Regarding claim 15, Haartsen does not teach wherein the processor is further configured to: instruct the follower device to process control information using the updated clock of the follower device . In an analogous art, Aweya teaches wherein the processor is further configured to: instruct the follower device to process control information using the updated clock of the follower device (Aweya – Paragraph [0055], note by combining features of Sync-E and IEEE 1588 PTP, the method may allow the slave to accurately measure the actual PDV of PTP messages (control information) arriving at the slave, the slave can then correctly adjust its clock while compensating for the actual delay variations). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Aweya into Haartsen for the same reason as claim 1 above. Regarding claim 17, Haartsen teaches a device comprising a processor coupled to storage (Haartsen – Fig. 1B; Paragraph [0049], note baseband processor 203, controller 204; Paragraph [0173], note implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions), wherein the processor is configured to: instruct an update of a clock of a follower device in absence of time synchronization information from a leader device by using time synchronization information previously received at the follower device (Haartsen – Paragraph [0050], note a slave unit in sniff mode may wake up periodically in order to listen to transmissions from the master unit and in order to re-synchronize its clock offset, packet exchange may provide timing information to update the clock of the slave unit, when no packets are exchanged, the clocks of the master unit and slave unit, respectively, may remain loosely in sync due to the previous adjustments, clock information should, therefore, preferably be stored during a previous connection stage, the clock information may, e.g., be stored as a time offset to its own native clock, the offset in the slave unit may have to be adjusted to compensate for drift, the reception of packets sent by the master unit may be used to adjust the offset). Haartsen does not teach instructing an update of a clock of a follower device to continue processing time-critical control information at the follower device. In an analogous art, Aweya teaches instructing an update of a clock of a follower device to continue processing time-critical control information at the follower device (Aweya – Paragraph [0055], note by combining features of Sync-E and IEEE 1588 PTP, the method may allow the slave to accurately measure the actual PDV of PTP messages (control information) arriving at the slave, the slave can then correctly adjust its clock while compensating for the actual delay variations). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Aweya into Haartsen in order to update the clock of a slave/follower and additionally verify time offset estimates for use in clock alignment, reducing clock update errors (Aweya – Paragraph [0059]). Regarding claim 19, Haartsen teaches a device comprising a processor coupled to storage (Haartsen – Fig. 1B; Paragraph [0049], note baseband processor 203, controller 204; Paragraph [0173], note implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions), wherein the processor is configured to: determine if a time synchronization at a follower device fails, wherein the time synchronization causes an update of a clock value of a clock of the follower device for synchronization to a further clock of another device (Haartsen – Paragraph [0050], note a slave unit in sniff mode may wake up periodically in order to listen to transmissions from the master unit and in order to re-synchronize its clock offset, packet reception fails (for receiving timing information and thus synchronization), e.g. due to multipath fading, packet exchange may provide timing information to update the clock of the slave unit); if it is determined that the time synchronization fails, determine a predefined drift threshold (Haartsen – Paragraph [0060], note the slave unit may remain in recovery scan (non-synchronized state) until the link is re-established or when a timeout TFASTRECOVERY has exceeded indicating the end of the fast recovery state, assuming a worst case mutual drift of e.g. 40 ppm, the timeout TFASTRECOVERY may, preferably, be set to about 30 minutes); and update the clock value of the clock using time synchronization information previously received at the follower device (Haartsen – Paragraph [0050], note when no packets are exchanged, the clocks of the master unit and slave unit, respectively, may remain loosely in sync due to the previous adjustments, clock information should, therefore, preferably be stored during a previous connection stage, the clock information may, e.g., be stored as a time offset to its own native clock, the offset in the slave unit may have to be adjusted to compensate for drift, the reception of packets sent by the master unit may be used to adjust the offset). Haartsen does not teach determining whether a drift between the clock and the further clock is less than a predefined drift threshold; and updating the clock value of the clock using time synchronization information if it is determined that the drift is less than the predetermined drift threshold. In an analogous art, Aweya teaches determining whether a drift between the clock and the further clock is less than a predefined drift threshold (Aweya – Paragraph [0058], note determining the skew of the slave clock according to the updated state equation, and if the skew is less than a predetermined level); and updating the clock value of the clock using time synchronization information if it is determined that the drift is less than the predetermined drift threshold (Aweya – Paragraph [0058], note only proceeding to adjust the actual time of the slave clock based on the updated state equation if the skew is less than a predetermined level). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Aweya into Haartsen in order to update the clock of a slave/follower when the drift/skew is below a threshold, and additionally verify time offset estimates for use in clock alignment, reducing clock update errors (Aweya – Paragraph [0059]). Regarding claim 20, the claim is interpreted and rejected for the same reason as claim 3 above. Claims 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Haartsen in view of Aweya as applied to claim 1 above, and further in view of Joseph et al. (US 2020/0228220 A1), hereinafter referred to as Joseph. Regarding claim 16, the combination of Haartsen and Aweya does not teach wherein the follower device and the leader device are Time Sensitive Networking-enabled devices. In an analogous art, Joseph teaches wherein the follower device and the leader device are Time Sensitive Networking-enabled devices (Joseph – Fig. 4; Paragraph [0158], note TSN 405, endpoints 415, and nodes 435). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Joseph into the combination of Haartsen and Aweya in order to improve flexibility of PTP time synchronization and reduce signaling overhead (Joseph – Paragraph [0103]). Regarding claim 18, the claim is interpreted and rejected for the same reason as claim 16 above. Allowable Subject Matter Claims 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 12-14 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Applicant’s dependent claims recite wherein the processor is configured to determine whether the clock drift between the clock of the follower device and the clock of the leader device is less than the predefined drift threshold by: determining a plurality of drift values each corresponding to previous time synchronization information received at the follower device prior to the failed reception of the time synchronization information, wherein each drift value is representative of a difference between a clock value of the clock of the follower device and a clock value of the clock of the leader device prior to the update instructed by the corresponding time synchronization information; and determining whether the clock drift between the clock of the follower device and the clock of the leader device is less than the predefined drift threshold based on the plurality of drift values; and wherein to instruct the update of the clock of the follower device based on time synchronization information previously received at the follower device the processor is configured to: determine a plurality of update values each corresponding to previous time synchronization information received at the follower device prior to the failed reception of the time synchronization information, wherein each update value is representative of an update of the clock value of the clock of the follower device instructed by the corresponding time synchronization information or of an update of the clock rate of the clock of the follower device instructed by the corresponding time synchronization information; and define an update value for updating the clock value or the clock rate of the clock of the follower device based on the plurality of update values, which are neither taught nor suggested by the prior art. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zheng et al. (US 8,995,473 B2) discloses determining errors and phase correction for slave clock nodes. Gudipati et al. (US 9,385,930 B2) discloses detecting anomalies in PTP synchronization for slave clocks. McGaughey (US 9,651,984 B2) discloses sending SYNC timestamps for removing synchronization errors. Abdullah et al. (US 10,355,799 B2) discloses synchronizing a slave clock to a master clock based on time difference. Wang (US 11,063,738 B1) discloses NTP/PTP master device that acts as a reference clock for slave devices. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAILOR C HSU whose telephone number is (571)272-1729. The examiner can normally be reached Mon-Fri. 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Vu can be reached at (571)-272-3155. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BAILOR C HSU/Primary Examiner, Art Unit 2461
Read full office action

Prosecution Timeline

Nov 14, 2022
Application Filed
Jan 10, 2023
Response after Non-Final Action
Jan 24, 2026
Non-Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
94%
With Interview (+5.1%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 308 resolved cases by this examiner. Grant probability derived from career allow rate.

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