DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because:
Figure 5 illustrates component 510 as register. However, specification [00120-00123] describes such 510 as registers. Examiner suggests amending the label of 510 as “registers”.
Figure 5 illustrates
2
π
-
64
, but specification [00116] describes “2x -64”.
Figure 5 illustrates the final output bit stream as 00100000, but specification [00113] describes the final output bit stream as 00100010. Examiner suggests amending figure 5 as described in the specification as the bit stream is accumulated of {00010000}, {00001000}, {00001000}, {00000010}. Thus, the correct accumulated result is 34 or 00100010.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-18 are objected to because of the following informalities:
Claim 1 line 5 “each having “N” layers” should be “each of the first bit streams having “N” layers” to clearly identify “each” is referring to each of the first bit streams as recited in claim 9 line 11.
Claim 1 line 7 “each having “N” layers” should be “each of the second bit streams having “N” layers” to clearly identify “each” is referring to each of the second bit streams as recited in claim 9 line 11.
claim 1 line 13; claim 9 line 21 "the combinations" should be "the possible combinations" as antecedently recited.
Claim 5 line 5 "the weight parameter or the input data" should be "the received weight parameter or the received input data" as antecedently recited.
Claim 5 line 6; claim 14 line 5 "the quantization scheme" should be "the predetermined quantization scheme" as antecedently recited.
Claim 7 line 2 "nPowerode" should be "node" as described in [00118].
Claim 8 line 2 "the quantization method of claim 1" should be “the processor-implemented artificial neural network quantization scheme implementation method of claim 1” or just “the method of claim 1” for clarification purposes.
Claim 9 line 7 "the registers" should be "the plurality of registers" as antecedently recited.
Dependent claims are also objected for inheriting the same deficiencies in which claims they depend on.
Appropriate correction is required.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 10-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 line 1 recites "the XNOR operator". It is unclear whether this limitation refers to the at least one XNOR operator or the corresponding XNOR operator as antecedently recited. For examination purposes, Examiner interprets as the at least one XOR operator.
Claim 11 line 1 recites "the popcounter". It is unclear whether this limitation refers to the at least one popcounter or the corresponding popcounter as antecedently recited. For examination purposes, Examiner interprets as the at least one popcounter.
Claim 11 line 2 "the XNOR operation". It is unclear whether this is referring to the XNOR operation recited in claim 10 line 2 or the XNOR operation recited in claim 9 line 14". For examination purposes, Examiner interprets as the XNOR operation recited in claim 10 line 2.
Dependent claims are also rejected for inheriting the same deficiencies in which claims they depend on.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 1 recites a method claim
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites limitations cover mathematical calculations, relationship, and/or formula, such as a method comprising: encoding the received input data corresponding to a first M-dimensional vector into first bit streams, each having "N" layers, based on a predetermined quantization scheme; encoding the received weight parameter corresponding to a second M-dimensional vector into second bit streams, each having "N" layers, based on the predetermined quantization scheme (see at least figure 4 [0091] illustrates the steps of encoding input data and weight into bit streams based on a quantization scheme, also see [0012] describes quantization equation); applying a corresponding first bit stream and a corresponding second bit stream to a binary neural network (BNN) operator, for each of possible combinations between layers of the first bit streams and layers of the second bit streams (see at least figure 4 [00110-00113] describe XNOR operation and the popcount operation, which is counting number of ones, of the BNN operator that is applied to each first and second bit streams. thus a BNN operator is interpreted as a mathematical operations of binary neural network); receiving a dot product result output based on a result obtained by shifting a BNN operation result corresponding to each of the combinations by a number of corresponding bits and accumulating the shifted BNN operation result, from the BNN operator (see at least figure 4 [00110-00116] describes a result obtained by shifting the XNOR result and counting number of ones for each combination and accumulated the BNN results); and quantizing the dot product result based on the predetermined quantization scheme ([00117-00118] describe the dot product being quantized, which is a mathematical operation). Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites a processor-implemented artificial neural network quantization scheme implementation method and binary neural network (BNN) operator (e.g., where the BNN operator is alternatively being interpreted as additional element). However, such additional element is recited at a high level of generality, i.e., as using computer component to perform a computer function of processing data and mere generally linking the use of the abstract idea into a particular technological environment or field of use, such as artificial neural network. Furthermore, the claim also recites the step of receiving data, such as input data and weight parameter, but such limitation is considered as insignificant extra solution activity (e.g., mere data gathering). Such additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer element. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a computer component. The same conclusion is reached in step 2B, i.e., mere instructions to apply an exception on computer element cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The step of receiving data is considered to be insignificant extra-solution activity in step 2A, and are determined to be well-understood, routine, conventional activity in the field. Court decisions cited in MPEP 2106.05(d)(II) section (i), indicate that mere receiving or transmitting data over a network, is well-understood, routing, conventional function when it is claimed in a merely generic manner. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 further recites wherein the applying of the corresponding first bit stream and the corresponding second bit stream to the BNN operator comprises: performing an XNOR operation between each of layers of one of the first bit streams and each of layers of one of the second bit streams in an alternating manner, with the BNN operator; and performing a popcount operation on each of results obtained by performing the XNOR operation. Such limitations cover mathematical calculations, relationship, and/or formula (see at least figure 4 illustrating performing XNOR operation on the bit streams and performing popcount operation, which is counting of ones in the bit streams. Thus, such operations are mathematical operations). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 further recites wherein the number of corresponding bits is determined based on layers of the corresponding first bit streams and layers of the corresponding second bit streams calculated for the BNN operation result. Such limitations cover mathematical calculations, relationship, and/or formula (such limitation merely describes determining the number of bits for shifting, which is mathematical calculations). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 further recites wherein the predetermined quantization scheme is a scheme in which at least one positive quantization level and at least one negative quantization level are completely symmetric to each other by excluding zero from quantization levels. Such limitations cover mathematical calculations, relationship, and/or formula (merely describing the quantization scheme, which is a mathematical algorithm, see at least [0050-0051]). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 further recites wherein: the received input data and the received weight parameter are quantized based on the following equation: where v denotes the weight parameter or the input data, s denotes a step side to determine a quantization range of the quantization scheme, and b denotes a predetermined number of quantization bits. Such limitations cover mathematical calculations, relationship, and/or formula (describing mathematical equation for quantization). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 further recites wherein the received weight parameter is trained and determined through at least one of quantization-aware training, post-training quantization, or data-free quantization, such limitations cover mathematical calculations, relationship, and/or formula (such limitation merely describes the weight data being determined using mathematical algorithm). Alternatively, such limitation is at most considered as mere generally linking the use of the judicial exception into a particular environment or field of use, such as training parameter for a neural network, under step 2A prong two. Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 further recites transmitting the quantized dot product result to a next nPowerode. Such additional element is considered as insignificant extra/post solution activity under step 2A prong two as mere data gathering, and determined to be well-understood, routine, and conventional activity under step 2B (see at least MPEP 2106.05(d)(II) section (i), indicate that mere receiving or transmitting data over a network). Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 8 further recites a non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform the quantization method of claim 1. Such additional elements are recited at a high level of generality, e.g., mere computer components for performing computer functions of storing instructions and executing instructions to perform the mathematical operations, and amount to no more than mere instructions to apply the judicial exception using computer components (see MPEP 2106.05(f)). Thus, the claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 9 recites an apparatus claim
Under Prong One of Step 2A of the USPTO current eligibility guidance (MPEP 2106), the claim recites limitations cover mathematical calculations, relationship, and/or formula, such as first bit streams, into which input data corresponding to a first M-dimensional vector is encoded based on a predetermined quantization scheme, second bit streams, into which a weight parameter corresponding to a second M-dimensional vector is encoded based on the predetermined quantization scheme, each of the first bit streams and the second bit streams having "N" layers (see at least figure 4 [0091] illustrates the steps of encoding input data and weight into bit streams based on a quantization scheme, also see [0012] describes quantization equation); for each of possible combinations between layers of the first bit streams and layers of the second bit streams: perform an XNOR operation between a corresponding first bit stream and a corresponding second bit stream, apply a popcount operation to a result of the XNOR operation (see at least figure 4 [00110-00113] describe XNOR operation and the popcount operation, which is counting number of ones, of the BNN operator that is applied to each first and second bit streams); shift a result of the popcount operation by a number of bits corresponding to a corresponding combination, and perform an accumulation operation on shifted results of popcount operations corresponding to the combinations, and wherein a dot product result between the input data and the weight parameter is output based on a result of the accumulation operation. (see at least figure 4 [00110-00116] describes a result obtained by shifting the XNOR result and counting number of ones for each combination and accumulated the BNN results). Therefore, the claim includes limitations that fall within the “Mathematical Concepts” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The claim additionally recites an apparatus, comprising: a plurality of registers; at least one XNOR operator; at least one popcounter; at least one shifter; and at least one accumulator, a corresponding XNOR operator; a corresponding popcounter; a corresponding shifter; and a corresponding accumulator. However, such additional element is recited at a high level of generality, i.e., as using computer components to perform computer function of storing and processing data, and such additional elements are merely added to simply perform the abstract idea of performing XNOR, pop count, shifting, and accumulating operations. Furthermore, the step of storing data, such as first and second bit streams is considered as insignificant extra solution activity (e.g., mere data gathering). Such additional elements fail to provide a meaningful limitation on the judicial exception, and amount to no more than mere instructions to apply the exception using computer elements. Thus, the claim is directed to an abstract idea.
Under Step 2B, as discussed with respect to Prong Two of Step 2A, the additional elements in the claim amount no more than mere instructions to apply the exception using a computer component. The same conclusion is reached in step 2B, i.e., mere instructions to apply an exception on computer element cannot integrate a judicial exception into a practical application at step 2A or provide an inventive concept that is furnished by an element or combination of elements that is recited in the claim in addition to (beyond) the judicial exception. The step of storing data is considered to be insignificant extra-solution activity in step 2A, and are determined to be well-understood, routine, conventional activity in the field. Court decisions cited in MPEP 2106.05(d)(II) section (iv), indicate that mere storing and retrieving information in memory, is well-understood, routing, conventional function when it is claimed in a merely generic manner. Thus, the additional element fails to ensure the claim as a whole amount to significantly more than the judicial exception itself. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claims 10-16 recite apparatus claims that would practice the method claims 2-7. Thus, they are rejected for the same reasons.
Claim 17 further recites, wherein the corresponding first bit stream and the corresponding second bit stream are applied to a binary neural network (BNN) operator for each of the possible combinations between the layers of the first bit streams and the layers of the second bit streams. Such limitations cover mathematical calculations, relationship, and/or formula (see at least figure 4 [00110-00113] describe XNOR operation and the popcount operation, which is counting number of ones, of the BNN operator that is applied to each first and second bit streams). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 18 further recites wherein an XNOR-popcount operation is alternately performed on each of an upper bit stream and a lower bit stream of the input data and each of an upper bit stream and a lower bit stream of the weight parameter. Such limitations cover mathematical calculations, relationship, and/or formula (see at least figure 4 illustrates the XNOR popocunt operation being performed alternately to generate a dot product result). The claim does not recite additional element that would integrate the judicial exception into a practical application under step 2A prong two or ensure the claim as a whole amount to significantly more than the judicial exception itself under step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Allowable Subject Matter
Claims 1-18 would be allowable if rewritten or amended to overcome the claims objections, rejections under 35 U.S.C. 112(b) and 101 as set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 1 and 9, prior art of records does not teach or suggest a combination of limitations, such as encoding received input data and weight data into first and second bit streams, apply a corresponding first bit stream and second bit stream to a BNN operator for each of possible combinations between layers of the first bit streams and layers of the second bit streams and receiving a dot product result based on a result obtained by shifting a BNN operation result corresponding to each of the combinations by a number of corresponding bits, and quantizing the result of dot product based on the predetermined quantization scheme.
Roy et al - US 20210150313 teaches a system and method for performing dot product based on XNOR and pop count operation. Figure 5b illustrates the input data and weight parameter are being encoded into first and second bit streams, each having N layers, wherein the weight and input data are encoded to have bitstreams of mask and bitstreams of values, where masks are AND together and values are XNOR together. Figure 6 further illustrates the MAC operation where the results of AND and XNOR operations are fed into popcount to count the number of 1. However, as illustrated in figure 6, Roy only performs the shift operation on the result of the XNOR operation for one of the bitstream of values, but does not perform shift operation on AND operation. Thus, Roy does not teach or suggest the step of receiving a dot product result based on a result obtained by shifting a BNN operation result corresponding to each of the combinations by a number of corresponding bits as required in the claims.
Nealis - US 20180307950 teaches a system and method for performing XNOR popcount based MAC operation as illustrated in figure 21, having registers for storing input data, XNOR unit and pop count unit to perform XNOR and popcount operations and registers to store result. However, Nealis does not teach or suggest encoding received input data and weight data into first and second bit streams, apply a corresponding first bit stream and second bit stream to a BNN operator for each of possible combinations between layers of the first bit streams and layers of the second bit streams and receiving a dot product result based on a result obtained by shifting a BNN operation result corresponding to each of the combinations by a number of corresponding bits, and quantizing the result of dot product based on the predetermined quantization scheme.
Zhou - NPL DOREFA-NET: TRAINING LOW BITWIDTH CONVOLU TIONAL NEURAL NETWORKS WITH LOW BITWIDTH GRADIENTS (IDS filed on 04/20/2026) - teaches an approach of performing convolution using low bitwidth neural network. Page 2 section 2.1 describes x and y being encoded into a bit stream x and y, and page 3 further describes the equations 3-4 for performing dot product by performing AND and bitcount operations followed by a multiplication of 2^m+k. However, Zhou does not teach x and y being encoded into first and second bit streams, apply a corresponding first bit stream and second bit stream to a BNN operator for each of possible combinations between layers of the first bit streams and layers of the second bit streams and receiving a dot product result based on a result obtained by shifting a BNN operation result corresponding to each of the combinations by a number of corresponding bits, and quantizing the result of dot product based on the predetermined quantization scheme.
Pham - XNOR-Popcount, an Alternative Solution to the Accumulation Multiplication Method for Approximate Computations, to Improve Latency and Power - teaches an approach that implements and evaluates the performance of the XNOR-popcount design at the transistor-level. Pham further teaches that the Binary Neural Network (BNN) model uses binary values to represent training weights and input values to reduce the network model size while still achieving acceptable accuracy. Page 14 figure 4 further describes the method of XNOR popcount design to perform MAC operation. However, Pham does not teach or suggest encoding received input data and weight data into first and second bit streams, apply a corresponding first bit stream and second bit stream to a BNN operator for each of possible combinations between layers of the first bit streams and layers of the second bit streams and receiving a dot product result based on a result obtained by shifting a BNN operation result corresponding to each of the combinations by a number of corresponding bits, and quantizing the result of dot product based on the predetermined quantization scheme.
Anonymous authors NPL - CSQ: Centered Symmetric Quantization for Extremely Low Bit Neural Networks (IDS filed on 11/14/2022) - teaches a method for encoding input data v and x into bit streams, such that x is encoded into xh and xl, v is encoded into vh and vl as described in equation 14 page 6. Page 16 also describes the digital hardware implementation for using XNOR popcount based inner product method of binary neural network and further describes equations 30 and 35 to perform dot product using XNOR and popcount and shifting operation to calculate accumulation result s.
Conclusion
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/HUY DUONG/Examiner, Art Unit 2182 (571)272-2764
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