DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-3, 5-20 without traverse in the reply filed on 10/06/2025 is acknowledged. Claims 4, 21-25 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Objections
Claim 11 is objected to because of the following informalities:
Claim 11 recites “wherein the vertical semiconductor patterns are penetrate the source structure and extend into the substrate…” which should be “wherein the vertical semiconductor patterns [[are ]] penetrate the source structure and extend into the substrate…”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 5, 8-10, 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PARK et all. (US 2020/0303390 A1)
Regarding claim 1, PARK teaches,
PNG
media_image1.png
704
544
media_image1.png
Greyscale
9
A three-dimensional semiconductor memory device (Figs. 3-4, 5A-5B), comprising:
a stack structure (ST, Fig. 4, para [0075]) including electrode layers (EL, para [0053]) and electrode interlayer insulating layers (IL1, para [0053]) alternately stacked on a substrate (100, para [0054]);
vertical semiconductor patterns (including LSP & USP, FIG. 4, para [0083]) penetrating the stack structure;
and a gate insulating layer (VP, Fig. 4, para [0053]) between the vertical semiconductor patterns and the stack structure, the gate insulating layer including a blocking insulating layer (BK, FIG. 5A, para [0051]) and charge storing patterns (TL, FIG. 5A, para [0051]), the blocking insulating layer being adjacent to the stack structure,
the charge storing patterns (TL) being spaced apart from the stack structure (ST) and arranged along a surface of the blocking insulating layer (BK, see FIG. 5A),
the blocking insulating layer (BK) between the charge storing patterns (TL) and the stack structure (ST),
and wherein, as a distance to the blocking insulating layer decreases, widths of the charge storing patterns increase (looking at protruding portion of VP along the side surface of EL (i.e. from right side of FIG. 5A) , width of TL increases with decreasing distance of TL from BK, FIG. 5A).
Regarding claim 3, PARK teaches the device of claim 1 and further teaches, wherein each of the charge storing patterns has a side surface that is inclined with respect to a surface of the blocking insulating layer (portion of TL along a side surface of EL is curved/inclined with respect to portion of BL along a side surface of IL1, see FIG. 5A. A curved surface is inclined in a sense that the inclination of the curved surface at any point is given by the slope of the tangent at that point).
Regarding claim 5, PARK teaches the device of claim 1 and further teaches, wherein each of the electrode layers has a first vertical length (vertical length of EL marked as L1 in Fig. 5A below), each of the charge storing patterns has a second vertical length (vertical length of horizontal portion of TL marked as L2 in FIG. 5A below), and the second vertical length is smaller than the first vertical length (as seen in FIG. 5A below L2 < L1).
PNG
media_image2.png
704
544
media_image2.png
Greyscale
Regarding claim 8, PARK teaches the device of claim 1 and further teaches, wherein the gate insulating layer further comprises a passivation layer (FM, para [0057]), the passivation layer is between the charge storing patterns (TL) and the vertical semiconductor patterns (USP), and the passivation layer covers the charge storing patterns (as seen).
Regarding claim 9, PARK teaches the device of claim 8 and further teaches , wherein the passivation layer comprises at least one of SiN, SiO, SiON, or a metal oxide material, and the passivation layer has a single-layered structure or a multi-layered structure (FM may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer, para [0052]).
Regarding claim 10, PARK teaches the device of claim 8 and further teaches, wherein the gate insulating layer further comprises a tunnel insulating layer (TN, para [0051]) between the passivation layer (FM) and the vertical semiconductor patterns (USP).
Regarding claim 12, PARK teaches the device of claim 1 and further teaches, wherein the gate insulating layer further comprises: a capping layer (GI, FIG. 5A, para [0096]) covering the charge storing patterns (TL); a passivation layer (FM, para [0057]) covering the capping layer (GI); and a tunnel insulating layer (TN) covering the passivation layer (FM).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. and further in view of Kim et al. US 20180286876 A1
Regarding claim 2, PARK teaches the device of claim 1 but does not explicitly teach, wherein the charge storing patterns have a polygonal shape, when viewed in a plan view or a sectional view
But Kim’876 teaches,
A charge storage pattern 121a/121b (para [0032]) maybe trapezoid/polygonal shape in a cross-sectional view (FIG. 2).
It would have been obvious to one of ordinary skill in art before the effective filing date of the laimed invention to modify the shape of TL as a trapezoid/polygonal shape since a mere change in shape, size or form of a known element when it performs the same function and yields predictable results is an obvious design choice to a person of ordinary skill in the art (KSR v. Teleflex (550 U.S. 398, 2007).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. and further in view of PACHAMUTHU et al. (US 20160111434 A1).
Regarding claim 6, PARK teaches the device of claim 1 but does not explicitly teach, wherein each of the charge storing patterns is a doped silicon crystal pattern or an undoped silicon crystal pattern.
But park additionally teaches,
Charge storage layer TL may be formed of silicon nitride (para [0086])
charge storage regions 9 may comprise an insulating charge trapping material, such as silicon nitride segments and may be floating gates comprising semiconductor material (e.g., silicon) that may be formed by a metal induced crystallization process (see para [0028]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute silicon nitride with silicon formed by crystallization process (i.e. Silicon crystal) as a material of the charge trapping layer TL, according to teaching of PACHAMUTHU, since the court has held that a simple substitution of one known element for another (silicon crystal for silicon nitride) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). (Please see Smith v. Hayashi, 209 USPQ 754 (Bd. of Pat. Inter. 1980)).
Ordinary artisan would have been motivated to use crystalized silicon instead for charge trapping layer, in order to form a floating gate, as taught by PACHAMUTHU above.
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. and further in view of SON et al. (US 20210066344 A1).
Regarding claim 11, PARK teaches the device of claim 1 but does not explicitly teach, further comprising: a source structure between the substrate and the stack structure, wherein the vertical semiconductor patterns are penetrate the source structure and extend into the substrate, the gate insulating layer is below the source structure and between the vertical semiconductor patterns and the substrate, the source structure penetrates the gate insulating layer and is in contact with the vertical semiconductor patterns, the gate insulating layer further comprises dummy charge storing patterns below the source structure, and as a distance to the blocking insulating layer decrease, widths of the dummy charge storing patterns increase.
But SON teaches,
PNG
media_image3.png
764
590
media_image3.png
Greyscale
a source structure (380, para [0019], similar to SC2 in FIG. 5A of disclosure) between the substrate and the stack structure (stack of 414 & 165), wherein the vertical semiconductor patterns (240, para [0022], Fig. 4) penetrate the source structure and extend into the substrate (100, para [0019]), the gate insulating layer (including 230 & 280 , para [0022]) below the source structure (230 is extends below the 380) and between the vertical semiconductor patterns and the substrate, the source structure (380) penetrates the gate insulating layer ( in lateral direction) and is in contact with the vertical semiconductor patterns (as seen), the gate insulating layer further comprises dummy charge storing patterns (portion of 230 below 380) below the source structure,
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify PARK such that a source structure (380) between the substrate and the stack structure (ST), wherein the vertical semiconductor patterns (LSP, USP) penetrate the source structure (380) and extend into the substrate (100) and the gate insulating layer further comprises a gate insulating layer (230 below 380) below the source structure and between the vertical semiconductor patterns and the substrate, the source structure (380) penetrates the gate insulating layer and is in contact with the vertical semiconductor patterns , according to teaching of SON, in order to have memory cells having the characteristics of MLCs as taught by SON (para [0051]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over PARK et all. (US 2020/0303390 A1) in view of Zawodny et al. (US 20180130515 A1)
Regarding claim 20, PARK teaches,
…….a semiconductor device (FIGs. 1-4) including a peripheral circuit structure (including ROW DCR and COL DCR, FIG. 1),
a cell array structure (CAR, FIG. 1) on the peripheral circuit structure (FIG. 1), ……,
the cell array structure including a stack structure (ST, FIG. 4) on the substrate, vertical semiconductor patterns (LSP & USP, Fig. 4) penetrating the stack structure and placed adjacent to the substrate,
and a gate insulating layer (VP, FIG. 4) between the vertical semiconductor patterns and the stack structure,
the stack structure including electrode layers (EL, FIG. 4) and electrode interlayer insulating layers (IL1, FIG. 4) alternately stacked on the substrate,
the gate insulating layer including a blocking insulating layer (BK, IG. 5A) and charge storing patterns (TL), the blocking insulating layer being adjacent to the stack structure, the charge storing patterns being spaced apart from the stack structure and arranged along a surface of the blocking insulating layer (as seen) , the blocking insulating layer (BK) between the charge storing patterns (TL) and the stack structure (EL),
wherein as a distance to the blocking insulating layer decreases, widths of the charge storing patterns increase(looking at protruding portion of VP along the side surface of EL (i.e. from right side of FIG. 5A) , width of TL increases with decreasing distance of TL from BK, FIG. 5A).……
But PARK does not explicitly teach,
An electronic system, comprising: the semiconductor device …….
an input/output pad electrically connected to the peripheral circuit structure,
and a controller electrically connected to the semiconductor device through the input/output pad, the controller configured to control the semiconductor device.
But Zawodny teaches,
PNG
media_image4.png
536
534
media_image4.png
Greyscale
a peripheral circuit structure(including Row DECODE and Column DECODE, FIG. 1),
an input/output pad (109, Fig. 1) electrically connected to the peripheral circuit structure
and a controller (103) electrically connected to the semiconductor device (110) through the input/output pad, the controller configured to control the semiconductor device.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to form the peripheral circuit structure including ROW and COLUMN DECODE circuitry, according to teaching of Zawodny, in order to form a computing system including a memory device (i.e. electronic system) ( Zawodny para [0007]).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claim 7, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
wherein each of the vertical semiconductor patterns has silicon crystal grains, and a mean size of the silicon crystal grains is larger than a mean size of the charge storing patterns (claim 7).
Claims 13-19 are allowed.
With respect to claim 13, the prior art made of record does not teach or suggest either alone or in combination “…each of the vertical semiconductor patterns includes silicon crystal grains having a mean size that is larger than a mean size of the charge storing patterns” in further combination with the additionally claimed limitations, as they are claimed by the Applicant.
Regarding claim 13, Choi et al. (US 2021/0066343 A1) teaches,
PNG
media_image5.png
600
696
media_image5.png
Greyscale
A three-dimensional semiconductor memory device (FIG. 11C), comprising:
a peripheral circuit structure (514, para [0100]) ;
and a cell array structure (512, para [0100]) on the peripheral circuit structure, the cell array structure including a first substrate (520, para [0109]),
a source structure (source region 572, para [0109]) on the first substrate, a stack structure (stack of CL & 110, para [0040]) on the first substrate,
a planarization insulating layer (114, para [0041]), a plurality of vertical semiconductor patterns(120, para [0041] of channel structure CHS5, FIG. 11C), bit line pads (182, para [0052]), and a gate insulating layer (including 132B, 134P & 140, para [0045]- [0047], FIG. 5) between the plurality of vertical semiconductor patterns and the stack structure,
the first substrate including a cell array region (region of 520 where channel structure CHS5 is connected) and a connection region (region of 520 where common source pattern CSP is connected) disposed in a first direction,
the stack structure including electrode layers (CL) and electrode interlayer insulating layers (110) alternately stacked on the first substrate,
the planarization insulating layer (114) on the connection region (as seen) and covering an end portion of the stack structure (as seen);
the plurality of vertical semiconductor patterns on the cell array region (as defined) , the plurality of vertical semiconductor patterns penetrating the stack structure and the source structure (as seen), the plurality of vertical semiconductor patterns adjacent to the first substrate (as seen), the bit line pads (182, para [0052]) on the plurality of vertical semiconductor patterns, respectively,
wherein the gate insulating layer including a blocking insulating layer (132B, para [0046]) and charge storing patterns (134P, para [0042]), the blocking insulating layer is adjacent to the stack structure (Fig. 5) , the charge storing patterns are spaced apart from the stack structure (FIG. 5) and arranged along a surface of the blocking insulating layer (Fig. 5),
the blocking insulating layer is between the charge storing patterns and the stack structure(Fig. 5).
But CHOI fails to teach,
and each of the vertical semiconductor patterns includes silicon crystal grains having a mean size that is larger than a mean size of the charge storing patterns.
The other cited arts, either alone or in combination, fails to cure deficiencies of CHOI.
Claims 14-19 are allowed being dependent on claim 13.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.A.R/Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813