DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Amendments dated 04/13/2026 has been acknowledged and entered. Claim 1, 11 & 20 have been amended. Claims 21-25 are canceled. Claim 4 is withdrawn by applicant. No new claims are added . Claims 1-20 remain pending in application.
Response to Arguments
Applicant’s argument dated 04/13/2026 has been acknowledged but are moot since a new ground of rejection is made in view of new primary reference SHIN (US 20120012920 A1) and none of the arguments applies to SHIN and any other reference used in a combination of current rejections(see rejections below).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SHIN et al. (US 2012/0012920 A1).
Regarding claim 1, SHIN teaches,
PNG
media_image1.png
649
492
media_image1.png
Greyscale
PNG
media_image2.png
502
758
media_image2.png
Greyscale
A three-dimensional semiconductor memory device (FIGs. 1-2), comprising:
a stack structure including electrode layers (130a, para [0064]) and electrode interlayer insulating layers (insulation air gap pattern G1-G3, para [0057]) alternately stacked on a substrate (100, para [0042]);
vertical semiconductor patterns (112a, para [0042]) penetrating the stack structure; and
a gate insulating layer(including 122a, 124a & 126a, para [0063]) between the vertical semiconductor patterns and the stack structure,
wherein the gate insulating layer includes a blocking insulating layer (126a, para 0063]) and charge storing patterns (124a, para [0063]),
the blocking insulating layer is adjacent to the stack structure(FIG. 1),
wherein the charge storing patterns are spaced apart from the stack structure (by intervening blocking insulating layer 126a) and spaced apart from each other along a surface of the blocking insulating layer(vertical surface of 126a in FIG. 1) ,
wherein the blocking insulating layer between the charge storing patterns and the stack structure(Fig. 1),
and wherein each of the charge storing patterns has a first width (A-B as marked along the surface of 134, see FIG. 1 enlarged view above) and a second width (C-D as marked along surface of 124a) that is farther away from the surface of the blocking insulating layer in a direction perpendicular to the surface of the blocking insulating layer than the first width, the first width being greater than the second width (A-B>C-D).
Regarding claim 2, SHIN teaches the device of claim 1 and further teaches, wherein the charge storing patterns have a polygonal shape, when viewed in a plan view or a sectional view (A-B-C-D is polygonal shape)
Regarding claim 3, SHIN teaches the device of claim 1 and further teaches , wherein each of the charge storing patterns (124a) has a side surface (A-F) that is inclined with respect to a surface (E-F) of the blocking insulating layer (126a).
Regarding claim 5, SHIN teaches the device of claim 1 and further teaches, wherein each of the electrode layers has a first vertical length (1-2, see FIG. 1 as annotated below), each of the charge storing patterns has a second vertical length (3-4 as marked below), and the second vertical length is smaller than the first vertical length (1-2< 3-4).
PNG
media_image3.png
502
758
media_image3.png
Greyscale
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over SHIN et al. and further in view of PACHAMUTHU et al. (US 20160111434 A1).
Regarding claim 6, SHIN teaches the device of claim 1 and further teaches, wherein each of the charge storing patterns is a doped silicon crystal pattern or an undoped silicon crystal pattern.
But SHIN additionally teaches,
Charge storage layer 124a may be formed of silicon nitride (para [0071])
Meanwhile, PACHAMUTHU teaches,
charge storage regions 9 may comprise an insulating charge trapping material, such as silicon nitride segments and may be floating gates comprising semiconductor material (e.g., silicon) that may be formed by a metal induced crystallization process (see para [0028]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute silicon nitride with silicon formed by crystallization process (i.e. Silicon crystal) as a material of the charge trapping layer TL, according to teaching of PACHAMUTHU, since the court has held that a simple substitution of one known element for another (silicon crystal for silicon nitride) to obtain predictable results is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007). (Please see Smith v. Hayashi, 209 USPQ 754 (Bd. of Pat. Inter. 1980)).
Ordinary artisan would have been motivated to use crystalized silicon instead for charge trapping layer, in order to form a floating gate, as taught by PACHAMUTHU above.
Claim 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over SHIN et al. and further in view of PARK et all. (US 2020/0303390 A1).
Regarding claim 8, SHIN teaches the device of claim 1 but does not explicitly teaches, wherein the gate insulating layer further comprises a passivation layer, the passivation layer is between the charge storing patterns and the vertical semiconductor patterns, and the passivation layer covers the charge storing patterns.
But PARK teaches,
PNG
media_image4.png
704
544
media_image4.png
Greyscale
But PARK teaches,
gate insulating layer (VP) further comprises a passivation layer (FM, para [0057]), the passivation layer is between the charge storing patterns (TL) and the vertical semiconductor patterns (USP), and the passivation layer covers the charge storing patterns (FIG. 5A).
The charge storage layer TL may be crooked or have a nonlinear shape due to the filling insulating layer FM. Because the charge storage layer TL is formed crookedly or with a nonlinear shape…… the data storage part DSP may be less likely to suffer loss of data stored therein (para [0069]).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a passivation layer FM between the charge storage pattern 124a and the vertical semiconductor patter 130a, according to teaching of PARK, in order to form non-linear shape charge storage pattern to prevent loss of data stored therein, as taught by PARK above
Regarding claim 9, SHIN & PARK teaches the device of claim 8 and PARK further teaches , wherein the passivation layer comprises at least one of SiN, SiO, SiON, or a metal oxide material, and the passivation layer has a single-layered structure or a multi-layered structure(FM may include a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer, PARK, para [0052])..
Regarding claim 10, SHIN & PARK teaches the device of claim 8 and further teaches,wherein the gate insulating layer further comprises a tunnel insulating layer(TN, PARK, para [0051]) between the passivation layer (FM) and the vertical semiconductor patterns (USP).
Claims 11 is rejected under 35 U.S.C. 103 as being unpatentable over SHIN et al. in view of PARK et al. and further in view of SON et al. (US 20210066344 A1).
Regarding claim 11, SHIN & PARK teaches the device of claim 8 but does not explicitly teaches, further comprising: a source structure between the substrate and the stack structure, wherein the vertical semiconductor patterns penetrate the source structure and extend into the substrate, the gate insulating layer is below the source structure and between the vertical semiconductor patterns and the substrate, the source structure penetrates the gate insulating layer and is in contact with the vertical semiconductor patterns, the gate insulating layer further comprises dummy charge storing patterns below the source structure, and as a distance to the blocking insulating layer decrease, widths of the dummy charge storing patterns increase.
But SON teaches,
PNG
media_image5.png
764
590
media_image5.png
Greyscale
a source structure (380, para [0019], similar to SC2 in FIG. 5A of disclosure) between the substrate and the stack structure (stack of 414 & 165), wherein the vertical semiconductor patterns (240, para [0022], Fig. 4) penetrate the source structure and extend into the substrate (100, para [0019]), the gate insulating layer (including 230 & 280 , para [0022]) below the source structure (230 is extends below the 380) and between the vertical semiconductor patterns and the substrate, the source structure (380) penetrates the gate insulating layer ( in lateral direction) and is in contact with the vertical semiconductor patterns (as seen), the gate insulating layer further comprises dummy charge storing patterns (portion of 230 below 380) below the source structure,
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SHIN such that a source structure (380) between the substrate (100) and the stack structure (), wherein the vertical semiconductor patterns penetrate the source structure (380) and extend into the substrate and the gate insulating layer further comprises a gate insulating layer (230 below 380) below the source structure and between the vertical semiconductor patterns and the substrate, the source structure (380) penetrates the gate insulating layer and is in contact with the vertical semiconductor patterns , according to teaching of SON, in order to have memory cells having the characteristics of MLCs as taught by SON (para [0051]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. and further in view of PARK et al. (US 2020/0303390 A1)
Regarding claim 12, SHIN teaches the device of claim 1 but does not explicitly teaches, further comprising, wherein the gate insulating layer further comprises: a capping layer covering the charge storing patterns; a passivation layer covering the capping layer; and a tunnel insulating layer covering the passivation layer.
Meanwhile, PARK teaches,
the gate insulating layer further comprises: a capping layer (GI, FIG. 5A, para [0096]) covering the charge storing patterns (TL); a passivation layer (FM, para [0057]) covering the capping layer (GI); and a tunnel insulating layer (TN) covering the passivation layer (FM).
The charge storage layer TL may be crooked or have a nonlinear shape due to the filling insulating layer FM. Because the charge storage layer TL is formed crookedly or with a nonlinear
shape…… the data storage part DSP may be less likely to suffer loss of data stored therein (para [0069]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify SHIN’s gate insulating layer to further include a passivation layer FM and a dielectric pattern GI such that the gate insulating layer further comprises: a capping layer (GI, FIG. 5A, para [0096]) covering the charge storing patterns (TL/124a); a passivation layer (FM, para [0057]) covering the capping layer (GI); and a tunnel insulating layer (TN/122a) covering the passivation layer (FM), according to teaching of PARK, in order to form non-linear shape charge storage pattern to prevent loss of data stored therein, as taught by PARK above
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. by SHIN et al. (US 20120012920 A1) in view of PARK et all. (US 2020/0303390 A1) in view of Zawodny et al. (US 20180130515 A1)
Regarding claim 20, SHIN teaches,
PNG
media_image1.png
649
492
media_image1.png
Greyscale
a cell array structure includes a stack structure (130a, para [0064]) on the substrate (100), vertical semiconductor patterns (112a, para [0042]) penetrating the stack structure and placed adjacent to the substrate, and a gate insulating layer (including 122a, 124a & 126a, para [0063]) between the vertical semiconductor patterns and the stack structure,
wherein the stack structure includes electrode layers (130a, para [0064]) and electrode interlayer insulating layers (insulation air gap pattern G1-G3, para [0057]) alternately stacked on the substrate,
wherein the gate insulating layer includes a blocking insulating layer (126a, para 0063]) and charge storing patterns (124a, para [0063]),
wherein the blocking insulating layer is adjacent to the stack structure (FIG. 1),
wherein the charge storing patterns are spaced apart from the stack structure (Fig. 1) and spaced apart from each other along a surface of the blocking insulating layer (vertical surface of 126a in FIG. 1),
wherein the blocking insulating layer is between the charge storing patterns and the stack structure (FIG. 1),
and wherein each of the charge storing patterns has a first width (A-B as marked along the surface of 134, see FIG. 1 enlarged view above) and a second width (C-D as marked along surface of 124a) that is farther away from the surface of the blocking insulating layer in a direction perpendicular to the surface of the blocking insulating layer than the first width, the first width being greater than the second width (A-B>C-D).
But Shin does not explicitly teach,
An electronic system, comprising: a semiconductor device including a peripheral circuit structure, a cell array structure on the peripheral circuit structure, and an input/output pad electrically connected to the peripheral circuit structure; and a controller electrically connected to the semiconductor device through the input/output pad, the controller configured to control the semiconductor device
Meanwhile, PARK teaches,
…….a semiconductor device (three-dimensional semiconductor memory device, FIGs. 1-4, para [0012]) including a peripheral circuit structure (including ROW DCR and COL DCR, FIG. 1), a cell array structure (CAR, FIG. 1) on the peripheral circuit structure (FIG. 1), ……,
and Zawodny teaches,
PNG
media_image6.png
536
534
media_image6.png
Greyscale
A semiconductor device (memory array 110) an input/output pad (109, Fig. 1) electrically connected to a peripheral circuit structure(including Row DECODE and Column DECODE, FIG. 1),
and a controller (103) electrically connected to the semiconductor device (110) through the input/output pad, the controller configured to control the semiconductor device.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to incorporate the teaching of PARK and Zawodny into the cell array structure of SHIN such that an electronic system, comprising: a semiconductor device (memory array 110, Zawodny FIG. 1) including a peripheral circuit structure(including Row DECODE and Column DECODE, FIG. 1, Zawodny), the cell array structure (SHIN’s cell array structure) on the peripheral circuit structure and an input/output pad(109, Fig. 1, Zawodny) electrically connected to the peripheral circuit structure; and a controller (103, Zawodny ) electrically connected to the semiconductor device (110, Zawodny) through the input/output pad, the controller configured to control the semiconductor device, in order to form a computing system including a memory device ( Zawodny para [0007]).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to include all of the limitations of the base claim and any intervening claims.
With respect to claim 7, the prior art of record does not appear to teach, suggest, or provide motivation for combination to following limitation:
wherein each of the vertical semiconductor patterns has silicon crystal grains, and a mean size of the silicon crystal grains is larger than a mean size of the charge storing patterns (claim 7).
Claims 13-19 are allowed in previous office action.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. (FP 7.40)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Loke, can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.A.R/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights