DETAILED ACTION
This office action is in response to claims filed 1 May 2026.
Claims 1-25 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 1 May 2026 have been fully considered but they are not persuasive.
On pages 9-10, the applicant argues:
“Independent claim 1 has been amended to clarify that the claimed routing is performed by specific hardware in a processing core, not by a generic computer component, and not by a mental judgement…
“Under Step 2A, Prong 1, the amended claim does not recite a mental process…The amended claim is directed to on-core hardware circuitry that receives a thread-control message from a message arbiter and physically routes the message within a pair of hardware processing resources using selection circuitry. A person cannot practically perform, in the human mind, the claimed intra-core hardware operation of receiving a thread-control message in a graphics processing core and using MA-PR hardware circuitry router selection circuitry to steer that message to one of two hardware processing resources. The claim therefore does not fall within the mental-process grouping identified in MPEP 2106.04(a).
“The specification confirms that the claimed MA-PR router is a concrete hardware structure, not an abstract decision-making concept…These passages show that the amended claim is directed to a specific hardware routing architecture within a processing core.”
The examiner respectfully disagrees. The 2019 Revised Patent Subject Matter Eligibility Guidance (PEG) states that “examiners should take note that the recitation of generic computer components in a claim does not preclude that claim from reciting an abstract idea. For instance, if a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it is still in the mental processes grouping unless the claim limitation cannot practically be performed in the mind”. In other words, even if a claim limitation recites a limitation being performed using computer components, it may still be ineligible if that limitation could practically be performed in the mind. In the instant application, applicant has amended “processing resources” to recite “hardware processing resources”, and “arbiter-processing resource routers” to recite “arbiter-processing resource hardware circuitry routers” in an attempt to establish that the recited computer components are not “generic”. However, 1) simply changing the name of the processing resources or arbiter-processing resource routers to include the term “hardware” does not change the eligibility of the claim, as generic computer components are also assumed to be “hardware” and nowhere does the 2019 PEG preclude hardware from being considered generic computer components. Further, 2) the “arbiter-processing resource hardware circuitry router” still represents a “generic computer component” because the claim treats the “arbiter-processing resource hardware circuitry router” as essentially a generic black box, and does not give any detail as to how the hardware of the router actually accomplishes the aforementioned receiving of the thread control message and routing of the thread control message. In other words, the “arbiter-processing resource hardware circuitry router” is akin to any other generic computer component having any other name that is capable of performing those same steps, and there is no distinction in form or functionality between the claimed “arbiter-processing resource hardware circuitry router” over any other generic component.
Further, it is important to note that the rejection only establishes “arbitration” as a mental process. The applicant’s argument that “A person cannot practically perform, in the human mind, the claimed intra-core hardware operation of receiving a thread-control message in a graphics processing core and using MA-PR hardware circuitry router selection circuitry to steer that message to one of two hardware processing resources” (emphasis added) does not actually address whether or not “arbitration” can be practically performed in the human mind, and therefore does not reflect or address the rejection in the office action, which did not reject receiving the thread-control message and steering/routing that message to a destination as being mental processes capable of being performed in the human mind. Further, the claim does not actually recite actual delivery of the thread control message to a destination, only that arbitration is performed “such that the thread control message is delivered.” Arbitration may simply result in a decision that a particular thread control message should be delivered to a destination, but without explicitly and positively claiming delivery of that thread control message to the destination, this arbitration remains within the realm of a mental decision making process.
Therefore, the applicant’s argument is not persuasive.
On page 11, the applicant argues:
“Under Step 2A, Prong 2, even if the Office were to continue identifying some alleged abstract idea, the amended claim integrates any such idea into a practical application. The claimed MA-PR hardware circuitry is not merely a field-of-use limitation or an instruction to ‘apply’ routing on a computer. It is part of a particular graphics-processor architecture that addresses a technical scaling problem. The specification explains that parallel rendering graphics architectures run large and demanding workloads with increasing performance expectations, and that increasing compute throughput by increasing processing resources depends on scalability of the supporting architecture hierarchy…The specification further explains that routers are introduced to provide arbitration with the increased number of processing resources…The amended claim captures this technical solution by requiring per-pair MA-PR hardware circuitry routers, positioned between the message arbiter and corresponding pairs of hardware processing resources, that use selection circuitry for intra- pair routing of thread-control messages.
“Accordingly, the amended claim improves the operation and scalability of a graphics processing core itself. It does not merely use a computer as a tool to perform an abstract idea. Rather, it recites a particular arrangement of hardware processing resources, MA-PR hardware circuitry routers, selection circuitry, local shared cache sequencers, and instruction caches that cooperate within the processing core to support execution-thread routing and resource scalability. This is a technology-rooted improvement to computer hardware architecture, consistent with the type of computer-functionality improvement recognized as patent eligible under Enfish and the Alice/Mayo framework.”
The examiner respectfully disagrees. MPEP 2106.05(a) explains:
“If it is asserted that the invention improves upon conventional functioning of a computer, or upon conventional technology or technological processes, a technical explanation as to how to implement the invention should be present in the specification. That is, the disclosure must provide sufficient details such that one of ordinary skill in the art would recognize the claimed invention as providing an improvement…An indication that the claimed invention provides an improvement can include a discussion in the specification that identifies a technical problem and explains the details of an unconventional technical solution expressed in the claim, or identifies technical improvements realized by the claim.”
In the case of the instant application, applicant asserts that the claimed invention improves compute throughput of “large and demanding workloads.” However, the claims do not recite execution of any workload, so any improvement to the compute throughput of a workload is unclaimed, and therefore, unrealized by the claimed invention. In other words, in order for an improvement to the compute throughput of a workload by using MA-PR routers to be recognized, or realized, the claim must actually recite execution of the workload using the MA-PR routers; otherwise, the claim may simply be reciting exchanging of thread control messages with no requirement for workload execution.
In a similar way, since claims do not recite “scaling” of a graphics processing core, the claims cannot realize an improvement to scalability of the graphics processing core. For these reasons, the applicant’s argument is not persuasive.
On pages 11-12, the applicant argues:
“The claim also satisfies Step 2B. Considered individually and as an ordered combination, the amended limitations amount to significantly more than the alleged abstract idea. The office action treats the prior recitation of processing resources, routers, caches, and sequencers as generic environment or extra solution activity. See Office Action ¶10. But the amended claim recites a specific on-core hardware routing arrangement: a MA-PR hardware circuitry router interposed between a message arbiter and a corresponding pair of hardware processing resources, using selection circuitry to perform intra-pair routing of a thread-control message to a destination processing resource. The rejection does not establish that this particular hardware arrangement for scalable GPU-core message routing was well-understood, routine, and conventional.
“The dependent claims are patent eligible for at least the same reasons.”
The examiner respectfully disagrees. As discussed above in reference to Step 2A, Prongs 1 and 2, the claim fails to distinguish “MA-PR hardware circuitry router”, “message arbiter”, and “pairs of hardware processing resources” from generic computer components, and the “specific on-core hardware routing arrangement” simply describes the environment, comprising those generic computer components, that is linked to the use of the mental process of arbitration. MPEP 2106.05(h) states that such “limitations that amount to merely indicating a field of use or technological environment in which to apply a judicial exception do not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application”. Furthermore, it is important to note, that the overall “hardware arrangement for scalable GPU-core message routing” was not found to solely be well-understood, routine, and conventional, as the applicant argues. Only the steps of receiving a thread control message, and storing instructions of one or more instruction threads as representing well-understood, routine, and conventional activities. Therefore, the applicant’s argument is not persuasive.
On pages 12-17, the applicant makes arguments regarding the rejections made under 35 U.S.C. 102 and 103. However, since these arguments fail to specifically challenge the new reference (YOSHIDA, cited below) used to reject the newly amended limitations at issue, these arguments are moot.
Claim Objections
Claim 15 is objected to because of the following informalities: ”the pair of processing resources” should read “the pair of hardware processing resources”. Appropriate correction is required.
Examiner’s Note
Claims 4-5, 13, 18, and 23 were not rejected using prior art under 35 U.S.C. 102 or 35 U.S.C. 103. However, they are not objected to because they stand rejected under other statutes.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract ides (mental process) without significantly more.
Regarding claim 1, in step 1 of the 101 analysis set forth in MPEP 2106, the claim recites a system that arbitrates routing of a thread control message between processing resources. A system is one of the four statutory categories of invention.
In step 2A, prong 1 of the 101 analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
i. “arbitrate intra-pair routing of the thread control message between the corresponding pair of hardware processing resources” (a person can mentally arbitrate routing of a message by simply making a judgement of where the message should go (MPEP 2106.04(a)))
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea.
In step 2A, prong 2 of the 101 analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
ii. “A processor comprising: a processing core comprising: a plurality of hardware processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) hardware circuitry routers, wherein a respective MA-PR hardware circuitry router of the plurality of MA-PR hardware circuitry routers is interposed between a message arbiter and a corresponding pair of hardware processing resources of the plurality of hardware processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
iii. “a respective MA-PR router…is to utilize selection circuitry to receive…and to arbitrate” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
vi. “receive, from the message arbiter, a thread control message directed to a destination processing resource of the corresponding pair of hardware processing resources” (insignificant extra-solution activity of mere data gathering (MPEP 2106.05(g))).
v. “the thread control message is delivered to the destination processing resource” (insignificant extra-solution activity of mere data output (MPEP 2106.05(g))).
vi. “a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)))
vii. “a plurality of instruction caches (ICs)… wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of hardware processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
viii. “instruction caches (ICs) to store instructions of the one or more execution threads” (insignificant extra-solution activity of mere data storage (MPEP 2106.05(g))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In step 2B of the 101 analysis set forth in the 2019 PEG, the examiner has determined through reanalysis of the following limitations considered in step 2A prong 2, that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
ii. “A processor comprising: a processing core comprising: a plurality of hardware processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) hardware circuitry routers, wherein a respective MA-PR hardware circuitry router of the plurality of MA-PR hardware circuitry routers is interposed between a message arbiter and a corresponding pair of hardware processing resources of the plurality of hardware processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
iii. “a respective MA-PR router…is to utilize selection circuitry to receive…and to arbitrate” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
vi. “receive, from the message arbiter, a thread control message directed to a destination processing resource of the corresponding pair of hardware processing resources” (well-understood, routine, and conventional activity of receiving data over a network, (MPEP 2106.05(d)(II)).
v. “the thread control message is delivered to the destination processing resource” (well-understood, routine, and conventional activity of transmitting data over a network, (MPEP 2106.05(d)(II)).
vi. “a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)))
vii. “a plurality of instruction caches (ICs)… wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of hardware processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
viii. “instruction caches (ICs) to store instructions of the one or more execution threads” (well-understood, routine, and conventional activity of storing information in memory, (MPEP 2106.05(d)(II)).
Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.
Regarding claim 2, the additional element “the respective MA-PR hardware circuitry router comprises a router first in first out (FIFO) data structure for timing convergence, and a selection circuit” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “direct arbitration to the pair of hardware processing resources” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally direct arbitration by simply making a judgement of which resource to direct arbitration to (MPEP 2106.04(a))).
Regarding claim 3, the additional element “the plurality of LSC sequencers have direct connections to the plurality of processing resources” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 4, the additional element “the processing core comprises a plurality of message arbiter-LSC (MA-LSC) arbiters corresponding to the plurality of LSC sequencers, wherein a respective MA-LSC arbiter corresponds to the pair of processing resources” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “arbitrate routing of a LSC request from a respective processing resource of the pair of hardware processing resources to a corresponding LSC sequencer of the plurality of LSC sequencers” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally arbitrate request routing by simply making a judgement of which sequencer to route a request to(MPEP 2106.04(a))).
Regarding claim 5, the additional element “the respective MA-LSC arbiter comprises: sideband storage data structures corresponding to each processing resource of the pair of hardware processing resources; data storage data structures corresponding to each processing resource of the pair of hardware processing resources; a first multiplexer… second multiplexer… and a round robin arbiter… wherein the data storage data structures comprises first in first out (FIFO) data structures” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “select between the sideband storage data structures for output to a LSC sequencer sideband storage data structure… select between the data storage data structure for output to a LSC sequencer data storage data structure…direct traffic to the second multiplexer” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally select between different storage options by simply making a judgement of which option to choose, and can further mentally direct traffic by simply making a judgement of a destination for traffic (MPEP 2106.04(a))).
Regarding claim 6, the additional element “the plurality of hardware processing resources have direct connections to the plurality of ICs” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 7, the additional element “, wherein the processing core comprises a plurality of IC- processing resource (IC-PR) routers corresponding to the plurality of ICs, wherein a respective IC-PR router corresponds to the pair of hardware processing resources” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “arbitrate routing of an IC request between the pair of hardware processing resources to a corresponding IC of the plurality of ICs” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally arbitrate request routing by simply making a judgement of which resource or cache to route a request to (MPEP 2106.04(a))).
Regarding claim 8, the additional element “the plurality of ICs interface with a higher- level cache that is outside of the processing core” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 9, the additional element “the processor comprises a graphics processing unit (GPU)” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 10, in step 1 of the 101 analysis set forth in MPEP 2106, the claim recites a method that arbitrates routing of a thread control message between processing resources. A system is one of the four statutory categories of invention.
In step 2A, prong 1 of the 101 analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
i. “arbitrating…intra-pair routing of the thread control message between the corresponding pair of hardware processing resources such that the thread control message is delivered to the destination processing resource of the corresponding pair of hardware processing resources” (a person can mentally arbitrate routing of a message between resources by simply making a judgement of where the message should go (MPEP 2106.04(a)))
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea.
In step 2A, prong 2 of the 101 analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
ii. “receiving…a thread control message from the message arbiter, the thread control message directed to a destination processing resource of the corresponding pair of hardware processing resources” (insignificant extra-solution activity of mere data gathering (MPEP 2106.05(g))).
iii. “by a message arbiter-processing resource (MA-PR) hardware circuitry router of a processing core of a graphics processor hardware device” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
iv. “wherein the MA-PR hardware circuitry router is interposed between a message arbiter and a corresponding pair of hardware processing resources of a plurality of hardware processing resources of the processing core, and wherein the MA-PR hardware circuitry router utilizes selection circuitry” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
v. “wherein the corresponding pair of hardware processing resources are part of the plurality of hardware processing resources of the hardware processing core that are to execute one or more execution threads” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
vi. “by the MA-PR hardware circuitry router using the selection circuitry” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
vii. “accessing…based on the thread control message, an instruction cache (IC) of a plurality of ICs of the processing core to obtain an instruction of the one or more execution threads for execution by the destination processing resource” (insignificant extra-solution activity of mere data gathering (MPEP 2106.05(g))).
viii. “by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
ix. “the IC is to interface with a portion of the plurality of hardware processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
x. “interfacing…with a local shared cache (LSC) sequencer of a plurality of LSC sequencers of the processing core” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
xi. “by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
xii. “the interfacing to communicate with at least one LSC of the processing core as part of execution of the instruction” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In step 2B of the 101 analysis set forth in the 2019 PEG, the examiner has determined through reanalysis of the following limitations considered in step 2A prong 2, that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
ii. “receiving…a thread control message from the message arbiter, the thread control message directed to a destination processing resource of the corresponding pair of hardware processing resources” ((well-understood, routine, and conventional activity of receiving data over a network (MPEP 2106.05(d)(II))).
iii. “by a message arbiter-processing resource (MA-PR) hardware circuitry router of a processing core of a graphics processor hardware device” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
iv. “wherein the MA-PR hardware circuitry router is interposed between a message arbiter and a corresponding pair of hardware processing resources of a plurality of hardware processing resources of the processing core, and wherein the MA-PR hardware circuitry router utilizes selection circuitry” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
v. “wherein the corresponding pair of hardware processing resources are part of the plurality of hardware processing resources of the hardware processing core that are to execute one or more execution threads” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
vi. “by the MA-PR hardware circuitry router using the selection circuitry” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
vii. “accessing…based on the thread control message, an instruction cache (IC) of a plurality of ICs of the processing core to obtain an instruction of the one or more execution threads for execution by the destination processing resource” (well-understood, routine, and conventional activity of receiving data over a network (MPEP 2106.05(d)(II))).
viii. “by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
ix. “the IC is to interface with a portion of the plurality of hardware processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
x. “interfacing…with a local shared cache (LSC) sequencer of a plurality of LSC sequencers of the processing core” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
xi. “by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
xii. “the interfacing to communicate with at least one LSC of the processing core as part of execution of the instruction” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.
Regarding claims 11-15, they comprise limitations similar to those of claims 1-4, and 6-7, and are therefore rejected for similar rationale.
Regarding claims 16-20, they comprise limitations similar to those of claims 1-2, 4, and 6-7. They are therefore rejected for similar rationale.
Regarding claims 21-25, they comprise limitations similar to those of claims 10, and 12-15. They are therefore rejected for similar rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-9, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of DEBURCHGRAEVE Pub. No.: US 2022/0276902 A1 (hereafter DEBURCHGRAEVE), in view of YOSHIDA et. al. Pub. No.: US 2013/0028083 A1 (hereafter YOSHIDA).
MESWANI and DEBURCHGRAEVE were cited previously.
Regarding claim 1, MESWANI teaches the invention substantially as claimed, including:
A processor ([0014] Processing system 100) comprising:
a processing core comprising: a plurality of hardware processing resources ([0014] Multiple processor cores 105, 106, 107, 108 (i.e., each individual processor core represents a “resource” and the collection of processing cores together represent a “processing core”)) to execute one or more execution threads ([0020] Access requests are generated by threads that are executing on the processing system 200);
…a respective MA-PR hardware circuitry router…is interposed between…a corresponding pair of hardware processing resources of the plurality of processing resources and is to utilize selection circuitry to receive…a thread control message directed to a destination processing resource of the corresponding pair of hardware processing resources ([0020] Access requests (i.e., “thread control messages”) are generated by threads that are executing on the processing system 200) and to arbitrate intra-pair routing of the thread control message between the corresponding pair of hardware processing resources such that the thread control message is delivered to the destination processing resource ([0022] The master controller 225 (i.e., “MA-PR router” that is interposed between hardware processor 205 and memory 210-220) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests (i.e., providing access requests to selected local controllers comprises “utilizing selection circuitry” to provide, or direct, the requests to destinations) to the corresponding memory modules 210, 215, 220. The control information may include information indicating priorities associated with the access requests or corresponding threads, prefetch requests determined based on access patterns associated with different threads, and the like (i.e., master controller at least schedules, or “arbitrates routing of” access requests));
a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of hardware processing resources ([0015] The shared cache 115 may be referred to as a last level cache (LLC) if it is the highest level cache in the cache hierarchy implemented by the processing system 100. Some embodiments of the shared cache 115 are implemented as an L2 cache. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controllers 235 represents a “local shared cache sequencer” because it provides an “interface” between a processor and a shared L2 cache as illustrated in Fig. 2)); and
a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108 (i.e., local caches, representing “instruction caches” associate, or “interface” with processing core resources to store instructions associated with the executing threads)).
While MESWANI discusses a master controller that schedules threads for execution across multiple processing cores, MESWANI does not explicitly teach that
a plurality of message arbiter-processing resource (MA-PR) hardware circuitry routers, wherein a respective MA-PR hardware circuitry router of the plurality of MA-PR hardware circuitry routers is interposed between…a corresponding pair of hardware processing resources of the plurality of hardware processing resources
However, in analogous art that similarly teaches using global schedulers to schedule tasks for execution, DEBURCHGRAEVE teaches:
a plurality of message arbiter-processing resource (MA-PR) hardware circuitry routers, wherein a respective MA-PR hardware circuitry router of the plurality of MA-PR hardware circuitry routers is interposed between…a corresponding pair of hardware processing resources of the plurality of hardware processing resources ([0007] The method comprises a task computation comprising: executing a scheduler (i.e., “MA-PR router”) by a current master thread of the set, determining by the current master thread an available thread (i.e., threads execute on processing unit resources) for performing a selected current task of a set of one or more tasks of the scheduler [0059] A first and second scheduler (i.e., plural MA-PR routers) may be provided. The first scheduler may be associated with a first set of tasks and the second scheduler may be associated with a second set of tasks. The first and second sets of tasks may be part of a same larger set of tasks that is split into the first and second sets of tasks. This may for example be useful when the first scheduler has too many tasks (e.g. the larger set) associated to it and the serial execution of master's functions becomes a bottleneck that prevents the concurrent use of all available slave threads in the pool. The two schedulers/master threads can be started so that they can process respective tasks of the larger set (i.e., plural master thread schedulers schedule tasks on threads of processing resources))
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined DEBURCHGRAEVE’s teaching of multiple master schedulers that schedule tasks on threads executing on processing resources, with MESWANI’s teaching of a global controller that schedules tasks on threads executing on processing resources, to realize, with a reasonable expectation of success, a system that schedules tasks on threads executing on processing resources, as in MESWANI, using a plurality of master schedulers, as in DEBURCHGRAEVE. A person having ordinary skill would have been motivated to make this combination to share task scheduling responsibilities between multiple master schedulers to reduce bottlenecks (DEBURCHGRAEVE [0059]).
While MESWANI and DEBURCHGRAEVE discuss routing of thread control messages between hardware resources, they do not explicitly teach:
a respective MA-PR hardware circuitry router of the plurality of MA-PR hardware circuitry routers is interposed between a message arbiter and a corresponding pair of hardware processing resources of the plurality of hardware processing resources and is to utilize selection circuitry to receive, from the message arbiter, a thread control message;
However, in analogous art that similarly discusses routing of messages between hardware resource destinations, YOSHIDA teaches:
a respective MA-PR hardware circuitry router of the plurality of MA-PR hardware circuitry routers is interposed between a message arbiter and a corresponding pair of hardware processing resources of the plurality of hardware processing resources and is to utilize selection circuitry to receive, from the message arbiter, a [control message] ([0087] A router according to the present disclosure includes a plurality of data storage sections which store input data, and an arbiter which arbitrates transmission of the data that is stored in those data storage sections. The data that has been entered into the router is once stored in any of those data storage sections. The arbiter compares the availability of at least one of the plurality of data storage sections with respect to data that is stored in that data storage section and that shares at least a part of a transmission path to the availability of another data storage section in adjacent router with respect to that data, thereby determining, based on a result of the comparison, whether or not to output that data. [0088] For example, if an address attribute such as the destination address or the source address has been defined for given data, then the arbiter compares, between two adjacent routers, pieces of information indicating the degrees to which data having the same address attribute as the data that is stored in each data storage section uses the data storage section, thereby determining, based on a result of the comparison, whether or not to output that data (i.e., arbiter interposes itself between adjacent routers along a path between bus master hardware resources and memory hardware resources, and transmits an indication, as a “control message” to output data to the next adjacent router));
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined YOSHIDA’s teaching of an arbiter interposed between routers that route messages between hardware resources, with the combination of MESWANI and DEBURCHGRAEVE’s teaching of routers that route messages between resources, to realize, with a reasonable expectation of success, a system that uses routers to route thread control messages between hardware resources, as in MESWANI and DEBURCHGRAEVE, which are arbitrated between using an arbiter, as in YOSHIDA. A person having ordinary skill would have been motivated to make this combination to better transfer data along transmission paths that avoid traffic flow interference (YOSHIDA [0005]).
Regarding claim 7, MESWANI further teaches:
the processing core comprises a plurality of IC- processing resource (IC-PR) routers corresponding to the plurality of ICs, wherein a respective IC-PR router corresponds to the pair of hardware processing resources and is to arbitrate routing of an IC request between the pair of hardware processing resources to a corresponding IC of the plurality of ICs ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controller 230 to L1 memory 210 represents an IC-processing resource router corresponding to a respective local cache)).
Regarding claim 8, MESWANI further teaches:
the plurality of ICs interface with a higher-level cache that is outside of the processing core ([0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively (i.e., L3 cache representing a “higher-level cache” interfaces with local cache in L1 memory via master controller 225, as illustrated in Fig. 2)).
Regarding claim 9, MESWANI further teaches:
the processor comprises a graphics processing unit (GPU) ([0014] The processing system 100 may be used to implement…a graphics processing unit (GPU)).
Regarding claims 16 and 20, they comprise limitations similar to claims 1, and 7 respectively, and are therefore rejected for similar rationale.
Claims 2, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of DEBURCHGRAEVE, in view of YOSHIDA, as applied to claims 1, and 16 above, and in further view of HARWOOD et al. Pub. No.: US 2020/0142753 A1 (hereafter HARWOOD).
HARWOODS was cited previously.
Regarding claim 2, MESWANI further teaches:
the respective MA-PR router comprises…a selection circuit to direct arbitration to the pair of hardware processing resources ([0022] The master controller 225 (i.e., “MA-PR router”) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220. The control information may include information indicating priorities associated with the access requests or corresponding threads, prefetch requests determined based on access patterns associated with different threads, and the like (i.e., assigning priorities to access requests causes selection of, or arbitration between the resources used to execute the access requests)).
While MESWANI, DEBURCHGRAEVE, and YOSHIDA discuss a master scheduler that performs arbitration between resources, they do not explicitly teach:
the respective MA-PR hardware circuitry router comprises a router first in first out (FIFO) data structure for timing convergence.
However, in analogous art, HARWOOD teaches:
the respective MA-PR hardware circuitry router comprises a router first in first out (FIFO) data structure for timing convergence ([0033] The service request and associated provisioning specifications are stored in the request queue pending scheduling by the global scheduler and request queue module 141 (i.e., global scheduler and request queue module 141 comprises an “MA-PR” router combined with a FIFO request queue that enables control of the timing of scheduling the requests)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined HARWOOD’s teaching a global scheduler combined with a FIFO queue, with the combination of MESWANI, DEBURCHGRAEVE, and YOSHIDA’s teaching of a global scheduler having a selection circuit to arbitrate scheduling of resources, to realize, with a reasonable expectation of success, a system comprising a global scheduler combined with a FIFO data structure, as in HARWOOD, which is used to arbitrate scheduling of resources, as in MESWANI and DEBURCHGRAEVE. A person having ordinary skill would have been motivated to make this combination to provide an efficient distributed computing environment for high performance computing applications (HARWOOD [0004]).
Regarding claim 17, it comprises limitations similar to that of claim 2, and is therefore rejected for similar rationale.
Claims 3, 6, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of DEBURCHGRAEVE, in view of YOSHIDA, as applied to claims 1, and 16 above, and in further view of Kilian et al. Pub. No.: US 2006/0248276 A1 (hereafter KILIAN).
KILIAN was cited previously.
Regarding claim 3, while MESWANI, DEBURCHGRAEVE, and YOSHIDA discuss processing resources having access to shared caches, they do not explicitly teach:
the plurality of LSC sequencers have direct connections to the plurality of processing resources.
However, in analogous art that similarly teaches processing resources having access to shared cache, KILIAN teaches:
the plurality of LSC sequencers have direct connections to the plurality of processing resources ([0020] Cache manager 225 (i.e., “LCS sequencer”) provides a cache implementation with a variety of functionality and services. Applications 130 may create a local cache 205 or shared cache 210 for their cached objects 220 and 223 with the aid of cache manager 225. In one embodiment, cache manager 225 may include a cache region factory for creating local or shared cache regions, which may then be populated with cached objects 220 and 223 (i.e., Cache manager 225 resides within, and is therefore directly connected to a worker node representing a processing resource)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined KILIAN’s teaching of a cache manager of a shared cache having a direct connection to a processing resource, with the combination of MESWANI, DEBURCHGRAEVE, and YOSHIDA’s teaching of a cache controller managing access to a shared cache, to realize, with a reasonable expectation of success, a system having a cache controller managing access to a shared cache, as in MESWANI, DEBURCHGRAEVE, and YOSHIDA, which is directly connected to a processing resource, as in KILIAN. A person having ordinary skill would have been motivated to make this combination to ensure operation of the cache managers are more robust and reliable and capable of sustainable, uninterrupted operation (KILIAN [0004]).
Regarding claim 6, while MESWANI, DEBURCHGRAEVE, and YOSHIDA discuss processing resources having access to local caches, they do not explicitly teach:
the plurality of processing resources have direct connections to the plurality of ICs.
However, in analogous art that similarly teaches processing resources having access to local cache, KILIAN teaches:
the plurality of processing resources have direct connections to the plurality of ICs ([0020] Cache manager 225 provides a cache implementation with a variety of functionality and services. Applications 130 may create a local cache 205 or shared cache 210 for their cached objects 220 and 223 with the aid of cache manager 225. In one embodiment, cache manager 225 may include a cache region factory for creating local or shared cache regions, which may then be populated with cached objects 220 and 223 (i.e., local cache 205 resides within, and are therefore directly connected to the worker nodes, representing “processing resources”)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined KILIAN’s teaching of local caches having a direct connection to a processing resource, with the combination of MESWANI, DEBURCHGRAEVE, and YOSHIDA’s teaching of a cache controller managing access to a shared cache, to realize, with a reasonable expectation of success, a system having a cache controller managing access to a local cache, as in MESWANI and DEBURCHGRAEVE, and YOSHIDA, which is directly connected to a processing resource, as in KILIAN. A person having ordinary skill would have been motivated to make this combination to ensure operation of the cache managers are more robust and reliable and capable of sustainable, uninterrupted operation (KILIAN [0004]).
Regarding claim 19, it comprises limitations similar to claim 6, and is therefore rejected for similar rationale.
Claims 10, 15, 21, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MESWANI, in view of YOSHIDA.
Regarding claim 10, MESWANI teaches:
A method comprising:
receiving, by a message arbiter-processing resource (MA-PR) hardware circuitry router of a processing core ([0014] Multiple processor cores 105, 106, 107, 108 (i.e., each individual processor core represents a “resource” and the collection of processing cores together represent a “processing core”). ([0022] The master controller 225 (i.e., “MA-PR router”) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests (i.e., “thread control messages”) to the corresponding memory modules 210, 215, 220) of a graphics processor hardware device ([0014] The processing system 100 may be used to implement…a graphics processing unit (GPU)), wherein the MA-PR hardware circuitry router is interposed between…a corresponding pair of hardware processing resources of a plurality of hardware processing resources of the processing core, and wherein the MA-PR hardware circuitry router utilizes selection circuitry, a thread control message ([0020] Access requests (i.e., “thread control messages”) are generated by threads that are executing on the processing system 200)…the thread control message directed to a destination processing resource of the corresponding pair of hardware processing resources, wherein the corresponding pair of hardware processing resources are part of the plurality of hardware processing resources of the hardware processing core that are to execute one or more execution threads ([0022] The master controller 225 (i.e., MA-PR router that is interposed between hardware processor 205 and memory 210-220) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests (i.e., providing access requests to selected local controllers comprises “utilizing selection circuitry” to provide, or direct, the requests to destinations) to the corresponding memory modules 210, 215, 220. The control information may include information indicating priorities associated with the access requests or corresponding threads, prefetch requests determined based on access patterns associated with different threads, and the like (i.e., master controller at least schedules, or “arbitrates routing of” access requests));
arbitrating, by the MA-PR hardware circuitry router using the selection circuitry, intra-pair routing of the thread control message between the corresponding pair of hardware processing resources such that the thread control message is delivered to the destination processing resource of the corresponding pair of hardware processing resources ([0022] The master controller 225 (i.e., “MA-PR router”) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220. The control information may include information indicating priorities associated with the access requests or corresponding threads, prefetch requests determined based on access patterns associated with different threads, and the like (i.e., master controller at least schedules, or “arbitrates routing of” access requests generated by at least two threads executing on at least two processing cores of the processing system)));
accessing, by the destination processing resource based on the thread control message, an instruction cache (IC) of a plurality of ICs of the processing core to obtain an instruction of the one or more execution threads for execution by the destination processing resource, wherein the IC is to interface with a portion of the plurality of hardware processing resources ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108 (i.e., local instruction caches interfaced with processing resources are accessed in the process of executing access requests of threads to obtain data or instructions)); and
interfacing, by the destination processing resource, with a local shared cache (LSC) sequencer of a plurality of LSC sequencers of the processing core, the interfacing to communicate with at least one LSC of the processing core as part of execution of the instruction ([0015] The shared cache 115 may be referred to as a last level cache (LLC) if it is the highest level cache in the cache hierarchy implemented by the processing system 100. Some embodiments of the shared cache 115 are implemented as an L2 cache. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controllers 235 represents a “local shared cache sequencer” because it provides an “interface” between a processor and a shared L2 cache as illustrated in Fig. 2)).
While MESWANI and DEBURCHGRAEVE discuss routing of thread control messages between hardware resources, they do not explicitly teach:
receiving, by a message arbiter-processing resource (MA-PR) hardware circuitry router of a processing core of a graphics processor hardware device, wherein the MA-PR hardware circuitry router is interposed between a message arbiter and a corresponding pair of hardware processing resources of a plurality of hardware processing resources of the processing core, and wherein the MA-PR hardware circuitry router utilizes selection circuitry, a [control message] from the message arbiter;
However, in analogous art that similarly discusses routing of messages between hardware resource destinations, YOSHIDA teaches:
receiving, by a message arbiter-processing resource (MA-PR) hardware circuitry router of a processing core of a graphics processor hardware device, wherein the MA-PR hardware circuitry router is interposed between a message arbiter and a corresponding pair of hardware processing resources of a plurality of hardware processing resources of the processing core, and wherein the MA-PR hardware circuitry router utilizes selection circuitry, a [control message] from the message arbiter ([0087] A router according to the present disclosure includes a plurality of data storage sections which store input data, and an arbiter which arbitrates transmission of the data that is stored in those data storage sections. The data that has been entered into the router is once stored in any of those data storage sections. The arbiter compares the availability of at least one of the plurality of data storage sections with respect to data that is stored in that data storage section and that shares at least a part of a transmission path to the availability of another data storage section in adjacent router with respect to that data, thereby determining, based on a result of the comparison, whether or not to output that data. [0088] For example, if an address attribute such as the destination address or the source address has been defined for given data, then the arbiter compares, between two adjacent routers, pieces of information indicating the degrees to which data having the same address attribute as the data that is stored in each data storage section uses the data storage section, thereby determining, based on a result of the comparison, whether or not to output that data (i.e., arbiter interposes itself between adjacent routers along a path between bus master hardware resources and memory hardware resources, and transmits an indication, as a “control message” to output data to the next adjacent router));
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined YOSHIDA’s teaching of an arbiter interposed between routers that route messages between hardware resources, with MESWANI’s teaching of routers that route messages between resources, to realize, with a reasonable expectation of success, a system that uses routers to route thread control messages between hardware resources, as in MESWANI, which are arbitrated between using an arbiter, as in YOSHIDA. A person having ordinary skill would have been motivated to make this combination to better transfer data along transmission paths that avoid traffic flow interference (YOSHIDA [0005]).
Regarding claim 15, MESWANI further teaches:
the processing core comprises a plurality of IC- processing resource (IC-PR) routers corresponding to the plurality of ICs, wherein a respective IC-PR router corresponds to the pair of processing resources and is to arbitrate routing of an IC request between the pair of hardware processing resources to a corresponding IC of the plurality of ICs ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controller 230 to L1 memory 210 represents an IC-processing resource router corresponding to a respective local cache)).
Regarding claims 21, and 25, they comprise limitations similar to those of claims 10, and 15 respectively, and are therefore rejected for similar rationale.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of YOSHIDA, as applied to claim 10 above, and in further view of HARWOOD.
Regarding claim 11, it comprises limitations similar to those of claims 1 and 2, and is therefore rejected for similar rationale.
Claims 12, 14, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of YOSHIDA, as applied to claims 10, and 21 above, and in further view of KILIAN.
Regarding claims 12, 14, 22, and 24, they comprise limitations similar to claims 3, and 6, and are therefore rejected for similar rationale.
Conclusion
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/MICHAEL W AYERS/Primary Examiner, Art Unit 2195
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