DETAILED ACTION
This office action is in response to claims filed 15 November 2022.
Claims 1-25 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
Claims 4-5, 13, 18, and 23 were not rejected using prior art under 35 U.S.C. 102 or 35 U.S.C. 103. However, they are not objected to because they stand rejected under other statutes.
Claim Objections
Claim 5 is objected to because of the following informalities: “second multiplexer” should read “a second multiplexer”, “data storage data structure” should read “data storage data structures”, and “data structure” should read “data storage data structure”. Appropriate correction is required.
Claims 10 and 21 are objected to because of the following informalities (line numbers correspond to claim 10): In lines 5-6, “part of plurality of processing resources” should read “part of a plurality of processing resources”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 5,
a. In line 10, it is not particularly pointed out or distinctly claimed what is meant by “a round robin arbiter to as input to the second multiplexer” because this sentence is incomplete. It is not clear what the round robin scheduler inputs to the second multiplexer. For examination purposes, the examiner will interpret the round robin arbiter as directing traffic to the second multiplexer, as described in [0401] of the specification.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract ides (mental process) without significantly more.
Regarding claim 1, in step 1 of the 101 analysis set forth in MPEP 2106, the claim recites a system that arbitrates routing of a thread control message between processing resources. A system is one of the four statutory categories of invention.
In step 2A, prong 1 of the 101 analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
i. “arbitrate routing of a thread control message from a message arbiter between the pair of processing resources” (a person can mentally arbitrate routing of a message by simply making a judgement of where the message should go (MPEP 2106.04(a)))
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea.
In step 2A, prong 2 of the 101 analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
ii. “A processor comprising: a processing core comprising: a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
iii. “a respective MA-PR router…is to arbitrate” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
iv. “a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)))
v. “a plurality of instruction caches (ICs)… wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
vi. “instruction caches (ICs) to store instructions of the one or more execution threads” (insignificant extra-solution activity of mere data storage (MPEP 2106.05(g))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In step 2B of the 101 analysis set forth in the 2019 PEG, the examiner has determined through reanalysis of the following limitations considered in step 2A prong 2, that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
ii. “A processor comprising: a processing core comprising: a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
iii. “a respective MA-PR router…is to arbitrate” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
iv. “a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)))
v. “a plurality of instruction caches (ICs)… wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
vi. “instruction caches (ICs) to store instructions of the one or more execution threads” (well-understood, routine, and conventional activity of storing information in memory, (MPEP 2106.05(d)(II)) ().
Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.
Regarding claim 2, the additional element “the respective MA-PR router comprises a router first in first out (FIFO) data structure for timing convergence, and a selection circuit” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “direct arbitration to the pair of processing resources” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally direct arbitration by simply making a judgement of which resource to direct arbitration to (MPEP 2106.04(a))).
Regarding claim 3, the additional element “the plurality of LSC sequencers have direct connections to the plurality of processing resources” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 4, the additional element “the processing core comprises a plurality of message arbiter-LSC (MA-LSC) arbiters corresponding to the plurality of LSC sequencers, wherein a respective MA-LSC arbiter corresponds to the pair of processing resources” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “arbitrate routing of a LSC request from a respective processing resource of the pair of processing resources to a corresponding LSC sequencer of the plurality of LSC sequencers” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally arbitrate request routing by simply making a judgement of which sequencer to route a request to(MPEP 2106.04(a))).
Regarding claim 5, the additional element “the respective MA-LSC arbiter comprises: sideband storage data structures corresponding to each processing resource of the pair of processing resources; data storage data structures corresponding to each processing resource of the pair of processing resources; a first multiplexer… second multiplexer… and a round robin arbiter… wherein the data structures comprises first in first out (FIFO) data structures” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “select between the sideband storage data structures for output to a LSC sequencer sideband storage data structure… select between the data storage data structure for output to a LSC sequencer data storage data structure” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally select between different storage options by simply making a judgement of which option to choose(MPEP 2106.04(a))). Further, the additional element “to as input to the second multiplexer” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (insignificant extra-solution activity of mere data output (MPEP 2106.05(g)), and under step 2B it does not amount to significantly more than the judicial exception (well-understood, routine and conventional activity of transmitting data over a network (MPEP 2106.05(d)(II)).
Regarding claim 6, the additional element “the plurality of processing resources have direct connections to the plurality of ICs” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 7, the additional element “, wherein the processing core comprises a plurality of IC- processing resource (IC-PR) routers corresponding to the plurality of ICs, wherein a respective IC-PR router corresponds to the pair of processing resources” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). Further, the additional element “arbitrate routing of an IC request between the pair of processing resources to a corresponding IC of the plurality of ICs” does not render the claim patent eligible because under step 2A prong 1, it recites a judicial exception (mental process) (a person can mentally arbitrate request routing by simply making a judgement of which resource or cache to route a request to (MPEP 2106.04(a))).
Regarding claim 8, the additional element “the plurality of ICs interface with a higher- level cache that is outside of the processing core” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 9, the additional element “the processor comprises a graphics processing unit (GPU)” does not render the claim patent eligible because under step 2A prong 2, it does not integrate the judicial exception into a practical application (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)), and under step 2B it does not amount to significantly more than the judicial exception (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Regarding claim 10, in step 1 of the 101 analysis set forth in MPEP 2106, the claim recites a method that arbitrates routing of a thread control message between processing resources. A system is one of the four statutory categories of invention.
In step 2A, prong 1 of the 101 analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, covers a mental process but for recitation of generic computer components:
i. “arbitrating…routing of the thread control message between the pair of processing resources such that the thread control message is delivered to the destination processing resource of the pair of processing resources” (a person can mentally arbitrate routing of a message by simply making a judgement of where the message should go (MPEP 2106.04(a)))
If claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process but for the recitation of generic computer components, then it falls within the mental process grouping of abstract ideas. Accordingly, the claim “recites” an abstract idea.
In step 2A, prong 2 of the 101 analysis set forth in MPEP 2106, the examiner has determined that the following additional elements do not integrate this judicial exception into a practical application:
ii. “receiving…a thread control message directed to a destination processing resource of a pair of processing resources corresponding to the MA-PR router” (insignificant extra-solution activity of mere data gathering (MPEP 2106.05(g))).
iii. “receiving, by a message arbiter-processing resource (MA-PR) router of a processing core of a graphics processor hardware device” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
iv. “wherein the pair of processing resources are part of plurality of processing resources of the processing core that are to execute one or more execution threads” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
v. “arbitrating, by the MA-PR router” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
vi. “accessing…based on the thread control message, an instruction cache (IC) of a plurality of ICs of the processing core to obtain an instruction of the one or more execution threads for execution by the destination processing resource” (insignificant extra-solution activity of mere data gathering (MPEP 2106.05(g))).
vii. “accessing, by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
viii. “the IC is to interface with a portion of the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
ix. “interfacing…with a local shared cache (LSC) sequencer of a plurality of LSC sequencers of the processing core” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
x. “interfacing by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
xi. “the interfacing to communicate with at least one LSC of the processing core as part of execution of the instruction” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Since the claim does not contain any other additional elements that are indicative of integration into a practical application, the claim is “directed” to an abstract idea.
In step 2B of the 101 analysis set forth in the 2019 PEG, the examiner has determined through reanalysis of the following limitations considered in step 2A prong 2, that the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
ii. “receiving…a thread control message directed to a destination processing resource of a pair of processing resources corresponding to the MA-PR router” (well-understood, routine, and conventional activity of receiving data over a network (MPEP 2106.05(d)(II))).
iii. “receiving, by a message arbiter-processing resource (MA-PR) router of a processing core of a graphics processor hardware device” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
iv. “wherein the pair of processing resources are part of plurality of processing resources of the processing core that are to execute one or more execution threads” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
v. “arbitrating, by the MA-PR router” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
vi. “accessing…based on the thread control message, an instruction cache (IC) of a plurality of ICs of the processing core to obtain an instruction of the one or more execution threads for execution by the destination processing resource” (well-understood, routine, and conventional activity of receiving data over a network (MPEP 2106.05(d)(II))).
vii. “accessing, by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
viii. “the IC is to interface with a portion of the plurality of processing resources” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
ix. “interfacing…with a local shared cache (LSC) sequencer of a plurality of LSC sequencers of the processing core” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
x. “interfacing by the destination processing resource” (Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (MPEP 2106.05(f))).
xi. “the interfacing to communicate with at least one LSC of the processing core as part of execution of the instruction” (generally links the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
Considering the additional elements individually and in combination, and the claim as a whole, the additional elements do not provide significantly more than the abstract idea. Therefore, the claim is not patent eligible.
Regarding claims 11-15, they comprise limitations similar to those of claims 1-4, and 6-7, and are therefore rejected for similar rationale.
Regarding claims 16-20, they comprise limitations similar to those of claims 1-2, 4, and 6-7. They are therefore rejected for similar rationale.
Regarding claims 21-25, they comprise limitations similar to those of claims 10, and 12-15. They are therefore rejected for similar rationale.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 10, 15, 21, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MESWANI et al. Pub. No.: US 2017/0083474 A1 (hereafter MESWANI).
Regarding claim 10, MESWANI teaches:
A method comprising:
receiving, by a message arbiter-processing resource (MA-PR) router of a processing core ([0014] Multiple processor cores 105, 106, 107, 108 (i.e., each individual processor core represents a “resource” and the collection of processing cores together represent a “processing core”). ([0022] The master controller 225 (i.e., “MA-PR router”) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests (i.e., “thread control messages”) to the corresponding memory modules 210, 215, 220) of a graphics processor hardware device ([0014] The processing system 100 may be used to implement…a graphics processing unit (GPU)), a thread control message directed to a destination processing resource of a pair of processing resources corresponding to the MA-PR router, wherein the pair of processing resources are part of plurality of processing resources of the processing core that are to execute one or more execution threads ([0020] Access requests (i.e., “thread control messages”) are generated by threads that are executing on the processing system 200);
arbitrating, by the MA-PR router, routing of the thread control message between the pair of processing resources such that the thread control message is delivered to the destination processing resource of the pair of processing resources ([0022] The master controller 225 (i.e., “MA-PR router”) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220. The control information may include information indicating priorities associated with the access requests or corresponding threads, prefetch requests determined based on access patterns associated with different threads, and the like (i.e., master controller at least schedules, or “arbitrates routing of” access requests generated by at least two threads executing on at least two processing cores of the processing system)));
accessing, by the destination processing resource based on the thread control message, an instruction cache (IC) of a plurality of ICs of the processing core to obtain an instruction of the one or more execution threads for execution by the destination processing resource, wherein the IC is to interface with a portion of the plurality of processing resources ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108 (i.e., local instruction caches interfaced with processing resources are accessed in the process of executing access requests of threads to obtain data or instructions)); and
interfacing, by the destination processing resource, with a local shared cache (LSC) sequencer of a plurality of LSC sequencers of the processing core, the interfacing to communicate with at least one LSC of the processing core as part of execution of the instruction ([0015] The shared cache 115 may be referred to as a last level cache (LLC) if it is the highest level cache in the cache hierarchy implemented by the processing system 100. Some embodiments of the shared cache 115 are implemented as an L2 cache. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controllers 235 represents a “local shared cache sequencer” because it provides an “interface” between a processor and a shared L2 cache as illustrated in Fig. 2)).
Regarding claim 15, MESWANI further teaches:
the processing core comprises a plurality of IC- processing resource (IC-PR) routers corresponding to the plurality of ICs, wherein a respective IC-PR router corresponds to the pair of processing resources and is to arbitrate routing of an IC request between the pair of processing resources to a corresponding IC of the plurality of ICs ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controller 230 to L1 memory 210 represents an IC-processing resource router corresponding to a respective local cache)).
Regarding claims 21, and 25, they comprise limitations similar to those of claims 10, and 15 respectively, and are therefore rejected for similar rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-9, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of DEBURCHGRAEVE Pub. No.: US 2022/0276902 A1 (hereafter DEBURCHGRAEVE).
Regarding claim 1, MESWANI teaches the invention substantially as claimed, including:
A processor ([0014] Processing system 100) comprising:
a processing core comprising: a plurality of processing resources ([0014] Multiple processor cores 105, 106, 107, 108 (i.e., each individual processor core represents a “resource” and the collection of processing cores together represent a “processing core”)) to execute one or more execution threads ([0020] Access requests are generated by threads that are executing on the processing system 200);
…a respective MA-PR router…corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources ([0022] The master controller 225 (i.e., “MA-PR router”) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests (i.e., “thread control messages”) to the corresponding memory modules 210, 215, 220. The control information may include information indicating priorities associated with the access requests or corresponding threads, prefetch requests determined based on access patterns associated with different threads, and the like (i.e., master controller at least schedules, or “arbitrates routing of” access requests generated by at least two threads executing on at least two processing cores of the processing system));
a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources ([0015] The shared cache 115 may be referred to as a last level cache (LLC) if it is the highest level cache in the cache hierarchy implemented by the processing system 100. Some embodiments of the shared cache 115 are implemented as an L2 cache. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controllers 235 represents a “local shared cache sequencer” because it provides an “interface” between a processor and a shared L2 cache as illustrated in Fig. 2)); and
a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108 (i.e., local caches, representing “instruction caches” associate, or “interface” with processing core resources to store instructions associated with the executing threads)).
While MESWANI discusses a master controller that schedules threads for execution across multiple processing cores, MESWANI does not explicitly teach that
a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources
However, in analogous art that similarly teaches using global schedulers to schedule tasks for execution, DEBURCHGRAEVE teaches:
a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources ([0007] The method comprises a task computation comprising: executing a scheduler (i.e., “MA-PR router”) by a current master thread of the set, determining by the current master thread an available thread (i.e., threads execute on processing unit resources) for performing a selected current task of a set of one or more tasks of the scheduler [0059] A first and second scheduler (i.e., plural MA-PR routers) may be provided. The first scheduler may be associated with a first set of tasks and the second scheduler may be associated with a second set of tasks. The first and second sets of tasks may be part of a same larger set of tasks that is split into the first and second sets of tasks. This may for example be useful when the first scheduler has too many tasks (e.g. the larger set) associated to it and the serial execution of master's functions becomes a bottleneck that prevents the concurrent use of all available slave threads in the pool. The two schedulers/master threads can be started so that they can process respective tasks of the larger set (i.e., plural master thread schedulers schedule tasks on threads of processing resources))
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined DEBURCHGRAEVE’s teaching of multiple master schedulers that schedule tasks on threads executing on processing resources, with MESWANI’s teaching of a global controller that schedules tasks on threads executing on processing resources, to realize, with a reasonable expectation of success, a system that schedules tasks on threads executing on processing resources, as in MESWANI, using a plurality of master schedulers, as in DEBURCHGRAEVE. A person having ordinary skill would have been motivated to make this combination to share task scheduling responsibilities between multiple master schedulers to reduce bottlenecks (DEBURCHGRAEVE [0059]).
Regarding claim 7, MESWANI further teaches:
the processing core comprises a plurality of IC- processing resource (IC-PR) routers corresponding to the plurality of ICs, wherein a respective IC-PR router corresponds to the pair of processing resources and is to arbitrate routing of an IC request between the pair of processing resources to a corresponding IC of the plurality of ICs ([0015] Some embodiments of the processing system 100 include local caches 110, 111, 112, 113 that are referred to collectively as the “local caches 110-113.” Each of the processor cores 105-108 is associated with a corresponding one of the local caches 110-113. For example, the local caches 110-113 may be L1 caches for caching instructions or data that may be accessed by one or more of the processor cores 105-108. [0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively. The master controller 225 also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220 (i.e., local controller 230 to L1 memory 210 represents an IC-processing resource router corresponding to a respective local cache)).
Regarding claim 8, MESWANI further teaches:
the plurality of ICs interface with a higher-level cache that is outside of the processing core ([0022] A master controller 225 receives access requests from the processor 205 and selectively provides the access requests to local controllers 230, 235, 240 that are associated with the memory modules 210, 215, 220, respectively (i.e., L3 cache representing a “higher-level cache” interfaces with local cache in L1 memory via master controller 225, as illustrated in Fig. 2)).
Regarding claim 9, MESWANI further teaches:
the processor comprises a graphics processing unit (GPU) ([0014] The processing system 100 may be used to implement…a graphics processing unit (GPU)).
Regarding claims 16 and 20, they comprise limitations similar to claims 1, and 7 respectively, and are therefore rejected for similar rationale.
Claims 2, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of DEBURCHGRAEVE, as applied to claims 1, and 16 above, and in further view of HARWOOD et al. Pub. No.: US 2020/0142753 A1 (hereafter HARWOOD).
Regarding claim 2, MESWANI further teaches:
the respective MA-PR router comprises…a selection circuit to direct arbitration to the pair of processing resources ([0022] The master controller 225 (i.e., “MA-PR router”) also provides control information to the local controllers 230, 235, 240, which can use the control information to schedule access requests to the corresponding memory modules 210, 215, 220. The control information may include information indicating priorities associated with the access requests or corresponding threads, prefetch requests determined based on access patterns associated with different threads, and the like (i.e., assigning priorities to access requests causes selection of, or arbitration between the resources used to execute the access requests)).
While MESWANI and DEBURCHGRAEVE discuss a master scheduler that performs arbitration between resources, they do not explicitly teach:
the respective MA-PR router comprises a router first in first out (FIFO) data structure for timing convergence.
However, in analogous art, HARWOOD teaches:
the respective MA-PR router comprises a router first in first out (FIFO) data structure for timing convergence ([0033] The service request and associated provisioning specifications are stored in the request queue pending scheduling by the global scheduler and request queue module 141 (i.e., global scheduler and request queue module 141 comprises an “MA-PR” router combined with a FIFO request queue that enables control of the timing of scheduling the requests)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined HARWOOD’s teaching a global scheduler combined with a FIFO queue, with the combination of MESWANI and DEBURCHGRAEVE’s teaching of a global scheduler having a selection circuit to arbitrate scheduling of resources, to realize, with a reasonable expectation of success, a system comprising a global scheduler combined with a FIFO data structure, as in HARWOOD, which is used to arbitrate scheduling of resources, as in MESWANI and DEBURCHGRAEVE. A person having ordinary skill would have been motivated to make this combination to provide an efficient distributed computing environment for high performance computing applications (HARWOOD [0004]).
Regarding claim 17, it comprises limitations similar to that of claim 2, and is therefore rejected for similar rationale.
Claims 3, 6, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, in view of DEBURCHGRAEVE, as applied to claims 1, and 16 above, and in further view of Kilian et al. Pub. No.: US 2006/0248276 A1 (hereafter KILIAN).
Regarding claim 3, while MESWANI and DEBURCHGRAEVE discuss processing resources having access to shared caches, they do not explicitly teach:
the plurality of LSC sequencers have direct connections to the plurality of processing resources.
However, in analogous art that similarly teaches processing resources having access to shared cache, KILIAN teaches:
the plurality of LSC sequencers have direct connections to the plurality of processing resources ([0020] Cache manager 225 (i.e., “LCS sequencer”) provides a cache implementation with a variety of functionality and services. Applications 130 may create a local cache 205 or shared cache 210 for their cached objects 220 and 223 with the aid of cache manager 225. In one embodiment, cache manager 225 may include a cache region factory for creating local or shared cache regions, which may then be populated with cached objects 220 and 223 (i.e., Cache manager 225 resides within, and is therefore directly connected to a worker node representing a processing resource)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined KILIAN’s teaching of a cache manager of a shared cache having a direct connection to a processing resource, with the combination of MESWANI and DEBURCHGRAEVE’s teaching of a cache controller managing access to a shared cache, to realize, with a reasonable expectation of success, a system having a cache controller managing access to a shared cache, as in MESWANI and DEBURCHGRAEVE, which is directly connected to a processing resource, as in KILIAN. A person having ordinary skill would have been motivated to make this combination to ensure operation of the cache managers are more robust and reliable and capable of sustainable, uninterrupted operation (KILIAN [0004]).
Regarding claim 6, while MESWANI and DEBURCHGRAEVE discuss processing resources having access to local caches, they do not explicitly teach:
the plurality of processing resources have direct connections to the plurality of ICs.
However, in analogous art that similarly teaches processing resources having access to local cache, KILIAN teaches:
the plurality of processing resources have direct connections to the plurality of ICs ([0020] Cache manager 225 provides a cache implementation with a variety of functionality and services. Applications 130 may create a local cache 205 or shared cache 210 for their cached objects 220 and 223 with the aid of cache manager 225. In one embodiment, cache manager 225 may include a cache region factory for creating local or shared cache regions, which may then be populated with cached objects 220 and 223 (i.e., local cache 205 resides within, and are therefore directly connected to the worker nodes, representing “processing resources”)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to have combined KILIAN’s teaching of local caches having a direct connection to a processing resource, with the combination of MESWANI and DEBURCHGRAEVE’s teaching of a cache controller managing access to a shared cache, to realize, with a reasonable expectation of success, a system having a cache controller managing access to a local cache, as in MESWANI and DEBURCHGRAEVE, which is directly connected to a processing resource, as in KILIAN. A person having ordinary skill would have been motivated to make this combination to ensure operation of the cache managers are more robust and reliable and capable of sustainable, uninterrupted operation (KILIAN [0004]).
Regarding claim 19, it comprises limitations similar to claim 6, and is therefore rejected for similar rationale.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, as applied to claim 10 above, and in further view of HARWOOD.
Regarding claim 11, it comprises limitations similar to those of claims 1 and 2, and is therefore rejected for similar rationale.
Claims 12, 14, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over MESWANI, as applied to claims 10, and 21 above, and in further view of Kilian.
Regarding claims 12, 14, 22, and 24, they comprise limitations similar to claims 3, and 6, and are therefore rejected for similar rationale.
Conclusion
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/MICHAEL W AYERS/Primary Examiner, Art Unit 2195