DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicants’ submission filed on 4/24/2026 has been entered.
Response to Amendment
Acknowledgement is made of the amendment filed on 4/24/2026 in which claims 1, 7-8, 12, and 18-20 were amended. Claims 6 and 17 were cancelled and no new claims were added. Therefore
claims 1-5, 7-16, and 18-20 are pending examination below.
Response to Arguments
Applicants’ arguments filed 4/24/2026 have been fully considered but they are not persuasive. Applicant argues “to the extent there are processors in the sub-systems 140a, 140b, the processor cannot control power outside its own sub-system and thus cannot control power supply to the first and second systems which are separately disposed and that in Kurian the processor PMU 106 of the alleged ''second electronic device'' and including an ''always on'' component supplies power to other devices 140a, 140b. In claim 1, the processor of the chipset supplies power to other devices 310, 320 (including an always on component).” The examiner disagrees. Kurian ¶73 states that child PMUs can request the main PMU for power state changes, which reasonably discloses that the subsystems 140a/b via the child PMUs/processors can control the power supply outside of its own subsystem. Applicant argues “Kurian' s paragraphs 37 and 41 describe operations in different states, it is not appropriate to apply the operations described in Kurian's paragraphs 37 and 41 to the two operations in the second power state (i.e. the same power state), as described in amended Claim 1 of the present invention, and, since the examiner cited paragraph 41 of Kurian with respect to the first power state of Claim 1, it is deemed inappropriate to cite the same paragraph 41 of Kurian for both the first and second power states (i.e., for different power states), and Kurian does not disclose receiving different interrupts when the battery level is higher than or equal to or lower than a specific level in the second power state, as set forth in amended claim 1 of the present invention.” The examiner disagrees. It is ¶41 that discloses the first power state and ¶37 that discloses the second power state. The examiner only mentioned ¶41 again for claims 6/17 in order to show that Kurian discloses that the OS receives the battery related information for the second component. The examiner also notes that under the broadest reasonable interpretation the applicant’s “interrupts” are reasonably defined as any kind of signal within the system. Kurian ¶42 discloses the second state and what happens when the battery is higher than or equal to a specific level. ¶55-56 disclose what happens in the second power state when the battery level is lower than a specific level. The rejection is maintained below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-5, 7-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kurian et al. US 20200264691 in view of Bhat et al. US 20230029696.
With regards to claims 1, 12, and 20 Kurian discloses an electronic device [Fig. 1A device 100] comprising:
a battery [Battery 120];
memory [Memory 152];
a charging circuit coupled to the battery [PM circuitry 108 and ¶31 "the PM circuitry 108 may harvest energy from the power source 118, e.g., to charge the battery 120"];
at least one first electronic component coupled to the charging circuit [Fig. 1b Subsystem 140b is coupled to PM circuitry 108 through Main PMU 106];
at least one second electronic component coupled to the charging circuit and the battery
and including an always-on electronic component [Main PMU 106 which is part of subsystem 102 and ¶26 “For purposes of this disclosure, the subsystem 102 may also be referred to as a main subsystem, an always ON subsystem”],
wherein the at least one first electronic component includes electronic components except for the second electronic component [Fig 1a]; and
a chipset disposed separately from the at least one first electronic component and the at least one second electronic component, coupled to the at least one first electronic component and the at least one second electronic component [Subsystem 140a is separate but coupled with the 1st component 140b via the power rails 192a/b to the 2nd component 106], and
including at least one processor [Processor 150],
wherein the at least one processor is configured to: execute an operating system [¶64 “a child PMU 142 may operate only during active power states, and therefore, in an example, a part of the operation of the child PMU 142 may be software driven (e.g., by a processor of the corresponding subsystem 140)” which discloses the presence of an operating system, where the operation of the system is software driven, which is executed by the processor],
when an operating system-related state is a first power state in which the processor operates to supply power to the at least one first electronic component and the at least one second electronic component, receive battery-related information from the at least one second electronic component [¶41 "the main PMU 106 may notify distinct child PMUs 142 when the battery level reaches a pre-configured threshold. For example, the main PMU 106 may notify a child PMU 142 a warning message when the battery level drops to a threshold (but not yet critically low) during an active power state in which a subsystem 140 managed by the child PMU 142 is operational"],
when the operating system-related state is a second power state in which the processor operates to supply power to the processor and the memory and a level of the battery is higher than a specific level, receive a first interrupt configured to change the second power state to the first power state from the at least one second electronic component [¶42 discloses the system being in the “second power state”, the battery level increasing up to a threshold, then receiving a notification (claimed interrupt) to transition to the first power state],
when the operating system-related state is the second power state and the level of the battery is equal to or lower than the specific level, receive a second interrupt configured to terminate execution of the operating system from the at least one second electronic component [¶55 discloses being in the second power state and the battery running lower than a non-critical threshold, receiving an interrupt, and then pausing or aborting pending tasks].
Kurian fails to explicitly disclose when the operating system-related state is a third power state, operate to supply power only to the at least one second electronic component.
However, Bhat discloses when the operating system-related state is a third power state, operate to supply power only to the at least one second electronic component [Fig 1 LPI (low power island) subsystem 110 (claimed second electronic component) which includes processor 124 and TCM (tightly coupled memory) 130, and ¶22 “The LPI subsystem 110 supports “always-on” features that are expected to function even when the primary subsystems 108(A)-108(E) are inactive in a low-power mode” where the primary subsystems 108A-E read on the claimed first electronic component(s) and where the LPI being always-on means that power is supplied to both the processor and memory of the subsystem during the low power mode or claimed third power state].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the power management systems of Kurian with Bhat to control different power modes in order to reduce power consumption and extend battery life.
Claims 12 and 20 are rejected for similar reasons as claim 1 above, a detailed discussion is avoided for brevity.
With regards to claims 2 and 13 the combination discloses the electronic device of claim 1, wherein the at least one processor is electrically coupled to the battery [Kurian Fig. 1A processor 150 coupled to the battery 120], and
wherein the at least one processor is further configured to: receive the battery-related information from the at least one second electronic component among the at least one first electronic component and the at least one second electronic component [¶41 above where battery related information is sent from the Main PMU 106 (claimed second electronic component)to the Subsystem140a which includes the processor].
Claim 13 is rejected for similar reasons as claim 2 above, a detailed discussion is avoided for brevity.
With regards to claims 3 and 14, the combination discloses the electronic device of claim 1, further comprising: an input device [Kurian Wakeup events 170 and ¶39 "The wake-up events 170 may be external asynchronous wake events (e.g., generated based on external input via the I/O 118), generated by the RTC/Timers 114, and/or the like. Based on the wake-up events 170, the main PMU 106 may transition the device 100 from a sleep state to an active state (e.g., may turn on one or more of the child PMUs 142"],
wherein the at least one second electronic component comprises an input device integrated circuit (IC) configured to control the input device [Kurian ¶39 above where the wakeup events 170/I/O 118 (claimed input devices) received by the PMU 106 (claimed second electronic component) allow the PMU 106 to control different functions of the device].
Claim 14 is rejected for similar reasons as claim 3 above, a detailed discussion is avoided for brevity.
With regards to claims 4 and 15, the combination discloses the electronic device of claim 1, wherein while the operating system-related state is the second power state, the at least one first electronic component is turned off and the at least one second electronic component is turned on [Kurian ¶25 “One or more components (e.g., all the components) of the subsystems 140a and/or 140b (claimed first electronic devices) may be powered OFF (e.g., in an inactive state), when the device 100 is in the sleep state (e.g., in a deep sleep state)”and ¶68 "In sleep states, the bare essential components (e.g., components that generate asynchronous events for system operation, alarms, timers, environment sensing events, the main PMU 106 (claimed second electronic device), the PM circuitry 108, etc.) may be powered ON"].
Claim 15 is rejected for similar reasons as claim 4 above, a detailed discussion is avoided for brevity.
With regards to claims 5 and 16, the combination discloses the electronic device of claim 1, wherein the third power state comprises a deep sleep state [Kurian ¶69 "The sleep states may, for example, have different levels (deep sleep state, hibernation state, regular sleep state, light sleep state, one or more low power states, etc.)"].
Claim 16 is rejected for similar reasons as claim 5 above, a detailed discussion is avoided for brevity.
With regards to claims 7 and 18, the combination discloses the electronic device of claim 6, further comprising an input device, wherein the at least one processor is further configured to: when the operating system-related state is the second power state, and the level of the battery is higher than the specific level, receive the first interrupt configured to change the second power state to the first power state from the at least one second electronic component by control of the input device, and change the operating system-related state from the second power state to the first power state based on the first interrupt [Kurian ¶56 "Upon reception of such an interrupt, each child PMU 142 may decide, based on the pending tasks versus the available energy, to either complete the remaining task, or to store its current state in retention storage and transition to a sleep state. Once the battery 120 has harvested enough energy (e.g., from the power source 118), the main PMU 106 may then wake up the device 100 from the sleep state to an active state, and the pended tasks may be completed by the corresponding child subsystem 140"].
Claim 18 is rejected for similar reasons as claim 7 above, a detailed discussion is avoided for brevity.
With regards to claims 8 and 19, the combination discloses the electronic device of claim 7, wherein the specific level is a level set to terminate the operating system [¶57 "Upon a critical state-of-charge condition (e.g., when the battery power is lower than a critical threshold), the main PMU 106 may override the child PMUs 142, and may force a transition to a predefined sleep state"].
Claim 19 is rejected for similar reasons as claim 8 above, a detailed discussion is avoided for brevity.
With regards to claim 9, the combination discloses the electronic device of claim 1, wherein the at least one processor is further configured to: execute a first program to control the at least one second electronic component [¶55 above where the interrupt command from the main PMU 106 is transmitted which reads on the "first program" where "program" is taken to mean software including one or more instructions as defined in the applicant’s specification ¶55],
execute at least one second program supported by the operating system [¶55 above where the child PMU 142 receives the interrupt command and makes a decision],
execute at least one third program being an application program [¶52 "the device 100 may operate in more than one active states. For example, upon the device 100 entering a first active state (e.g., a regular active state discussed in FIG. 2), a child PMU 142 may be in charge of transitioning to a specialized second active power state (e.g., a high active state discussed in FIG. 2), requesting (e.g., to the main PMU 106) power rails 192 to be selectively powered ON or OFF, optimizing operating conditions (e.g., via DVFS) given the application's requirements, etc." disclosing that the device executes different programs/applications while sufficient power is available within the system], and
execute a fourth program to communicate with the first program, the at least one second program, and the at least one third program [¶41 above where the battery level is determined and communicated between the main PMU 106 and at least one child PMU 142, where each of the above "programs" would be run/stopped as a result of the battery level].
With regards to claim 10, the combination discloses the electronic device of claim 9, wherein the at least one processor is further configured to: based on the execution of the fourth program, obtain the battery-related information from the first program [As disclosed above in ¶41, the fourth program obtains the battery level/related information], and
based on the execution of the fourth program, provide the battery-related information to at least one of the at least one second program and the at least one third program [As disclosed above, where the fourth program obtains the battery level, and then based on the level of the battery the second program receives the interrupt command and the third program (being other applications) are either allowed to keep running or are terminated based on the battery level].
With regards to claim 11, the combination discloses the electronic device of claim 9, wherein the at least one processor is further configured to: obtain the interrupt based on the execution of the first program [¶55 above where the interrupt command is obtained],
transmit the interrupt to the at least one second program based on the execution the first program [¶55 above where the interrupt command is transmitted between the main PMU 106 and a child PMU 142], and
terminate the operating system based on the execution of the at least one second program [¶70 "the device 100 may be in such sleep state for most of the time (e.g., more than 95% of the time, about 99% of the time, etc.), during which all the child PMUs 142 and all the subsystems 140 are be turned OFF" where turned OFF reasonably reads on the claimed terminate the operating system and where the termination would only need to be performed during a time where the battery level is at a certain threshold].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nathaniel Instone whose telephone number is (571)272-1563. The examiner can normally be reached M-F 8-4 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julian Huffman can be reached at 571-272-2147. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN J INSTONE/ Examiner, Art Unit 2859
/NATHANIEL R PELTON/ Primary Examiner, Art Unit 2859
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